//
// Copyright (c) 2015 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARGPIO_H_INC_
#define ___ARGPIO_H_INC_

// Register GPIO_N_VM_00_0
#define GPIO_N_VM_00_0                  _MK_ADDR_CONST(0x0)
#define GPIO_N_VM_00_0_SECURE                   0x0
#define GPIO_N_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_00_0_WORD_COUNT                       0x1
#define GPIO_N_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM1_SHIFT)
#define GPIO_N_VM_00_0_VM1_RANGE                        1:0
#define GPIO_N_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM2_SHIFT)
#define GPIO_N_VM_00_0_VM2_RANGE                        3:2
#define GPIO_N_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM3_SHIFT)
#define GPIO_N_VM_00_0_VM3_RANGE                        5:4
#define GPIO_N_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM4_SHIFT)
#define GPIO_N_VM_00_0_VM4_RANGE                        7:6
#define GPIO_N_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM5_SHIFT)
#define GPIO_N_VM_00_0_VM5_RANGE                        9:8
#define GPIO_N_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM6_SHIFT)
#define GPIO_N_VM_00_0_VM6_RANGE                        11:10
#define GPIO_N_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM7_SHIFT)
#define GPIO_N_VM_00_0_VM7_RANGE                        13:12
#define GPIO_N_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM8_SHIFT)
#define GPIO_N_VM_00_0_VM8_RANGE                        15:14
#define GPIO_N_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_00_0
#define GPIO_N_SCR_00_0                 _MK_ADDR_CONST(0x4)
#define GPIO_N_SCR_00_0_SECURE                  0x0
#define GPIO_N_SCR_00_0_SCR                     0
#define GPIO_N_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR7_SHIFT)
#define GPIO_N_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR6_SHIFT)
#define GPIO_N_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR5_SHIFT)
#define GPIO_N_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR4_SHIFT)
#define GPIO_N_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR3_SHIFT)
#define GPIO_N_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR2_SHIFT)
#define GPIO_N_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR1_SHIFT)
#define GPIO_N_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR0_SHIFT)
#define GPIO_N_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7W_SHIFT)
#define GPIO_N_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6W_SHIFT)
#define GPIO_N_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5W_SHIFT)
#define GPIO_N_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4W_SHIFT)
#define GPIO_N_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3W_SHIFT)
#define GPIO_N_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2W_SHIFT)
#define GPIO_N_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1W_SHIFT)
#define GPIO_N_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0W_SHIFT)
#define GPIO_N_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7R_SHIFT)
#define GPIO_N_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6R_SHIFT)
#define GPIO_N_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5R_SHIFT)
#define GPIO_N_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4R_SHIFT)
#define GPIO_N_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3R_SHIFT)
#define GPIO_N_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2R_SHIFT)
#define GPIO_N_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1R_SHIFT)
#define GPIO_N_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0R_SHIFT)
#define GPIO_N_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_01_0
#define GPIO_N_VM_01_0                  _MK_ADDR_CONST(0x8)
#define GPIO_N_VM_01_0_SECURE                   0x0
#define GPIO_N_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_01_0_WORD_COUNT                       0x1
#define GPIO_N_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM1_SHIFT)
#define GPIO_N_VM_01_0_VM1_RANGE                        1:0
#define GPIO_N_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM2_SHIFT)
#define GPIO_N_VM_01_0_VM2_RANGE                        3:2
#define GPIO_N_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM3_SHIFT)
#define GPIO_N_VM_01_0_VM3_RANGE                        5:4
#define GPIO_N_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM4_SHIFT)
#define GPIO_N_VM_01_0_VM4_RANGE                        7:6
#define GPIO_N_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM5_SHIFT)
#define GPIO_N_VM_01_0_VM5_RANGE                        9:8
#define GPIO_N_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM6_SHIFT)
#define GPIO_N_VM_01_0_VM6_RANGE                        11:10
#define GPIO_N_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM7_SHIFT)
#define GPIO_N_VM_01_0_VM7_RANGE                        13:12
#define GPIO_N_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM8_SHIFT)
#define GPIO_N_VM_01_0_VM8_RANGE                        15:14
#define GPIO_N_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_01_0
#define GPIO_N_SCR_01_0                 _MK_ADDR_CONST(0xc)
#define GPIO_N_SCR_01_0_SECURE                  0x0
#define GPIO_N_SCR_01_0_SCR                     0
#define GPIO_N_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR7_SHIFT)
#define GPIO_N_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR6_SHIFT)
#define GPIO_N_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR5_SHIFT)
#define GPIO_N_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR4_SHIFT)
#define GPIO_N_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR3_SHIFT)
#define GPIO_N_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR2_SHIFT)
#define GPIO_N_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR1_SHIFT)
#define GPIO_N_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR0_SHIFT)
#define GPIO_N_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7W_SHIFT)
#define GPIO_N_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6W_SHIFT)
#define GPIO_N_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5W_SHIFT)
#define GPIO_N_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4W_SHIFT)
#define GPIO_N_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3W_SHIFT)
#define GPIO_N_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2W_SHIFT)
#define GPIO_N_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1W_SHIFT)
#define GPIO_N_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0W_SHIFT)
#define GPIO_N_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7R_SHIFT)
#define GPIO_N_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6R_SHIFT)
#define GPIO_N_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5R_SHIFT)
#define GPIO_N_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4R_SHIFT)
#define GPIO_N_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3R_SHIFT)
#define GPIO_N_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2R_SHIFT)
#define GPIO_N_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1R_SHIFT)
#define GPIO_N_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0R_SHIFT)
#define GPIO_N_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_02_0
#define GPIO_N_VM_02_0                  _MK_ADDR_CONST(0x10)
#define GPIO_N_VM_02_0_SECURE                   0x0
#define GPIO_N_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_02_0_WORD_COUNT                       0x1
#define GPIO_N_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM1_SHIFT)
#define GPIO_N_VM_02_0_VM1_RANGE                        1:0
#define GPIO_N_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM2_SHIFT)
#define GPIO_N_VM_02_0_VM2_RANGE                        3:2
#define GPIO_N_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM3_SHIFT)
#define GPIO_N_VM_02_0_VM3_RANGE                        5:4
#define GPIO_N_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM4_SHIFT)
#define GPIO_N_VM_02_0_VM4_RANGE                        7:6
#define GPIO_N_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM5_SHIFT)
#define GPIO_N_VM_02_0_VM5_RANGE                        9:8
#define GPIO_N_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM6_SHIFT)
#define GPIO_N_VM_02_0_VM6_RANGE                        11:10
#define GPIO_N_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM7_SHIFT)
#define GPIO_N_VM_02_0_VM7_RANGE                        13:12
#define GPIO_N_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM8_SHIFT)
#define GPIO_N_VM_02_0_VM8_RANGE                        15:14
#define GPIO_N_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_02_0
#define GPIO_N_SCR_02_0                 _MK_ADDR_CONST(0x14)
#define GPIO_N_SCR_02_0_SECURE                  0x0
#define GPIO_N_SCR_02_0_SCR                     0
#define GPIO_N_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR7_SHIFT)
#define GPIO_N_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR6_SHIFT)
#define GPIO_N_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR5_SHIFT)
#define GPIO_N_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR4_SHIFT)
#define GPIO_N_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR3_SHIFT)
#define GPIO_N_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR2_SHIFT)
#define GPIO_N_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR1_SHIFT)
#define GPIO_N_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR0_SHIFT)
#define GPIO_N_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7W_SHIFT)
#define GPIO_N_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6W_SHIFT)
#define GPIO_N_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5W_SHIFT)
#define GPIO_N_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4W_SHIFT)
#define GPIO_N_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3W_SHIFT)
#define GPIO_N_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2W_SHIFT)
#define GPIO_N_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1W_SHIFT)
#define GPIO_N_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0W_SHIFT)
#define GPIO_N_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7R_SHIFT)
#define GPIO_N_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6R_SHIFT)
#define GPIO_N_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5R_SHIFT)
#define GPIO_N_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4R_SHIFT)
#define GPIO_N_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3R_SHIFT)
#define GPIO_N_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2R_SHIFT)
#define GPIO_N_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1R_SHIFT)
#define GPIO_N_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0R_SHIFT)
#define GPIO_N_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_03_0
#define GPIO_N_VM_03_0                  _MK_ADDR_CONST(0x18)
#define GPIO_N_VM_03_0_SECURE                   0x0
#define GPIO_N_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_03_0_WORD_COUNT                       0x1
#define GPIO_N_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM1_SHIFT)
#define GPIO_N_VM_03_0_VM1_RANGE                        1:0
#define GPIO_N_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM2_SHIFT)
#define GPIO_N_VM_03_0_VM2_RANGE                        3:2
#define GPIO_N_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM3_SHIFT)
#define GPIO_N_VM_03_0_VM3_RANGE                        5:4
#define GPIO_N_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM4_SHIFT)
#define GPIO_N_VM_03_0_VM4_RANGE                        7:6
#define GPIO_N_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM5_SHIFT)
#define GPIO_N_VM_03_0_VM5_RANGE                        9:8
#define GPIO_N_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM6_SHIFT)
#define GPIO_N_VM_03_0_VM6_RANGE                        11:10
#define GPIO_N_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM7_SHIFT)
#define GPIO_N_VM_03_0_VM7_RANGE                        13:12
#define GPIO_N_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM8_SHIFT)
#define GPIO_N_VM_03_0_VM8_RANGE                        15:14
#define GPIO_N_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_03_0
#define GPIO_N_SCR_03_0                 _MK_ADDR_CONST(0x1c)
#define GPIO_N_SCR_03_0_SECURE                  0x0
#define GPIO_N_SCR_03_0_SCR                     0
#define GPIO_N_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR7_SHIFT)
#define GPIO_N_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR6_SHIFT)
#define GPIO_N_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR5_SHIFT)
#define GPIO_N_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR4_SHIFT)
#define GPIO_N_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR3_SHIFT)
#define GPIO_N_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR2_SHIFT)
#define GPIO_N_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR1_SHIFT)
#define GPIO_N_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR0_SHIFT)
#define GPIO_N_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7W_SHIFT)
#define GPIO_N_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6W_SHIFT)
#define GPIO_N_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5W_SHIFT)
#define GPIO_N_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4W_SHIFT)
#define GPIO_N_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3W_SHIFT)
#define GPIO_N_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2W_SHIFT)
#define GPIO_N_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1W_SHIFT)
#define GPIO_N_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0W_SHIFT)
#define GPIO_N_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7R_SHIFT)
#define GPIO_N_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6R_SHIFT)
#define GPIO_N_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5R_SHIFT)
#define GPIO_N_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4R_SHIFT)
#define GPIO_N_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3R_SHIFT)
#define GPIO_N_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2R_SHIFT)
#define GPIO_N_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1R_SHIFT)
#define GPIO_N_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0R_SHIFT)
#define GPIO_N_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_04_0
#define GPIO_N_VM_04_0                  _MK_ADDR_CONST(0x20)
#define GPIO_N_VM_04_0_SECURE                   0x0
#define GPIO_N_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_04_0_WORD_COUNT                       0x1
#define GPIO_N_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM1_SHIFT)
#define GPIO_N_VM_04_0_VM1_RANGE                        1:0
#define GPIO_N_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM2_SHIFT)
#define GPIO_N_VM_04_0_VM2_RANGE                        3:2
#define GPIO_N_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM3_SHIFT)
#define GPIO_N_VM_04_0_VM3_RANGE                        5:4
#define GPIO_N_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM4_SHIFT)
#define GPIO_N_VM_04_0_VM4_RANGE                        7:6
#define GPIO_N_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM5_SHIFT)
#define GPIO_N_VM_04_0_VM5_RANGE                        9:8
#define GPIO_N_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM6_SHIFT)
#define GPIO_N_VM_04_0_VM6_RANGE                        11:10
#define GPIO_N_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM7_SHIFT)
#define GPIO_N_VM_04_0_VM7_RANGE                        13:12
#define GPIO_N_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM8_SHIFT)
#define GPIO_N_VM_04_0_VM8_RANGE                        15:14
#define GPIO_N_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_04_0
#define GPIO_N_SCR_04_0                 _MK_ADDR_CONST(0x24)
#define GPIO_N_SCR_04_0_SECURE                  0x0
#define GPIO_N_SCR_04_0_SCR                     0
#define GPIO_N_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR7_SHIFT)
#define GPIO_N_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR6_SHIFT)
#define GPIO_N_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR5_SHIFT)
#define GPIO_N_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR4_SHIFT)
#define GPIO_N_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR3_SHIFT)
#define GPIO_N_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR2_SHIFT)
#define GPIO_N_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR1_SHIFT)
#define GPIO_N_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR0_SHIFT)
#define GPIO_N_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7W_SHIFT)
#define GPIO_N_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6W_SHIFT)
#define GPIO_N_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5W_SHIFT)
#define GPIO_N_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4W_SHIFT)
#define GPIO_N_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3W_SHIFT)
#define GPIO_N_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2W_SHIFT)
#define GPIO_N_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1W_SHIFT)
#define GPIO_N_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0W_SHIFT)
#define GPIO_N_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7R_SHIFT)
#define GPIO_N_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6R_SHIFT)
#define GPIO_N_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5R_SHIFT)
#define GPIO_N_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4R_SHIFT)
#define GPIO_N_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3R_SHIFT)
#define GPIO_N_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2R_SHIFT)
#define GPIO_N_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1R_SHIFT)
#define GPIO_N_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0R_SHIFT)
#define GPIO_N_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_05_0
#define GPIO_N_VM_05_0                  _MK_ADDR_CONST(0x28)
#define GPIO_N_VM_05_0_SECURE                   0x0
#define GPIO_N_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_05_0_WORD_COUNT                       0x1
#define GPIO_N_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM1_SHIFT)
#define GPIO_N_VM_05_0_VM1_RANGE                        1:0
#define GPIO_N_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM2_SHIFT)
#define GPIO_N_VM_05_0_VM2_RANGE                        3:2
#define GPIO_N_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM3_SHIFT)
#define GPIO_N_VM_05_0_VM3_RANGE                        5:4
#define GPIO_N_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM4_SHIFT)
#define GPIO_N_VM_05_0_VM4_RANGE                        7:6
#define GPIO_N_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM5_SHIFT)
#define GPIO_N_VM_05_0_VM5_RANGE                        9:8
#define GPIO_N_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM6_SHIFT)
#define GPIO_N_VM_05_0_VM6_RANGE                        11:10
#define GPIO_N_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM7_SHIFT)
#define GPIO_N_VM_05_0_VM7_RANGE                        13:12
#define GPIO_N_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM8_SHIFT)
#define GPIO_N_VM_05_0_VM8_RANGE                        15:14
#define GPIO_N_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_05_0
#define GPIO_N_SCR_05_0                 _MK_ADDR_CONST(0x2c)
#define GPIO_N_SCR_05_0_SECURE                  0x0
#define GPIO_N_SCR_05_0_SCR                     0
#define GPIO_N_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR7_SHIFT)
#define GPIO_N_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR6_SHIFT)
#define GPIO_N_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR5_SHIFT)
#define GPIO_N_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR4_SHIFT)
#define GPIO_N_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR3_SHIFT)
#define GPIO_N_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR2_SHIFT)
#define GPIO_N_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR1_SHIFT)
#define GPIO_N_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR0_SHIFT)
#define GPIO_N_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7W_SHIFT)
#define GPIO_N_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6W_SHIFT)
#define GPIO_N_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5W_SHIFT)
#define GPIO_N_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4W_SHIFT)
#define GPIO_N_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3W_SHIFT)
#define GPIO_N_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2W_SHIFT)
#define GPIO_N_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1W_SHIFT)
#define GPIO_N_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0W_SHIFT)
#define GPIO_N_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7R_SHIFT)
#define GPIO_N_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6R_SHIFT)
#define GPIO_N_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5R_SHIFT)
#define GPIO_N_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4R_SHIFT)
#define GPIO_N_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3R_SHIFT)
#define GPIO_N_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2R_SHIFT)
#define GPIO_N_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1R_SHIFT)
#define GPIO_N_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0R_SHIFT)
#define GPIO_N_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_N_VM_06_0
#define GPIO_N_VM_06_0                  _MK_ADDR_CONST(0x30)
#define GPIO_N_VM_06_0_SECURE                   0x0
#define GPIO_N_VM_06_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_N_VM_06_0_WORD_COUNT                       0x1
#define GPIO_N_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM1_SHIFT)
#define GPIO_N_VM_06_0_VM1_RANGE                        1:0
#define GPIO_N_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM2_SHIFT)
#define GPIO_N_VM_06_0_VM2_RANGE                        3:2
#define GPIO_N_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM3_SHIFT)
#define GPIO_N_VM_06_0_VM3_RANGE                        5:4
#define GPIO_N_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM4_SHIFT)
#define GPIO_N_VM_06_0_VM4_RANGE                        7:6
#define GPIO_N_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM5_SHIFT)
#define GPIO_N_VM_06_0_VM5_RANGE                        9:8
#define GPIO_N_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM6_SHIFT)
#define GPIO_N_VM_06_0_VM6_RANGE                        11:10
#define GPIO_N_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM7_SHIFT)
#define GPIO_N_VM_06_0_VM7_RANGE                        13:12
#define GPIO_N_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_N_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM8_SHIFT)
#define GPIO_N_VM_06_0_VM8_RANGE                        15:14
#define GPIO_N_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_SCR_06_0
#define GPIO_N_SCR_06_0                 _MK_ADDR_CONST(0x34)
#define GPIO_N_SCR_06_0_SECURE                  0x0
#define GPIO_N_SCR_06_0_SCR                     0
#define GPIO_N_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR7_SHIFT)
#define GPIO_N_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR6_SHIFT)
#define GPIO_N_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR5_SHIFT)
#define GPIO_N_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR4_SHIFT)
#define GPIO_N_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR3_SHIFT)
#define GPIO_N_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR2_SHIFT)
#define GPIO_N_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR1_SHIFT)
#define GPIO_N_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR0_SHIFT)
#define GPIO_N_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7W_SHIFT)
#define GPIO_N_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6W_SHIFT)
#define GPIO_N_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5W_SHIFT)
#define GPIO_N_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4W_SHIFT)
#define GPIO_N_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3W_SHIFT)
#define GPIO_N_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2W_SHIFT)
#define GPIO_N_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1W_SHIFT)
#define GPIO_N_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0W_SHIFT)
#define GPIO_N_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7R_SHIFT)
#define GPIO_N_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6R_SHIFT)
#define GPIO_N_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5R_SHIFT)
#define GPIO_N_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4R_SHIFT)
#define GPIO_N_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3R_SHIFT)
#define GPIO_N_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2R_SHIFT)
#define GPIO_N_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1R_SHIFT)
#define GPIO_N_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_N_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0R_SHIFT)
#define GPIO_N_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 56 [0x38]

// Reserved address 60 [0x3c]

// Register GPIO_O_VM_00_0
#define GPIO_O_VM_00_0                  _MK_ADDR_CONST(0x40)
#define GPIO_O_VM_00_0_SECURE                   0x0
#define GPIO_O_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_O_VM_00_0_WORD_COUNT                       0x1
#define GPIO_O_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM1_SHIFT)
#define GPIO_O_VM_00_0_VM1_RANGE                        1:0
#define GPIO_O_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM2_SHIFT)
#define GPIO_O_VM_00_0_VM2_RANGE                        3:2
#define GPIO_O_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM3_SHIFT)
#define GPIO_O_VM_00_0_VM3_RANGE                        5:4
#define GPIO_O_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM4_SHIFT)
#define GPIO_O_VM_00_0_VM4_RANGE                        7:6
#define GPIO_O_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM5_SHIFT)
#define GPIO_O_VM_00_0_VM5_RANGE                        9:8
#define GPIO_O_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM6_SHIFT)
#define GPIO_O_VM_00_0_VM6_RANGE                        11:10
#define GPIO_O_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM7_SHIFT)
#define GPIO_O_VM_00_0_VM7_RANGE                        13:12
#define GPIO_O_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM8_SHIFT)
#define GPIO_O_VM_00_0_VM8_RANGE                        15:14
#define GPIO_O_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_SCR_00_0
#define GPIO_O_SCR_00_0                 _MK_ADDR_CONST(0x44)
#define GPIO_O_SCR_00_0_SECURE                  0x0
#define GPIO_O_SCR_00_0_SCR                     0
#define GPIO_O_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR7_SHIFT)
#define GPIO_O_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR6_SHIFT)
#define GPIO_O_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR5_SHIFT)
#define GPIO_O_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR4_SHIFT)
#define GPIO_O_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR3_SHIFT)
#define GPIO_O_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR2_SHIFT)
#define GPIO_O_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR1_SHIFT)
#define GPIO_O_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR0_SHIFT)
#define GPIO_O_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G7W_SHIFT)
#define GPIO_O_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G6W_SHIFT)
#define GPIO_O_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G5W_SHIFT)
#define GPIO_O_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G4W_SHIFT)
#define GPIO_O_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G3W_SHIFT)
#define GPIO_O_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G2W_SHIFT)
#define GPIO_O_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G1W_SHIFT)
#define GPIO_O_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G0W_SHIFT)
#define GPIO_O_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G7R_SHIFT)
#define GPIO_O_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G6R_SHIFT)
#define GPIO_O_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G5R_SHIFT)
#define GPIO_O_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G4R_SHIFT)
#define GPIO_O_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G3R_SHIFT)
#define GPIO_O_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G2R_SHIFT)
#define GPIO_O_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G1R_SHIFT)
#define GPIO_O_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G0R_SHIFT)
#define GPIO_O_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_O_VM_01_0
#define GPIO_O_VM_01_0                  _MK_ADDR_CONST(0x48)
#define GPIO_O_VM_01_0_SECURE                   0x0
#define GPIO_O_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_O_VM_01_0_WORD_COUNT                       0x1
#define GPIO_O_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM1_SHIFT)
#define GPIO_O_VM_01_0_VM1_RANGE                        1:0
#define GPIO_O_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM2_SHIFT)
#define GPIO_O_VM_01_0_VM2_RANGE                        3:2
#define GPIO_O_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM3_SHIFT)
#define GPIO_O_VM_01_0_VM3_RANGE                        5:4
#define GPIO_O_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM4_SHIFT)
#define GPIO_O_VM_01_0_VM4_RANGE                        7:6
#define GPIO_O_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM5_SHIFT)
#define GPIO_O_VM_01_0_VM5_RANGE                        9:8
#define GPIO_O_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM6_SHIFT)
#define GPIO_O_VM_01_0_VM6_RANGE                        11:10
#define GPIO_O_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM7_SHIFT)
#define GPIO_O_VM_01_0_VM7_RANGE                        13:12
#define GPIO_O_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM8_SHIFT)
#define GPIO_O_VM_01_0_VM8_RANGE                        15:14
#define GPIO_O_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_SCR_01_0
#define GPIO_O_SCR_01_0                 _MK_ADDR_CONST(0x4c)
#define GPIO_O_SCR_01_0_SECURE                  0x0
#define GPIO_O_SCR_01_0_SCR                     0
#define GPIO_O_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR7_SHIFT)
#define GPIO_O_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR6_SHIFT)
#define GPIO_O_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR5_SHIFT)
#define GPIO_O_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR4_SHIFT)
#define GPIO_O_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR3_SHIFT)
#define GPIO_O_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR2_SHIFT)
#define GPIO_O_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR1_SHIFT)
#define GPIO_O_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR0_SHIFT)
#define GPIO_O_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G7W_SHIFT)
#define GPIO_O_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G6W_SHIFT)
#define GPIO_O_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G5W_SHIFT)
#define GPIO_O_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G4W_SHIFT)
#define GPIO_O_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G3W_SHIFT)
#define GPIO_O_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G2W_SHIFT)
#define GPIO_O_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G1W_SHIFT)
#define GPIO_O_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G0W_SHIFT)
#define GPIO_O_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G7R_SHIFT)
#define GPIO_O_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G6R_SHIFT)
#define GPIO_O_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G5R_SHIFT)
#define GPIO_O_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G4R_SHIFT)
#define GPIO_O_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G3R_SHIFT)
#define GPIO_O_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G2R_SHIFT)
#define GPIO_O_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G1R_SHIFT)
#define GPIO_O_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G0R_SHIFT)
#define GPIO_O_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_O_VM_02_0
#define GPIO_O_VM_02_0                  _MK_ADDR_CONST(0x50)
#define GPIO_O_VM_02_0_SECURE                   0x0
#define GPIO_O_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_O_VM_02_0_WORD_COUNT                       0x1
#define GPIO_O_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM1_SHIFT)
#define GPIO_O_VM_02_0_VM1_RANGE                        1:0
#define GPIO_O_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM2_SHIFT)
#define GPIO_O_VM_02_0_VM2_RANGE                        3:2
#define GPIO_O_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM3_SHIFT)
#define GPIO_O_VM_02_0_VM3_RANGE                        5:4
#define GPIO_O_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM4_SHIFT)
#define GPIO_O_VM_02_0_VM4_RANGE                        7:6
#define GPIO_O_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM5_SHIFT)
#define GPIO_O_VM_02_0_VM5_RANGE                        9:8
#define GPIO_O_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM6_SHIFT)
#define GPIO_O_VM_02_0_VM6_RANGE                        11:10
#define GPIO_O_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM7_SHIFT)
#define GPIO_O_VM_02_0_VM7_RANGE                        13:12
#define GPIO_O_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM8_SHIFT)
#define GPIO_O_VM_02_0_VM8_RANGE                        15:14
#define GPIO_O_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_SCR_02_0
#define GPIO_O_SCR_02_0                 _MK_ADDR_CONST(0x54)
#define GPIO_O_SCR_02_0_SECURE                  0x0
#define GPIO_O_SCR_02_0_SCR                     0
#define GPIO_O_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR7_SHIFT)
#define GPIO_O_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR6_SHIFT)
#define GPIO_O_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR5_SHIFT)
#define GPIO_O_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR4_SHIFT)
#define GPIO_O_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR3_SHIFT)
#define GPIO_O_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR2_SHIFT)
#define GPIO_O_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR1_SHIFT)
#define GPIO_O_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR0_SHIFT)
#define GPIO_O_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G7W_SHIFT)
#define GPIO_O_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G6W_SHIFT)
#define GPIO_O_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G5W_SHIFT)
#define GPIO_O_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G4W_SHIFT)
#define GPIO_O_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G3W_SHIFT)
#define GPIO_O_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G2W_SHIFT)
#define GPIO_O_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G1W_SHIFT)
#define GPIO_O_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G0W_SHIFT)
#define GPIO_O_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G7R_SHIFT)
#define GPIO_O_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G6R_SHIFT)
#define GPIO_O_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G5R_SHIFT)
#define GPIO_O_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G4R_SHIFT)
#define GPIO_O_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G3R_SHIFT)
#define GPIO_O_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G2R_SHIFT)
#define GPIO_O_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G1R_SHIFT)
#define GPIO_O_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G0R_SHIFT)
#define GPIO_O_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_O_VM_03_0
#define GPIO_O_VM_03_0                  _MK_ADDR_CONST(0x58)
#define GPIO_O_VM_03_0_SECURE                   0x0
#define GPIO_O_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_O_VM_03_0_WORD_COUNT                       0x1
#define GPIO_O_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM1_SHIFT)
#define GPIO_O_VM_03_0_VM1_RANGE                        1:0
#define GPIO_O_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM2_SHIFT)
#define GPIO_O_VM_03_0_VM2_RANGE                        3:2
#define GPIO_O_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM3_SHIFT)
#define GPIO_O_VM_03_0_VM3_RANGE                        5:4
#define GPIO_O_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM4_SHIFT)
#define GPIO_O_VM_03_0_VM4_RANGE                        7:6
#define GPIO_O_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM5_SHIFT)
#define GPIO_O_VM_03_0_VM5_RANGE                        9:8
#define GPIO_O_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM6_SHIFT)
#define GPIO_O_VM_03_0_VM6_RANGE                        11:10
#define GPIO_O_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM7_SHIFT)
#define GPIO_O_VM_03_0_VM7_RANGE                        13:12
#define GPIO_O_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_O_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM8_SHIFT)
#define GPIO_O_VM_03_0_VM8_RANGE                        15:14
#define GPIO_O_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_SCR_03_0
#define GPIO_O_SCR_03_0                 _MK_ADDR_CONST(0x5c)
#define GPIO_O_SCR_03_0_SECURE                  0x0
#define GPIO_O_SCR_03_0_SCR                     0
#define GPIO_O_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR7_SHIFT)
#define GPIO_O_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR6_SHIFT)
#define GPIO_O_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR5_SHIFT)
#define GPIO_O_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR4_SHIFT)
#define GPIO_O_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR3_SHIFT)
#define GPIO_O_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR2_SHIFT)
#define GPIO_O_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR1_SHIFT)
#define GPIO_O_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR0_SHIFT)
#define GPIO_O_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G7W_SHIFT)
#define GPIO_O_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G6W_SHIFT)
#define GPIO_O_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G5W_SHIFT)
#define GPIO_O_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G4W_SHIFT)
#define GPIO_O_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G3W_SHIFT)
#define GPIO_O_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G2W_SHIFT)
#define GPIO_O_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G1W_SHIFT)
#define GPIO_O_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G0W_SHIFT)
#define GPIO_O_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G7R_SHIFT)
#define GPIO_O_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G6R_SHIFT)
#define GPIO_O_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G5R_SHIFT)
#define GPIO_O_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G4R_SHIFT)
#define GPIO_O_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G3R_SHIFT)
#define GPIO_O_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G2R_SHIFT)
#define GPIO_O_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G1R_SHIFT)
#define GPIO_O_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_O_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G0R_SHIFT)
#define GPIO_O_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 96 [0x60]

// Reserved address 100 [0x64]

// Reserved address 104 [0x68]

// Reserved address 108 [0x6c]

// Reserved address 112 [0x70]

// Reserved address 116 [0x74]

// Reserved address 120 [0x78]

// Reserved address 124 [0x7c]

// Register GPIO_Q_VM_00_0
#define GPIO_Q_VM_00_0                  _MK_ADDR_CONST(0x80)
#define GPIO_Q_VM_00_0_SECURE                   0x0
#define GPIO_Q_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM1_SHIFT)
#define GPIO_Q_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM2_SHIFT)
#define GPIO_Q_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM3_SHIFT)
#define GPIO_Q_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM4_SHIFT)
#define GPIO_Q_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM5_SHIFT)
#define GPIO_Q_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM6_SHIFT)
#define GPIO_Q_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM7_SHIFT)
#define GPIO_Q_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM8_SHIFT)
#define GPIO_Q_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_00_0
#define GPIO_Q_SCR_00_0                 _MK_ADDR_CONST(0x84)
#define GPIO_Q_SCR_00_0_SECURE                  0x0
#define GPIO_Q_SCR_00_0_SCR                     0
#define GPIO_Q_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR7_SHIFT)
#define GPIO_Q_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR6_SHIFT)
#define GPIO_Q_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR5_SHIFT)
#define GPIO_Q_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR4_SHIFT)
#define GPIO_Q_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR3_SHIFT)
#define GPIO_Q_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR2_SHIFT)
#define GPIO_Q_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR1_SHIFT)
#define GPIO_Q_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR0_SHIFT)
#define GPIO_Q_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7W_SHIFT)
#define GPIO_Q_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6W_SHIFT)
#define GPIO_Q_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5W_SHIFT)
#define GPIO_Q_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4W_SHIFT)
#define GPIO_Q_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3W_SHIFT)
#define GPIO_Q_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2W_SHIFT)
#define GPIO_Q_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1W_SHIFT)
#define GPIO_Q_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0W_SHIFT)
#define GPIO_Q_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7R_SHIFT)
#define GPIO_Q_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6R_SHIFT)
#define GPIO_Q_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5R_SHIFT)
#define GPIO_Q_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4R_SHIFT)
#define GPIO_Q_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3R_SHIFT)
#define GPIO_Q_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2R_SHIFT)
#define GPIO_Q_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1R_SHIFT)
#define GPIO_Q_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0R_SHIFT)
#define GPIO_Q_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Q_VM_01_0
#define GPIO_Q_VM_01_0                  _MK_ADDR_CONST(0x88)
#define GPIO_Q_VM_01_0_SECURE                   0x0
#define GPIO_Q_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM1_SHIFT)
#define GPIO_Q_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM2_SHIFT)
#define GPIO_Q_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM3_SHIFT)
#define GPIO_Q_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM4_SHIFT)
#define GPIO_Q_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM5_SHIFT)
#define GPIO_Q_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM6_SHIFT)
#define GPIO_Q_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM7_SHIFT)
#define GPIO_Q_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM8_SHIFT)
#define GPIO_Q_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_01_0
#define GPIO_Q_SCR_01_0                 _MK_ADDR_CONST(0x8c)
#define GPIO_Q_SCR_01_0_SECURE                  0x0
#define GPIO_Q_SCR_01_0_SCR                     0
#define GPIO_Q_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR7_SHIFT)
#define GPIO_Q_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR6_SHIFT)
#define GPIO_Q_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR5_SHIFT)
#define GPIO_Q_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR4_SHIFT)
#define GPIO_Q_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR3_SHIFT)
#define GPIO_Q_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR2_SHIFT)
#define GPIO_Q_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR1_SHIFT)
#define GPIO_Q_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR0_SHIFT)
#define GPIO_Q_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7W_SHIFT)
#define GPIO_Q_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6W_SHIFT)
#define GPIO_Q_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5W_SHIFT)
#define GPIO_Q_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4W_SHIFT)
#define GPIO_Q_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3W_SHIFT)
#define GPIO_Q_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2W_SHIFT)
#define GPIO_Q_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1W_SHIFT)
#define GPIO_Q_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0W_SHIFT)
#define GPIO_Q_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7R_SHIFT)
#define GPIO_Q_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6R_SHIFT)
#define GPIO_Q_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5R_SHIFT)
#define GPIO_Q_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4R_SHIFT)
#define GPIO_Q_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3R_SHIFT)
#define GPIO_Q_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2R_SHIFT)
#define GPIO_Q_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1R_SHIFT)
#define GPIO_Q_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0R_SHIFT)
#define GPIO_Q_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Q_VM_02_0
#define GPIO_Q_VM_02_0                  _MK_ADDR_CONST(0x90)
#define GPIO_Q_VM_02_0_SECURE                   0x0
#define GPIO_Q_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM1_SHIFT)
#define GPIO_Q_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM2_SHIFT)
#define GPIO_Q_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM3_SHIFT)
#define GPIO_Q_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM4_SHIFT)
#define GPIO_Q_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM5_SHIFT)
#define GPIO_Q_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM6_SHIFT)
#define GPIO_Q_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM7_SHIFT)
#define GPIO_Q_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM8_SHIFT)
#define GPIO_Q_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_02_0
#define GPIO_Q_SCR_02_0                 _MK_ADDR_CONST(0x94)
#define GPIO_Q_SCR_02_0_SECURE                  0x0
#define GPIO_Q_SCR_02_0_SCR                     0
#define GPIO_Q_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR7_SHIFT)
#define GPIO_Q_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR6_SHIFT)
#define GPIO_Q_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR5_SHIFT)
#define GPIO_Q_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR4_SHIFT)
#define GPIO_Q_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR3_SHIFT)
#define GPIO_Q_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR2_SHIFT)
#define GPIO_Q_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR1_SHIFT)
#define GPIO_Q_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR0_SHIFT)
#define GPIO_Q_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7W_SHIFT)
#define GPIO_Q_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6W_SHIFT)
#define GPIO_Q_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5W_SHIFT)
#define GPIO_Q_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4W_SHIFT)
#define GPIO_Q_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3W_SHIFT)
#define GPIO_Q_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2W_SHIFT)
#define GPIO_Q_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1W_SHIFT)
#define GPIO_Q_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0W_SHIFT)
#define GPIO_Q_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7R_SHIFT)
#define GPIO_Q_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6R_SHIFT)
#define GPIO_Q_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5R_SHIFT)
#define GPIO_Q_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4R_SHIFT)
#define GPIO_Q_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3R_SHIFT)
#define GPIO_Q_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2R_SHIFT)
#define GPIO_Q_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1R_SHIFT)
#define GPIO_Q_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0R_SHIFT)
#define GPIO_Q_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Q_VM_03_0
#define GPIO_Q_VM_03_0                  _MK_ADDR_CONST(0x98)
#define GPIO_Q_VM_03_0_SECURE                   0x0
#define GPIO_Q_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM1_SHIFT)
#define GPIO_Q_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM2_SHIFT)
#define GPIO_Q_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM3_SHIFT)
#define GPIO_Q_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM4_SHIFT)
#define GPIO_Q_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM5_SHIFT)
#define GPIO_Q_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM6_SHIFT)
#define GPIO_Q_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM7_SHIFT)
#define GPIO_Q_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM8_SHIFT)
#define GPIO_Q_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_03_0
#define GPIO_Q_SCR_03_0                 _MK_ADDR_CONST(0x9c)
#define GPIO_Q_SCR_03_0_SECURE                  0x0
#define GPIO_Q_SCR_03_0_SCR                     0
#define GPIO_Q_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR7_SHIFT)
#define GPIO_Q_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR6_SHIFT)
#define GPIO_Q_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR5_SHIFT)
#define GPIO_Q_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR4_SHIFT)
#define GPIO_Q_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR3_SHIFT)
#define GPIO_Q_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR2_SHIFT)
#define GPIO_Q_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR1_SHIFT)
#define GPIO_Q_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR0_SHIFT)
#define GPIO_Q_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7W_SHIFT)
#define GPIO_Q_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6W_SHIFT)
#define GPIO_Q_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5W_SHIFT)
#define GPIO_Q_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4W_SHIFT)
#define GPIO_Q_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3W_SHIFT)
#define GPIO_Q_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2W_SHIFT)
#define GPIO_Q_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1W_SHIFT)
#define GPIO_Q_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0W_SHIFT)
#define GPIO_Q_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7R_SHIFT)
#define GPIO_Q_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6R_SHIFT)
#define GPIO_Q_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5R_SHIFT)
#define GPIO_Q_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4R_SHIFT)
#define GPIO_Q_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3R_SHIFT)
#define GPIO_Q_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2R_SHIFT)
#define GPIO_Q_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1R_SHIFT)
#define GPIO_Q_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0R_SHIFT)
#define GPIO_Q_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Q_VM_04_0
#define GPIO_Q_VM_04_0                  _MK_ADDR_CONST(0xa0)
#define GPIO_Q_VM_04_0_SECURE                   0x0
#define GPIO_Q_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM1_SHIFT)
#define GPIO_Q_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM2_SHIFT)
#define GPIO_Q_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM3_SHIFT)
#define GPIO_Q_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM4_SHIFT)
#define GPIO_Q_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM5_SHIFT)
#define GPIO_Q_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM6_SHIFT)
#define GPIO_Q_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM7_SHIFT)
#define GPIO_Q_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM8_SHIFT)
#define GPIO_Q_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_04_0
#define GPIO_Q_SCR_04_0                 _MK_ADDR_CONST(0xa4)
#define GPIO_Q_SCR_04_0_SECURE                  0x0
#define GPIO_Q_SCR_04_0_SCR                     0
#define GPIO_Q_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR7_SHIFT)
#define GPIO_Q_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR6_SHIFT)
#define GPIO_Q_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR5_SHIFT)
#define GPIO_Q_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR4_SHIFT)
#define GPIO_Q_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR3_SHIFT)
#define GPIO_Q_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR2_SHIFT)
#define GPIO_Q_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR1_SHIFT)
#define GPIO_Q_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR0_SHIFT)
#define GPIO_Q_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7W_SHIFT)
#define GPIO_Q_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6W_SHIFT)
#define GPIO_Q_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5W_SHIFT)
#define GPIO_Q_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4W_SHIFT)
#define GPIO_Q_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3W_SHIFT)
#define GPIO_Q_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2W_SHIFT)
#define GPIO_Q_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1W_SHIFT)
#define GPIO_Q_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0W_SHIFT)
#define GPIO_Q_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7R_SHIFT)
#define GPIO_Q_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6R_SHIFT)
#define GPIO_Q_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5R_SHIFT)
#define GPIO_Q_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4R_SHIFT)
#define GPIO_Q_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3R_SHIFT)
#define GPIO_Q_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2R_SHIFT)
#define GPIO_Q_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1R_SHIFT)
#define GPIO_Q_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0R_SHIFT)
#define GPIO_Q_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Q_VM_05_0
#define GPIO_Q_VM_05_0                  _MK_ADDR_CONST(0xa8)
#define GPIO_Q_VM_05_0_SECURE                   0x0
#define GPIO_Q_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_Q_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM1_SHIFT)
#define GPIO_Q_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM2_SHIFT)
#define GPIO_Q_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM3_SHIFT)
#define GPIO_Q_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM4_SHIFT)
#define GPIO_Q_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM5_SHIFT)
#define GPIO_Q_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM6_SHIFT)
#define GPIO_Q_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM7_SHIFT)
#define GPIO_Q_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Q_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM8_SHIFT)
#define GPIO_Q_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_SCR_05_0
#define GPIO_Q_SCR_05_0                 _MK_ADDR_CONST(0xac)
#define GPIO_Q_SCR_05_0_SECURE                  0x0
#define GPIO_Q_SCR_05_0_SCR                     0
#define GPIO_Q_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR7_SHIFT)
#define GPIO_Q_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR6_SHIFT)
#define GPIO_Q_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR5_SHIFT)
#define GPIO_Q_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR4_SHIFT)
#define GPIO_Q_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR3_SHIFT)
#define GPIO_Q_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR2_SHIFT)
#define GPIO_Q_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR1_SHIFT)
#define GPIO_Q_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR0_SHIFT)
#define GPIO_Q_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7W_SHIFT)
#define GPIO_Q_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6W_SHIFT)
#define GPIO_Q_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5W_SHIFT)
#define GPIO_Q_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4W_SHIFT)
#define GPIO_Q_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3W_SHIFT)
#define GPIO_Q_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2W_SHIFT)
#define GPIO_Q_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1W_SHIFT)
#define GPIO_Q_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0W_SHIFT)
#define GPIO_Q_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7R_SHIFT)
#define GPIO_Q_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6R_SHIFT)
#define GPIO_Q_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5R_SHIFT)
#define GPIO_Q_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4R_SHIFT)
#define GPIO_Q_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3R_SHIFT)
#define GPIO_Q_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2R_SHIFT)
#define GPIO_Q_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1R_SHIFT)
#define GPIO_Q_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Q_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0R_SHIFT)
#define GPIO_Q_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 176 [0xb0]

// Reserved address 180 [0xb4]

// Reserved address 184 [0xb8]

// Reserved address 188 [0xbc]

// Register GPIO_T_VM_00_0
#define GPIO_T_VM_00_0                  _MK_ADDR_CONST(0xc0)
#define GPIO_T_VM_00_0_SECURE                   0x0
#define GPIO_T_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_T_VM_00_0_WORD_COUNT                       0x1
#define GPIO_T_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM1_SHIFT)
#define GPIO_T_VM_00_0_VM1_RANGE                        1:0
#define GPIO_T_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM2_SHIFT)
#define GPIO_T_VM_00_0_VM2_RANGE                        3:2
#define GPIO_T_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM3_SHIFT)
#define GPIO_T_VM_00_0_VM3_RANGE                        5:4
#define GPIO_T_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM4_SHIFT)
#define GPIO_T_VM_00_0_VM4_RANGE                        7:6
#define GPIO_T_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM5_SHIFT)
#define GPIO_T_VM_00_0_VM5_RANGE                        9:8
#define GPIO_T_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM6_SHIFT)
#define GPIO_T_VM_00_0_VM6_RANGE                        11:10
#define GPIO_T_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM7_SHIFT)
#define GPIO_T_VM_00_0_VM7_RANGE                        13:12
#define GPIO_T_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM8_SHIFT)
#define GPIO_T_VM_00_0_VM8_RANGE                        15:14
#define GPIO_T_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_SCR_00_0
#define GPIO_T_SCR_00_0                 _MK_ADDR_CONST(0xc4)
#define GPIO_T_SCR_00_0_SECURE                  0x0
#define GPIO_T_SCR_00_0_SCR                     0
#define GPIO_T_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR7_SHIFT)
#define GPIO_T_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR6_SHIFT)
#define GPIO_T_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR5_SHIFT)
#define GPIO_T_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR4_SHIFT)
#define GPIO_T_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR3_SHIFT)
#define GPIO_T_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR2_SHIFT)
#define GPIO_T_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR1_SHIFT)
#define GPIO_T_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR0_SHIFT)
#define GPIO_T_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G7W_SHIFT)
#define GPIO_T_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G6W_SHIFT)
#define GPIO_T_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G5W_SHIFT)
#define GPIO_T_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G4W_SHIFT)
#define GPIO_T_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G3W_SHIFT)
#define GPIO_T_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G2W_SHIFT)
#define GPIO_T_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G1W_SHIFT)
#define GPIO_T_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G0W_SHIFT)
#define GPIO_T_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G7R_SHIFT)
#define GPIO_T_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G6R_SHIFT)
#define GPIO_T_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G5R_SHIFT)
#define GPIO_T_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G4R_SHIFT)
#define GPIO_T_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G3R_SHIFT)
#define GPIO_T_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G2R_SHIFT)
#define GPIO_T_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G1R_SHIFT)
#define GPIO_T_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G0R_SHIFT)
#define GPIO_T_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_T_VM_01_0
#define GPIO_T_VM_01_0                  _MK_ADDR_CONST(0xc8)
#define GPIO_T_VM_01_0_SECURE                   0x0
#define GPIO_T_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_T_VM_01_0_WORD_COUNT                       0x1
#define GPIO_T_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM1_SHIFT)
#define GPIO_T_VM_01_0_VM1_RANGE                        1:0
#define GPIO_T_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM2_SHIFT)
#define GPIO_T_VM_01_0_VM2_RANGE                        3:2
#define GPIO_T_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM3_SHIFT)
#define GPIO_T_VM_01_0_VM3_RANGE                        5:4
#define GPIO_T_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM4_SHIFT)
#define GPIO_T_VM_01_0_VM4_RANGE                        7:6
#define GPIO_T_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM5_SHIFT)
#define GPIO_T_VM_01_0_VM5_RANGE                        9:8
#define GPIO_T_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM6_SHIFT)
#define GPIO_T_VM_01_0_VM6_RANGE                        11:10
#define GPIO_T_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM7_SHIFT)
#define GPIO_T_VM_01_0_VM7_RANGE                        13:12
#define GPIO_T_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM8_SHIFT)
#define GPIO_T_VM_01_0_VM8_RANGE                        15:14
#define GPIO_T_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_SCR_01_0
#define GPIO_T_SCR_01_0                 _MK_ADDR_CONST(0xcc)
#define GPIO_T_SCR_01_0_SECURE                  0x0
#define GPIO_T_SCR_01_0_SCR                     0
#define GPIO_T_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR7_SHIFT)
#define GPIO_T_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR6_SHIFT)
#define GPIO_T_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR5_SHIFT)
#define GPIO_T_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR4_SHIFT)
#define GPIO_T_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR3_SHIFT)
#define GPIO_T_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR2_SHIFT)
#define GPIO_T_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR1_SHIFT)
#define GPIO_T_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR0_SHIFT)
#define GPIO_T_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G7W_SHIFT)
#define GPIO_T_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G6W_SHIFT)
#define GPIO_T_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G5W_SHIFT)
#define GPIO_T_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G4W_SHIFT)
#define GPIO_T_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G3W_SHIFT)
#define GPIO_T_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G2W_SHIFT)
#define GPIO_T_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G1W_SHIFT)
#define GPIO_T_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G0W_SHIFT)
#define GPIO_T_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G7R_SHIFT)
#define GPIO_T_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G6R_SHIFT)
#define GPIO_T_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G5R_SHIFT)
#define GPIO_T_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G4R_SHIFT)
#define GPIO_T_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G3R_SHIFT)
#define GPIO_T_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G2R_SHIFT)
#define GPIO_T_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G1R_SHIFT)
#define GPIO_T_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G0R_SHIFT)
#define GPIO_T_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_T_VM_02_0
#define GPIO_T_VM_02_0                  _MK_ADDR_CONST(0xd0)
#define GPIO_T_VM_02_0_SECURE                   0x0
#define GPIO_T_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_T_VM_02_0_WORD_COUNT                       0x1
#define GPIO_T_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM1_SHIFT)
#define GPIO_T_VM_02_0_VM1_RANGE                        1:0
#define GPIO_T_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM2_SHIFT)
#define GPIO_T_VM_02_0_VM2_RANGE                        3:2
#define GPIO_T_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM3_SHIFT)
#define GPIO_T_VM_02_0_VM3_RANGE                        5:4
#define GPIO_T_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM4_SHIFT)
#define GPIO_T_VM_02_0_VM4_RANGE                        7:6
#define GPIO_T_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM5_SHIFT)
#define GPIO_T_VM_02_0_VM5_RANGE                        9:8
#define GPIO_T_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM6_SHIFT)
#define GPIO_T_VM_02_0_VM6_RANGE                        11:10
#define GPIO_T_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM7_SHIFT)
#define GPIO_T_VM_02_0_VM7_RANGE                        13:12
#define GPIO_T_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM8_SHIFT)
#define GPIO_T_VM_02_0_VM8_RANGE                        15:14
#define GPIO_T_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_SCR_02_0
#define GPIO_T_SCR_02_0                 _MK_ADDR_CONST(0xd4)
#define GPIO_T_SCR_02_0_SECURE                  0x0
#define GPIO_T_SCR_02_0_SCR                     0
#define GPIO_T_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR7_SHIFT)
#define GPIO_T_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR6_SHIFT)
#define GPIO_T_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR5_SHIFT)
#define GPIO_T_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR4_SHIFT)
#define GPIO_T_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR3_SHIFT)
#define GPIO_T_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR2_SHIFT)
#define GPIO_T_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR1_SHIFT)
#define GPIO_T_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR0_SHIFT)
#define GPIO_T_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G7W_SHIFT)
#define GPIO_T_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G6W_SHIFT)
#define GPIO_T_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G5W_SHIFT)
#define GPIO_T_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G4W_SHIFT)
#define GPIO_T_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G3W_SHIFT)
#define GPIO_T_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G2W_SHIFT)
#define GPIO_T_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G1W_SHIFT)
#define GPIO_T_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G0W_SHIFT)
#define GPIO_T_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G7R_SHIFT)
#define GPIO_T_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G6R_SHIFT)
#define GPIO_T_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G5R_SHIFT)
#define GPIO_T_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G4R_SHIFT)
#define GPIO_T_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G3R_SHIFT)
#define GPIO_T_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G2R_SHIFT)
#define GPIO_T_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G1R_SHIFT)
#define GPIO_T_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G0R_SHIFT)
#define GPIO_T_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_T_VM_03_0
#define GPIO_T_VM_03_0                  _MK_ADDR_CONST(0xd8)
#define GPIO_T_VM_03_0_SECURE                   0x0
#define GPIO_T_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_T_VM_03_0_WORD_COUNT                       0x1
#define GPIO_T_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM1_SHIFT)
#define GPIO_T_VM_03_0_VM1_RANGE                        1:0
#define GPIO_T_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM2_SHIFT)
#define GPIO_T_VM_03_0_VM2_RANGE                        3:2
#define GPIO_T_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM3_SHIFT)
#define GPIO_T_VM_03_0_VM3_RANGE                        5:4
#define GPIO_T_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM4_SHIFT)
#define GPIO_T_VM_03_0_VM4_RANGE                        7:6
#define GPIO_T_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM5_SHIFT)
#define GPIO_T_VM_03_0_VM5_RANGE                        9:8
#define GPIO_T_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM6_SHIFT)
#define GPIO_T_VM_03_0_VM6_RANGE                        11:10
#define GPIO_T_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM7_SHIFT)
#define GPIO_T_VM_03_0_VM7_RANGE                        13:12
#define GPIO_T_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_T_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM8_SHIFT)
#define GPIO_T_VM_03_0_VM8_RANGE                        15:14
#define GPIO_T_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_SCR_03_0
#define GPIO_T_SCR_03_0                 _MK_ADDR_CONST(0xdc)
#define GPIO_T_SCR_03_0_SECURE                  0x0
#define GPIO_T_SCR_03_0_SCR                     0
#define GPIO_T_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR7_SHIFT)
#define GPIO_T_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR6_SHIFT)
#define GPIO_T_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR5_SHIFT)
#define GPIO_T_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR4_SHIFT)
#define GPIO_T_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR3_SHIFT)
#define GPIO_T_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR2_SHIFT)
#define GPIO_T_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR1_SHIFT)
#define GPIO_T_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR0_SHIFT)
#define GPIO_T_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G7W_SHIFT)
#define GPIO_T_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G6W_SHIFT)
#define GPIO_T_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G5W_SHIFT)
#define GPIO_T_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G4W_SHIFT)
#define GPIO_T_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G3W_SHIFT)
#define GPIO_T_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G2W_SHIFT)
#define GPIO_T_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G1W_SHIFT)
#define GPIO_T_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G0W_SHIFT)
#define GPIO_T_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G7R_SHIFT)
#define GPIO_T_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G6R_SHIFT)
#define GPIO_T_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G5R_SHIFT)
#define GPIO_T_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G4R_SHIFT)
#define GPIO_T_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G3R_SHIFT)
#define GPIO_T_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G2R_SHIFT)
#define GPIO_T_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G1R_SHIFT)
#define GPIO_T_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_T_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G0R_SHIFT)
#define GPIO_T_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 224 [0xe0]

// Reserved address 228 [0xe4]

// Reserved address 232 [0xe8]

// Reserved address 236 [0xec]

// Reserved address 240 [0xf0]

// Reserved address 244 [0xf4]

// Reserved address 248 [0xf8]

// Reserved address 252 [0xfc]

// Register GPIO_I_VM_00_0
#define GPIO_I_VM_00_0                  _MK_ADDR_CONST(0x100)
#define GPIO_I_VM_00_0_SECURE                   0x0
#define GPIO_I_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_00_0_WORD_COUNT                       0x1
#define GPIO_I_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM1_SHIFT)
#define GPIO_I_VM_00_0_VM1_RANGE                        1:0
#define GPIO_I_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM2_SHIFT)
#define GPIO_I_VM_00_0_VM2_RANGE                        3:2
#define GPIO_I_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM3_SHIFT)
#define GPIO_I_VM_00_0_VM3_RANGE                        5:4
#define GPIO_I_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM4_SHIFT)
#define GPIO_I_VM_00_0_VM4_RANGE                        7:6
#define GPIO_I_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM5_SHIFT)
#define GPIO_I_VM_00_0_VM5_RANGE                        9:8
#define GPIO_I_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM6_SHIFT)
#define GPIO_I_VM_00_0_VM6_RANGE                        11:10
#define GPIO_I_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM7_SHIFT)
#define GPIO_I_VM_00_0_VM7_RANGE                        13:12
#define GPIO_I_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM8_SHIFT)
#define GPIO_I_VM_00_0_VM8_RANGE                        15:14
#define GPIO_I_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_00_0
#define GPIO_I_SCR_00_0                 _MK_ADDR_CONST(0x104)
#define GPIO_I_SCR_00_0_SECURE                  0x0
#define GPIO_I_SCR_00_0_SCR                     0
#define GPIO_I_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR7_SHIFT)
#define GPIO_I_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR6_SHIFT)
#define GPIO_I_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR5_SHIFT)
#define GPIO_I_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR4_SHIFT)
#define GPIO_I_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR3_SHIFT)
#define GPIO_I_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR2_SHIFT)
#define GPIO_I_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR1_SHIFT)
#define GPIO_I_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR0_SHIFT)
#define GPIO_I_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7W_SHIFT)
#define GPIO_I_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6W_SHIFT)
#define GPIO_I_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5W_SHIFT)
#define GPIO_I_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4W_SHIFT)
#define GPIO_I_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3W_SHIFT)
#define GPIO_I_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2W_SHIFT)
#define GPIO_I_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1W_SHIFT)
#define GPIO_I_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0W_SHIFT)
#define GPIO_I_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7R_SHIFT)
#define GPIO_I_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6R_SHIFT)
#define GPIO_I_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5R_SHIFT)
#define GPIO_I_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4R_SHIFT)
#define GPIO_I_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3R_SHIFT)
#define GPIO_I_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2R_SHIFT)
#define GPIO_I_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1R_SHIFT)
#define GPIO_I_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0R_SHIFT)
#define GPIO_I_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_01_0
#define GPIO_I_VM_01_0                  _MK_ADDR_CONST(0x108)
#define GPIO_I_VM_01_0_SECURE                   0x0
#define GPIO_I_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_01_0_WORD_COUNT                       0x1
#define GPIO_I_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM1_SHIFT)
#define GPIO_I_VM_01_0_VM1_RANGE                        1:0
#define GPIO_I_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM2_SHIFT)
#define GPIO_I_VM_01_0_VM2_RANGE                        3:2
#define GPIO_I_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM3_SHIFT)
#define GPIO_I_VM_01_0_VM3_RANGE                        5:4
#define GPIO_I_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM4_SHIFT)
#define GPIO_I_VM_01_0_VM4_RANGE                        7:6
#define GPIO_I_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM5_SHIFT)
#define GPIO_I_VM_01_0_VM5_RANGE                        9:8
#define GPIO_I_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM6_SHIFT)
#define GPIO_I_VM_01_0_VM6_RANGE                        11:10
#define GPIO_I_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM7_SHIFT)
#define GPIO_I_VM_01_0_VM7_RANGE                        13:12
#define GPIO_I_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM8_SHIFT)
#define GPIO_I_VM_01_0_VM8_RANGE                        15:14
#define GPIO_I_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_01_0
#define GPIO_I_SCR_01_0                 _MK_ADDR_CONST(0x10c)
#define GPIO_I_SCR_01_0_SECURE                  0x0
#define GPIO_I_SCR_01_0_SCR                     0
#define GPIO_I_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR7_SHIFT)
#define GPIO_I_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR6_SHIFT)
#define GPIO_I_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR5_SHIFT)
#define GPIO_I_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR4_SHIFT)
#define GPIO_I_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR3_SHIFT)
#define GPIO_I_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR2_SHIFT)
#define GPIO_I_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR1_SHIFT)
#define GPIO_I_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR0_SHIFT)
#define GPIO_I_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7W_SHIFT)
#define GPIO_I_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6W_SHIFT)
#define GPIO_I_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5W_SHIFT)
#define GPIO_I_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4W_SHIFT)
#define GPIO_I_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3W_SHIFT)
#define GPIO_I_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2W_SHIFT)
#define GPIO_I_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1W_SHIFT)
#define GPIO_I_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0W_SHIFT)
#define GPIO_I_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7R_SHIFT)
#define GPIO_I_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6R_SHIFT)
#define GPIO_I_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5R_SHIFT)
#define GPIO_I_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4R_SHIFT)
#define GPIO_I_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3R_SHIFT)
#define GPIO_I_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2R_SHIFT)
#define GPIO_I_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1R_SHIFT)
#define GPIO_I_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0R_SHIFT)
#define GPIO_I_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_02_0
#define GPIO_I_VM_02_0                  _MK_ADDR_CONST(0x110)
#define GPIO_I_VM_02_0_SECURE                   0x0
#define GPIO_I_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_02_0_WORD_COUNT                       0x1
#define GPIO_I_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM1_SHIFT)
#define GPIO_I_VM_02_0_VM1_RANGE                        1:0
#define GPIO_I_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM2_SHIFT)
#define GPIO_I_VM_02_0_VM2_RANGE                        3:2
#define GPIO_I_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM3_SHIFT)
#define GPIO_I_VM_02_0_VM3_RANGE                        5:4
#define GPIO_I_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM4_SHIFT)
#define GPIO_I_VM_02_0_VM4_RANGE                        7:6
#define GPIO_I_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM5_SHIFT)
#define GPIO_I_VM_02_0_VM5_RANGE                        9:8
#define GPIO_I_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM6_SHIFT)
#define GPIO_I_VM_02_0_VM6_RANGE                        11:10
#define GPIO_I_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM7_SHIFT)
#define GPIO_I_VM_02_0_VM7_RANGE                        13:12
#define GPIO_I_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM8_SHIFT)
#define GPIO_I_VM_02_0_VM8_RANGE                        15:14
#define GPIO_I_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_02_0
#define GPIO_I_SCR_02_0                 _MK_ADDR_CONST(0x114)
#define GPIO_I_SCR_02_0_SECURE                  0x0
#define GPIO_I_SCR_02_0_SCR                     0
#define GPIO_I_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR7_SHIFT)
#define GPIO_I_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR6_SHIFT)
#define GPIO_I_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR5_SHIFT)
#define GPIO_I_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR4_SHIFT)
#define GPIO_I_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR3_SHIFT)
#define GPIO_I_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR2_SHIFT)
#define GPIO_I_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR1_SHIFT)
#define GPIO_I_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR0_SHIFT)
#define GPIO_I_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7W_SHIFT)
#define GPIO_I_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6W_SHIFT)
#define GPIO_I_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5W_SHIFT)
#define GPIO_I_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4W_SHIFT)
#define GPIO_I_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3W_SHIFT)
#define GPIO_I_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2W_SHIFT)
#define GPIO_I_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1W_SHIFT)
#define GPIO_I_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0W_SHIFT)
#define GPIO_I_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7R_SHIFT)
#define GPIO_I_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6R_SHIFT)
#define GPIO_I_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5R_SHIFT)
#define GPIO_I_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4R_SHIFT)
#define GPIO_I_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3R_SHIFT)
#define GPIO_I_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2R_SHIFT)
#define GPIO_I_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1R_SHIFT)
#define GPIO_I_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0R_SHIFT)
#define GPIO_I_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_03_0
#define GPIO_I_VM_03_0                  _MK_ADDR_CONST(0x118)
#define GPIO_I_VM_03_0_SECURE                   0x0
#define GPIO_I_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_03_0_WORD_COUNT                       0x1
#define GPIO_I_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM1_SHIFT)
#define GPIO_I_VM_03_0_VM1_RANGE                        1:0
#define GPIO_I_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM2_SHIFT)
#define GPIO_I_VM_03_0_VM2_RANGE                        3:2
#define GPIO_I_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM3_SHIFT)
#define GPIO_I_VM_03_0_VM3_RANGE                        5:4
#define GPIO_I_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM4_SHIFT)
#define GPIO_I_VM_03_0_VM4_RANGE                        7:6
#define GPIO_I_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM5_SHIFT)
#define GPIO_I_VM_03_0_VM5_RANGE                        9:8
#define GPIO_I_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM6_SHIFT)
#define GPIO_I_VM_03_0_VM6_RANGE                        11:10
#define GPIO_I_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM7_SHIFT)
#define GPIO_I_VM_03_0_VM7_RANGE                        13:12
#define GPIO_I_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM8_SHIFT)
#define GPIO_I_VM_03_0_VM8_RANGE                        15:14
#define GPIO_I_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_03_0
#define GPIO_I_SCR_03_0                 _MK_ADDR_CONST(0x11c)
#define GPIO_I_SCR_03_0_SECURE                  0x0
#define GPIO_I_SCR_03_0_SCR                     0
#define GPIO_I_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR7_SHIFT)
#define GPIO_I_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR6_SHIFT)
#define GPIO_I_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR5_SHIFT)
#define GPIO_I_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR4_SHIFT)
#define GPIO_I_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR3_SHIFT)
#define GPIO_I_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR2_SHIFT)
#define GPIO_I_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR1_SHIFT)
#define GPIO_I_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR0_SHIFT)
#define GPIO_I_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7W_SHIFT)
#define GPIO_I_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6W_SHIFT)
#define GPIO_I_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5W_SHIFT)
#define GPIO_I_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4W_SHIFT)
#define GPIO_I_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3W_SHIFT)
#define GPIO_I_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2W_SHIFT)
#define GPIO_I_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1W_SHIFT)
#define GPIO_I_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0W_SHIFT)
#define GPIO_I_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7R_SHIFT)
#define GPIO_I_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6R_SHIFT)
#define GPIO_I_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5R_SHIFT)
#define GPIO_I_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4R_SHIFT)
#define GPIO_I_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3R_SHIFT)
#define GPIO_I_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2R_SHIFT)
#define GPIO_I_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1R_SHIFT)
#define GPIO_I_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0R_SHIFT)
#define GPIO_I_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_04_0
#define GPIO_I_VM_04_0                  _MK_ADDR_CONST(0x120)
#define GPIO_I_VM_04_0_SECURE                   0x0
#define GPIO_I_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_04_0_WORD_COUNT                       0x1
#define GPIO_I_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM1_SHIFT)
#define GPIO_I_VM_04_0_VM1_RANGE                        1:0
#define GPIO_I_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM2_SHIFT)
#define GPIO_I_VM_04_0_VM2_RANGE                        3:2
#define GPIO_I_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM3_SHIFT)
#define GPIO_I_VM_04_0_VM3_RANGE                        5:4
#define GPIO_I_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM4_SHIFT)
#define GPIO_I_VM_04_0_VM4_RANGE                        7:6
#define GPIO_I_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM5_SHIFT)
#define GPIO_I_VM_04_0_VM5_RANGE                        9:8
#define GPIO_I_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM6_SHIFT)
#define GPIO_I_VM_04_0_VM6_RANGE                        11:10
#define GPIO_I_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM7_SHIFT)
#define GPIO_I_VM_04_0_VM7_RANGE                        13:12
#define GPIO_I_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM8_SHIFT)
#define GPIO_I_VM_04_0_VM8_RANGE                        15:14
#define GPIO_I_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_04_0
#define GPIO_I_SCR_04_0                 _MK_ADDR_CONST(0x124)
#define GPIO_I_SCR_04_0_SECURE                  0x0
#define GPIO_I_SCR_04_0_SCR                     0
#define GPIO_I_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR7_SHIFT)
#define GPIO_I_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR6_SHIFT)
#define GPIO_I_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR5_SHIFT)
#define GPIO_I_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR4_SHIFT)
#define GPIO_I_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR3_SHIFT)
#define GPIO_I_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR2_SHIFT)
#define GPIO_I_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR1_SHIFT)
#define GPIO_I_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR0_SHIFT)
#define GPIO_I_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7W_SHIFT)
#define GPIO_I_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6W_SHIFT)
#define GPIO_I_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5W_SHIFT)
#define GPIO_I_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4W_SHIFT)
#define GPIO_I_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3W_SHIFT)
#define GPIO_I_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2W_SHIFT)
#define GPIO_I_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1W_SHIFT)
#define GPIO_I_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0W_SHIFT)
#define GPIO_I_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7R_SHIFT)
#define GPIO_I_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6R_SHIFT)
#define GPIO_I_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5R_SHIFT)
#define GPIO_I_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4R_SHIFT)
#define GPIO_I_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3R_SHIFT)
#define GPIO_I_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2R_SHIFT)
#define GPIO_I_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1R_SHIFT)
#define GPIO_I_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0R_SHIFT)
#define GPIO_I_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_05_0
#define GPIO_I_VM_05_0                  _MK_ADDR_CONST(0x128)
#define GPIO_I_VM_05_0_SECURE                   0x0
#define GPIO_I_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_05_0_WORD_COUNT                       0x1
#define GPIO_I_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM1_SHIFT)
#define GPIO_I_VM_05_0_VM1_RANGE                        1:0
#define GPIO_I_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM2_SHIFT)
#define GPIO_I_VM_05_0_VM2_RANGE                        3:2
#define GPIO_I_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM3_SHIFT)
#define GPIO_I_VM_05_0_VM3_RANGE                        5:4
#define GPIO_I_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM4_SHIFT)
#define GPIO_I_VM_05_0_VM4_RANGE                        7:6
#define GPIO_I_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM5_SHIFT)
#define GPIO_I_VM_05_0_VM5_RANGE                        9:8
#define GPIO_I_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM6_SHIFT)
#define GPIO_I_VM_05_0_VM6_RANGE                        11:10
#define GPIO_I_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM7_SHIFT)
#define GPIO_I_VM_05_0_VM7_RANGE                        13:12
#define GPIO_I_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM8_SHIFT)
#define GPIO_I_VM_05_0_VM8_RANGE                        15:14
#define GPIO_I_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_05_0
#define GPIO_I_SCR_05_0                 _MK_ADDR_CONST(0x12c)
#define GPIO_I_SCR_05_0_SECURE                  0x0
#define GPIO_I_SCR_05_0_SCR                     0
#define GPIO_I_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR7_SHIFT)
#define GPIO_I_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR6_SHIFT)
#define GPIO_I_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR5_SHIFT)
#define GPIO_I_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR4_SHIFT)
#define GPIO_I_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR3_SHIFT)
#define GPIO_I_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR2_SHIFT)
#define GPIO_I_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR1_SHIFT)
#define GPIO_I_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR0_SHIFT)
#define GPIO_I_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7W_SHIFT)
#define GPIO_I_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6W_SHIFT)
#define GPIO_I_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5W_SHIFT)
#define GPIO_I_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4W_SHIFT)
#define GPIO_I_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3W_SHIFT)
#define GPIO_I_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2W_SHIFT)
#define GPIO_I_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1W_SHIFT)
#define GPIO_I_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0W_SHIFT)
#define GPIO_I_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7R_SHIFT)
#define GPIO_I_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6R_SHIFT)
#define GPIO_I_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5R_SHIFT)
#define GPIO_I_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4R_SHIFT)
#define GPIO_I_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3R_SHIFT)
#define GPIO_I_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2R_SHIFT)
#define GPIO_I_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1R_SHIFT)
#define GPIO_I_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0R_SHIFT)
#define GPIO_I_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_06_0
#define GPIO_I_VM_06_0                  _MK_ADDR_CONST(0x130)
#define GPIO_I_VM_06_0_SECURE                   0x0
#define GPIO_I_VM_06_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_06_0_WORD_COUNT                       0x1
#define GPIO_I_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM1_SHIFT)
#define GPIO_I_VM_06_0_VM1_RANGE                        1:0
#define GPIO_I_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM2_SHIFT)
#define GPIO_I_VM_06_0_VM2_RANGE                        3:2
#define GPIO_I_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM3_SHIFT)
#define GPIO_I_VM_06_0_VM3_RANGE                        5:4
#define GPIO_I_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM4_SHIFT)
#define GPIO_I_VM_06_0_VM4_RANGE                        7:6
#define GPIO_I_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM5_SHIFT)
#define GPIO_I_VM_06_0_VM5_RANGE                        9:8
#define GPIO_I_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM6_SHIFT)
#define GPIO_I_VM_06_0_VM6_RANGE                        11:10
#define GPIO_I_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM7_SHIFT)
#define GPIO_I_VM_06_0_VM7_RANGE                        13:12
#define GPIO_I_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM8_SHIFT)
#define GPIO_I_VM_06_0_VM8_RANGE                        15:14
#define GPIO_I_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_06_0
#define GPIO_I_SCR_06_0                 _MK_ADDR_CONST(0x134)
#define GPIO_I_SCR_06_0_SECURE                  0x0
#define GPIO_I_SCR_06_0_SCR                     0
#define GPIO_I_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR7_SHIFT)
#define GPIO_I_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR6_SHIFT)
#define GPIO_I_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR5_SHIFT)
#define GPIO_I_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR4_SHIFT)
#define GPIO_I_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR3_SHIFT)
#define GPIO_I_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR2_SHIFT)
#define GPIO_I_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR1_SHIFT)
#define GPIO_I_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR0_SHIFT)
#define GPIO_I_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7W_SHIFT)
#define GPIO_I_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6W_SHIFT)
#define GPIO_I_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5W_SHIFT)
#define GPIO_I_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4W_SHIFT)
#define GPIO_I_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3W_SHIFT)
#define GPIO_I_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2W_SHIFT)
#define GPIO_I_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1W_SHIFT)
#define GPIO_I_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0W_SHIFT)
#define GPIO_I_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7R_SHIFT)
#define GPIO_I_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6R_SHIFT)
#define GPIO_I_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5R_SHIFT)
#define GPIO_I_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4R_SHIFT)
#define GPIO_I_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3R_SHIFT)
#define GPIO_I_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2R_SHIFT)
#define GPIO_I_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1R_SHIFT)
#define GPIO_I_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0R_SHIFT)
#define GPIO_I_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_I_VM_07_0
#define GPIO_I_VM_07_0                  _MK_ADDR_CONST(0x138)
#define GPIO_I_VM_07_0_SECURE                   0x0
#define GPIO_I_VM_07_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_I_VM_07_0_WORD_COUNT                       0x1
#define GPIO_I_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM1_SHIFT)
#define GPIO_I_VM_07_0_VM1_RANGE                        1:0
#define GPIO_I_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM2_SHIFT)
#define GPIO_I_VM_07_0_VM2_RANGE                        3:2
#define GPIO_I_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM3_SHIFT)
#define GPIO_I_VM_07_0_VM3_RANGE                        5:4
#define GPIO_I_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM4_SHIFT)
#define GPIO_I_VM_07_0_VM4_RANGE                        7:6
#define GPIO_I_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM5_SHIFT)
#define GPIO_I_VM_07_0_VM5_RANGE                        9:8
#define GPIO_I_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM6_SHIFT)
#define GPIO_I_VM_07_0_VM6_RANGE                        11:10
#define GPIO_I_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM7_SHIFT)
#define GPIO_I_VM_07_0_VM7_RANGE                        13:12
#define GPIO_I_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_I_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_07_0_VM8_SHIFT)
#define GPIO_I_VM_07_0_VM8_RANGE                        15:14
#define GPIO_I_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_SCR_07_0
#define GPIO_I_SCR_07_0                 _MK_ADDR_CONST(0x13c)
#define GPIO_I_SCR_07_0_SECURE                  0x0
#define GPIO_I_SCR_07_0_SCR                     0
#define GPIO_I_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR7_SHIFT)
#define GPIO_I_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR6_SHIFT)
#define GPIO_I_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR5_SHIFT)
#define GPIO_I_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR4_SHIFT)
#define GPIO_I_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR3_SHIFT)
#define GPIO_I_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR2_SHIFT)
#define GPIO_I_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR1_SHIFT)
#define GPIO_I_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_PR0_SHIFT)
#define GPIO_I_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G7W_SHIFT)
#define GPIO_I_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G6W_SHIFT)
#define GPIO_I_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G5W_SHIFT)
#define GPIO_I_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G4W_SHIFT)
#define GPIO_I_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G3W_SHIFT)
#define GPIO_I_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G2W_SHIFT)
#define GPIO_I_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G1W_SHIFT)
#define GPIO_I_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G0W_SHIFT)
#define GPIO_I_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G7R_SHIFT)
#define GPIO_I_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G6R_SHIFT)
#define GPIO_I_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G5R_SHIFT)
#define GPIO_I_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G4R_SHIFT)
#define GPIO_I_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G3R_SHIFT)
#define GPIO_I_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G2R_SHIFT)
#define GPIO_I_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G1R_SHIFT)
#define GPIO_I_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_I_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_07_0_G0R_SHIFT)
#define GPIO_I_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_00_0
#define GPIO_R_VM_00_0                  _MK_ADDR_CONST(0x140)
#define GPIO_R_VM_00_0_SECURE                   0x0
#define GPIO_R_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_00_0_WORD_COUNT                       0x1
#define GPIO_R_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM1_SHIFT)
#define GPIO_R_VM_00_0_VM1_RANGE                        1:0
#define GPIO_R_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM2_SHIFT)
#define GPIO_R_VM_00_0_VM2_RANGE                        3:2
#define GPIO_R_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM3_SHIFT)
#define GPIO_R_VM_00_0_VM3_RANGE                        5:4
#define GPIO_R_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM4_SHIFT)
#define GPIO_R_VM_00_0_VM4_RANGE                        7:6
#define GPIO_R_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM5_SHIFT)
#define GPIO_R_VM_00_0_VM5_RANGE                        9:8
#define GPIO_R_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM6_SHIFT)
#define GPIO_R_VM_00_0_VM6_RANGE                        11:10
#define GPIO_R_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM7_SHIFT)
#define GPIO_R_VM_00_0_VM7_RANGE                        13:12
#define GPIO_R_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM8_SHIFT)
#define GPIO_R_VM_00_0_VM8_RANGE                        15:14
#define GPIO_R_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_00_0
#define GPIO_R_SCR_00_0                 _MK_ADDR_CONST(0x144)
#define GPIO_R_SCR_00_0_SECURE                  0x0
#define GPIO_R_SCR_00_0_SCR                     0
#define GPIO_R_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR7_SHIFT)
#define GPIO_R_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR6_SHIFT)
#define GPIO_R_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR5_SHIFT)
#define GPIO_R_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR4_SHIFT)
#define GPIO_R_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR3_SHIFT)
#define GPIO_R_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR2_SHIFT)
#define GPIO_R_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR1_SHIFT)
#define GPIO_R_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR0_SHIFT)
#define GPIO_R_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7W_SHIFT)
#define GPIO_R_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6W_SHIFT)
#define GPIO_R_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5W_SHIFT)
#define GPIO_R_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4W_SHIFT)
#define GPIO_R_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3W_SHIFT)
#define GPIO_R_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2W_SHIFT)
#define GPIO_R_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1W_SHIFT)
#define GPIO_R_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0W_SHIFT)
#define GPIO_R_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7R_SHIFT)
#define GPIO_R_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6R_SHIFT)
#define GPIO_R_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5R_SHIFT)
#define GPIO_R_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4R_SHIFT)
#define GPIO_R_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3R_SHIFT)
#define GPIO_R_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2R_SHIFT)
#define GPIO_R_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1R_SHIFT)
#define GPIO_R_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0R_SHIFT)
#define GPIO_R_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_01_0
#define GPIO_R_VM_01_0                  _MK_ADDR_CONST(0x148)
#define GPIO_R_VM_01_0_SECURE                   0x0
#define GPIO_R_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_01_0_WORD_COUNT                       0x1
#define GPIO_R_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM1_SHIFT)
#define GPIO_R_VM_01_0_VM1_RANGE                        1:0
#define GPIO_R_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM2_SHIFT)
#define GPIO_R_VM_01_0_VM2_RANGE                        3:2
#define GPIO_R_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM3_SHIFT)
#define GPIO_R_VM_01_0_VM3_RANGE                        5:4
#define GPIO_R_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM4_SHIFT)
#define GPIO_R_VM_01_0_VM4_RANGE                        7:6
#define GPIO_R_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM5_SHIFT)
#define GPIO_R_VM_01_0_VM5_RANGE                        9:8
#define GPIO_R_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM6_SHIFT)
#define GPIO_R_VM_01_0_VM6_RANGE                        11:10
#define GPIO_R_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM7_SHIFT)
#define GPIO_R_VM_01_0_VM7_RANGE                        13:12
#define GPIO_R_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM8_SHIFT)
#define GPIO_R_VM_01_0_VM8_RANGE                        15:14
#define GPIO_R_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_01_0
#define GPIO_R_SCR_01_0                 _MK_ADDR_CONST(0x14c)
#define GPIO_R_SCR_01_0_SECURE                  0x0
#define GPIO_R_SCR_01_0_SCR                     0
#define GPIO_R_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR7_SHIFT)
#define GPIO_R_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR6_SHIFT)
#define GPIO_R_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR5_SHIFT)
#define GPIO_R_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR4_SHIFT)
#define GPIO_R_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR3_SHIFT)
#define GPIO_R_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR2_SHIFT)
#define GPIO_R_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR1_SHIFT)
#define GPIO_R_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR0_SHIFT)
#define GPIO_R_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7W_SHIFT)
#define GPIO_R_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6W_SHIFT)
#define GPIO_R_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5W_SHIFT)
#define GPIO_R_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4W_SHIFT)
#define GPIO_R_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3W_SHIFT)
#define GPIO_R_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2W_SHIFT)
#define GPIO_R_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1W_SHIFT)
#define GPIO_R_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0W_SHIFT)
#define GPIO_R_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7R_SHIFT)
#define GPIO_R_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6R_SHIFT)
#define GPIO_R_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5R_SHIFT)
#define GPIO_R_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4R_SHIFT)
#define GPIO_R_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3R_SHIFT)
#define GPIO_R_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2R_SHIFT)
#define GPIO_R_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1R_SHIFT)
#define GPIO_R_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0R_SHIFT)
#define GPIO_R_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_02_0
#define GPIO_R_VM_02_0                  _MK_ADDR_CONST(0x150)
#define GPIO_R_VM_02_0_SECURE                   0x0
#define GPIO_R_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_02_0_WORD_COUNT                       0x1
#define GPIO_R_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM1_SHIFT)
#define GPIO_R_VM_02_0_VM1_RANGE                        1:0
#define GPIO_R_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM2_SHIFT)
#define GPIO_R_VM_02_0_VM2_RANGE                        3:2
#define GPIO_R_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM3_SHIFT)
#define GPIO_R_VM_02_0_VM3_RANGE                        5:4
#define GPIO_R_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM4_SHIFT)
#define GPIO_R_VM_02_0_VM4_RANGE                        7:6
#define GPIO_R_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM5_SHIFT)
#define GPIO_R_VM_02_0_VM5_RANGE                        9:8
#define GPIO_R_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM6_SHIFT)
#define GPIO_R_VM_02_0_VM6_RANGE                        11:10
#define GPIO_R_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM7_SHIFT)
#define GPIO_R_VM_02_0_VM7_RANGE                        13:12
#define GPIO_R_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM8_SHIFT)
#define GPIO_R_VM_02_0_VM8_RANGE                        15:14
#define GPIO_R_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_02_0
#define GPIO_R_SCR_02_0                 _MK_ADDR_CONST(0x154)
#define GPIO_R_SCR_02_0_SECURE                  0x0
#define GPIO_R_SCR_02_0_SCR                     0
#define GPIO_R_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR7_SHIFT)
#define GPIO_R_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR6_SHIFT)
#define GPIO_R_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR5_SHIFT)
#define GPIO_R_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR4_SHIFT)
#define GPIO_R_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR3_SHIFT)
#define GPIO_R_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR2_SHIFT)
#define GPIO_R_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR1_SHIFT)
#define GPIO_R_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR0_SHIFT)
#define GPIO_R_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7W_SHIFT)
#define GPIO_R_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6W_SHIFT)
#define GPIO_R_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5W_SHIFT)
#define GPIO_R_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4W_SHIFT)
#define GPIO_R_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3W_SHIFT)
#define GPIO_R_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2W_SHIFT)
#define GPIO_R_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1W_SHIFT)
#define GPIO_R_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0W_SHIFT)
#define GPIO_R_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7R_SHIFT)
#define GPIO_R_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6R_SHIFT)
#define GPIO_R_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5R_SHIFT)
#define GPIO_R_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4R_SHIFT)
#define GPIO_R_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3R_SHIFT)
#define GPIO_R_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2R_SHIFT)
#define GPIO_R_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1R_SHIFT)
#define GPIO_R_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0R_SHIFT)
#define GPIO_R_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_03_0
#define GPIO_R_VM_03_0                  _MK_ADDR_CONST(0x158)
#define GPIO_R_VM_03_0_SECURE                   0x0
#define GPIO_R_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_03_0_WORD_COUNT                       0x1
#define GPIO_R_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM1_SHIFT)
#define GPIO_R_VM_03_0_VM1_RANGE                        1:0
#define GPIO_R_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM2_SHIFT)
#define GPIO_R_VM_03_0_VM2_RANGE                        3:2
#define GPIO_R_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM3_SHIFT)
#define GPIO_R_VM_03_0_VM3_RANGE                        5:4
#define GPIO_R_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM4_SHIFT)
#define GPIO_R_VM_03_0_VM4_RANGE                        7:6
#define GPIO_R_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM5_SHIFT)
#define GPIO_R_VM_03_0_VM5_RANGE                        9:8
#define GPIO_R_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM6_SHIFT)
#define GPIO_R_VM_03_0_VM6_RANGE                        11:10
#define GPIO_R_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM7_SHIFT)
#define GPIO_R_VM_03_0_VM7_RANGE                        13:12
#define GPIO_R_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM8_SHIFT)
#define GPIO_R_VM_03_0_VM8_RANGE                        15:14
#define GPIO_R_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_03_0
#define GPIO_R_SCR_03_0                 _MK_ADDR_CONST(0x15c)
#define GPIO_R_SCR_03_0_SECURE                  0x0
#define GPIO_R_SCR_03_0_SCR                     0
#define GPIO_R_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR7_SHIFT)
#define GPIO_R_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR6_SHIFT)
#define GPIO_R_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR5_SHIFT)
#define GPIO_R_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR4_SHIFT)
#define GPIO_R_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR3_SHIFT)
#define GPIO_R_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR2_SHIFT)
#define GPIO_R_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR1_SHIFT)
#define GPIO_R_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR0_SHIFT)
#define GPIO_R_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7W_SHIFT)
#define GPIO_R_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6W_SHIFT)
#define GPIO_R_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5W_SHIFT)
#define GPIO_R_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4W_SHIFT)
#define GPIO_R_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3W_SHIFT)
#define GPIO_R_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2W_SHIFT)
#define GPIO_R_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1W_SHIFT)
#define GPIO_R_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0W_SHIFT)
#define GPIO_R_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7R_SHIFT)
#define GPIO_R_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6R_SHIFT)
#define GPIO_R_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5R_SHIFT)
#define GPIO_R_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4R_SHIFT)
#define GPIO_R_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3R_SHIFT)
#define GPIO_R_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2R_SHIFT)
#define GPIO_R_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1R_SHIFT)
#define GPIO_R_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0R_SHIFT)
#define GPIO_R_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_04_0
#define GPIO_R_VM_04_0                  _MK_ADDR_CONST(0x160)
#define GPIO_R_VM_04_0_SECURE                   0x0
#define GPIO_R_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_04_0_WORD_COUNT                       0x1
#define GPIO_R_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM1_SHIFT)
#define GPIO_R_VM_04_0_VM1_RANGE                        1:0
#define GPIO_R_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM2_SHIFT)
#define GPIO_R_VM_04_0_VM2_RANGE                        3:2
#define GPIO_R_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM3_SHIFT)
#define GPIO_R_VM_04_0_VM3_RANGE                        5:4
#define GPIO_R_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM4_SHIFT)
#define GPIO_R_VM_04_0_VM4_RANGE                        7:6
#define GPIO_R_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM5_SHIFT)
#define GPIO_R_VM_04_0_VM5_RANGE                        9:8
#define GPIO_R_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM6_SHIFT)
#define GPIO_R_VM_04_0_VM6_RANGE                        11:10
#define GPIO_R_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM7_SHIFT)
#define GPIO_R_VM_04_0_VM7_RANGE                        13:12
#define GPIO_R_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM8_SHIFT)
#define GPIO_R_VM_04_0_VM8_RANGE                        15:14
#define GPIO_R_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_04_0
#define GPIO_R_SCR_04_0                 _MK_ADDR_CONST(0x164)
#define GPIO_R_SCR_04_0_SECURE                  0x0
#define GPIO_R_SCR_04_0_SCR                     0
#define GPIO_R_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR7_SHIFT)
#define GPIO_R_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR6_SHIFT)
#define GPIO_R_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR5_SHIFT)
#define GPIO_R_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR4_SHIFT)
#define GPIO_R_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR3_SHIFT)
#define GPIO_R_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR2_SHIFT)
#define GPIO_R_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR1_SHIFT)
#define GPIO_R_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR0_SHIFT)
#define GPIO_R_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7W_SHIFT)
#define GPIO_R_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6W_SHIFT)
#define GPIO_R_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5W_SHIFT)
#define GPIO_R_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4W_SHIFT)
#define GPIO_R_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3W_SHIFT)
#define GPIO_R_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2W_SHIFT)
#define GPIO_R_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1W_SHIFT)
#define GPIO_R_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0W_SHIFT)
#define GPIO_R_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7R_SHIFT)
#define GPIO_R_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6R_SHIFT)
#define GPIO_R_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5R_SHIFT)
#define GPIO_R_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4R_SHIFT)
#define GPIO_R_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3R_SHIFT)
#define GPIO_R_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2R_SHIFT)
#define GPIO_R_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1R_SHIFT)
#define GPIO_R_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0R_SHIFT)
#define GPIO_R_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_R_VM_05_0
#define GPIO_R_VM_05_0                  _MK_ADDR_CONST(0x168)
#define GPIO_R_VM_05_0_SECURE                   0x0
#define GPIO_R_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_R_VM_05_0_WORD_COUNT                       0x1
#define GPIO_R_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM1_SHIFT)
#define GPIO_R_VM_05_0_VM1_RANGE                        1:0
#define GPIO_R_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM2_SHIFT)
#define GPIO_R_VM_05_0_VM2_RANGE                        3:2
#define GPIO_R_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM3_SHIFT)
#define GPIO_R_VM_05_0_VM3_RANGE                        5:4
#define GPIO_R_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM4_SHIFT)
#define GPIO_R_VM_05_0_VM4_RANGE                        7:6
#define GPIO_R_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM5_SHIFT)
#define GPIO_R_VM_05_0_VM5_RANGE                        9:8
#define GPIO_R_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM6_SHIFT)
#define GPIO_R_VM_05_0_VM6_RANGE                        11:10
#define GPIO_R_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM7_SHIFT)
#define GPIO_R_VM_05_0_VM7_RANGE                        13:12
#define GPIO_R_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_R_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM8_SHIFT)
#define GPIO_R_VM_05_0_VM8_RANGE                        15:14
#define GPIO_R_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_SCR_05_0
#define GPIO_R_SCR_05_0                 _MK_ADDR_CONST(0x16c)
#define GPIO_R_SCR_05_0_SECURE                  0x0
#define GPIO_R_SCR_05_0_SCR                     0
#define GPIO_R_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR7_SHIFT)
#define GPIO_R_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR6_SHIFT)
#define GPIO_R_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR5_SHIFT)
#define GPIO_R_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR4_SHIFT)
#define GPIO_R_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR3_SHIFT)
#define GPIO_R_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR2_SHIFT)
#define GPIO_R_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR1_SHIFT)
#define GPIO_R_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR0_SHIFT)
#define GPIO_R_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7W_SHIFT)
#define GPIO_R_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6W_SHIFT)
#define GPIO_R_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5W_SHIFT)
#define GPIO_R_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4W_SHIFT)
#define GPIO_R_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3W_SHIFT)
#define GPIO_R_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2W_SHIFT)
#define GPIO_R_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1W_SHIFT)
#define GPIO_R_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0W_SHIFT)
#define GPIO_R_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7R_SHIFT)
#define GPIO_R_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6R_SHIFT)
#define GPIO_R_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5R_SHIFT)
#define GPIO_R_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4R_SHIFT)
#define GPIO_R_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3R_SHIFT)
#define GPIO_R_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2R_SHIFT)
#define GPIO_R_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1R_SHIFT)
#define GPIO_R_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_R_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0R_SHIFT)
#define GPIO_R_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 368 [0x170]

// Reserved address 372 [0x174]

// Reserved address 376 [0x178]

// Reserved address 380 [0x17c]

// Register GPIO_CTL0_VM_SCR_0
#define GPIO_CTL0_VM_SCR_0                      _MK_ADDR_CONST(0x800)
#define GPIO_CTL0_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL0_VM_SCR_0_SCR                  0
#define GPIO_CTL0_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL0_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL0_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL0_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL0_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL0_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL0_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL0_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL0_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL0_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL0_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL0_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL0_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL0_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL0_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL0_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL0_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL0_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL0_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL0_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL0_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL0_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL0_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL0_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL0_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL0_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL0_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL0_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL0_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL0_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL0_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL0_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL0_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL0_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL0_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL0_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL0_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL0_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL0_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL0_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL0_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL0_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL0_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL0_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL0_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL0_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL0_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL0_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL0_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL0_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL0_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL0_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x804)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x808)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL0_SCR_0
#define GPIO_CTL0_SCR_0                 _MK_ADDR_CONST(0x80c)
#define GPIO_CTL0_SCR_0_SECURE                  0x0
#define GPIO_CTL0_SCR_0_SCR                     0
#define GPIO_CTL0_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL0_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL0_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL0_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL0_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL0_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL0_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL0_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL0_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL0_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL0_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL0_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL0_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL0_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL0_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL0_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL0_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL0_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL0_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL0_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL0_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL0_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL0_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL0_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL0_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL0_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL0_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL0_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL0_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL0_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL0_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL0_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL0_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL0_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL0_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL0_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL0_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL0_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL0_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL0_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL0_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL0_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL0_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL0_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL0_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL0_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL0_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL0_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL0_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL0_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL0_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL0_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL0_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL0_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL0_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL0_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL0_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL0_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL0_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL0_ICG_EN_OVERRIDE_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x810)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL0_SPARE_0
#define GPIO_CTL0_SPARE_0                       _MK_ADDR_CONST(0x814)
#define GPIO_CTL0_SPARE_0_SECURE                        0x0
#define GPIO_CTL0_SPARE_0_SCR                   0
#define GPIO_CTL0_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL0_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL0_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL0_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL0_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL0_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_00_0
#define GPIO_H_VM_00_0                  _MK_ADDR_CONST(0x1000)
#define GPIO_H_VM_00_0_SECURE                   0x0
#define GPIO_H_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_00_0_WORD_COUNT                       0x1
#define GPIO_H_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM1_SHIFT)
#define GPIO_H_VM_00_0_VM1_RANGE                        1:0
#define GPIO_H_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM2_SHIFT)
#define GPIO_H_VM_00_0_VM2_RANGE                        3:2
#define GPIO_H_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM3_SHIFT)
#define GPIO_H_VM_00_0_VM3_RANGE                        5:4
#define GPIO_H_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM4_SHIFT)
#define GPIO_H_VM_00_0_VM4_RANGE                        7:6
#define GPIO_H_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM5_SHIFT)
#define GPIO_H_VM_00_0_VM5_RANGE                        9:8
#define GPIO_H_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM6_SHIFT)
#define GPIO_H_VM_00_0_VM6_RANGE                        11:10
#define GPIO_H_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM7_SHIFT)
#define GPIO_H_VM_00_0_VM7_RANGE                        13:12
#define GPIO_H_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM8_SHIFT)
#define GPIO_H_VM_00_0_VM8_RANGE                        15:14
#define GPIO_H_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_00_0
#define GPIO_H_SCR_00_0                 _MK_ADDR_CONST(0x1004)
#define GPIO_H_SCR_00_0_SECURE                  0x0
#define GPIO_H_SCR_00_0_SCR                     0
#define GPIO_H_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR7_SHIFT)
#define GPIO_H_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR6_SHIFT)
#define GPIO_H_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR5_SHIFT)
#define GPIO_H_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR4_SHIFT)
#define GPIO_H_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR3_SHIFT)
#define GPIO_H_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR2_SHIFT)
#define GPIO_H_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR1_SHIFT)
#define GPIO_H_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR0_SHIFT)
#define GPIO_H_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7W_SHIFT)
#define GPIO_H_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6W_SHIFT)
#define GPIO_H_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5W_SHIFT)
#define GPIO_H_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4W_SHIFT)
#define GPIO_H_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3W_SHIFT)
#define GPIO_H_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2W_SHIFT)
#define GPIO_H_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1W_SHIFT)
#define GPIO_H_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0W_SHIFT)
#define GPIO_H_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7R_SHIFT)
#define GPIO_H_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6R_SHIFT)
#define GPIO_H_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5R_SHIFT)
#define GPIO_H_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4R_SHIFT)
#define GPIO_H_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3R_SHIFT)
#define GPIO_H_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2R_SHIFT)
#define GPIO_H_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1R_SHIFT)
#define GPIO_H_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0R_SHIFT)
#define GPIO_H_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_01_0
#define GPIO_H_VM_01_0                  _MK_ADDR_CONST(0x1008)
#define GPIO_H_VM_01_0_SECURE                   0x0
#define GPIO_H_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_01_0_WORD_COUNT                       0x1
#define GPIO_H_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM1_SHIFT)
#define GPIO_H_VM_01_0_VM1_RANGE                        1:0
#define GPIO_H_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM2_SHIFT)
#define GPIO_H_VM_01_0_VM2_RANGE                        3:2
#define GPIO_H_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM3_SHIFT)
#define GPIO_H_VM_01_0_VM3_RANGE                        5:4
#define GPIO_H_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM4_SHIFT)
#define GPIO_H_VM_01_0_VM4_RANGE                        7:6
#define GPIO_H_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM5_SHIFT)
#define GPIO_H_VM_01_0_VM5_RANGE                        9:8
#define GPIO_H_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM6_SHIFT)
#define GPIO_H_VM_01_0_VM6_RANGE                        11:10
#define GPIO_H_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM7_SHIFT)
#define GPIO_H_VM_01_0_VM7_RANGE                        13:12
#define GPIO_H_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM8_SHIFT)
#define GPIO_H_VM_01_0_VM8_RANGE                        15:14
#define GPIO_H_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_01_0
#define GPIO_H_SCR_01_0                 _MK_ADDR_CONST(0x100c)
#define GPIO_H_SCR_01_0_SECURE                  0x0
#define GPIO_H_SCR_01_0_SCR                     0
#define GPIO_H_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR7_SHIFT)
#define GPIO_H_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR6_SHIFT)
#define GPIO_H_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR5_SHIFT)
#define GPIO_H_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR4_SHIFT)
#define GPIO_H_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR3_SHIFT)
#define GPIO_H_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR2_SHIFT)
#define GPIO_H_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR1_SHIFT)
#define GPIO_H_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR0_SHIFT)
#define GPIO_H_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7W_SHIFT)
#define GPIO_H_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6W_SHIFT)
#define GPIO_H_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5W_SHIFT)
#define GPIO_H_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4W_SHIFT)
#define GPIO_H_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3W_SHIFT)
#define GPIO_H_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2W_SHIFT)
#define GPIO_H_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1W_SHIFT)
#define GPIO_H_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0W_SHIFT)
#define GPIO_H_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7R_SHIFT)
#define GPIO_H_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6R_SHIFT)
#define GPIO_H_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5R_SHIFT)
#define GPIO_H_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4R_SHIFT)
#define GPIO_H_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3R_SHIFT)
#define GPIO_H_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2R_SHIFT)
#define GPIO_H_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1R_SHIFT)
#define GPIO_H_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0R_SHIFT)
#define GPIO_H_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_02_0
#define GPIO_H_VM_02_0                  _MK_ADDR_CONST(0x1010)
#define GPIO_H_VM_02_0_SECURE                   0x0
#define GPIO_H_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_02_0_WORD_COUNT                       0x1
#define GPIO_H_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM1_SHIFT)
#define GPIO_H_VM_02_0_VM1_RANGE                        1:0
#define GPIO_H_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM2_SHIFT)
#define GPIO_H_VM_02_0_VM2_RANGE                        3:2
#define GPIO_H_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM3_SHIFT)
#define GPIO_H_VM_02_0_VM3_RANGE                        5:4
#define GPIO_H_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM4_SHIFT)
#define GPIO_H_VM_02_0_VM4_RANGE                        7:6
#define GPIO_H_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM5_SHIFT)
#define GPIO_H_VM_02_0_VM5_RANGE                        9:8
#define GPIO_H_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM6_SHIFT)
#define GPIO_H_VM_02_0_VM6_RANGE                        11:10
#define GPIO_H_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM7_SHIFT)
#define GPIO_H_VM_02_0_VM7_RANGE                        13:12
#define GPIO_H_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM8_SHIFT)
#define GPIO_H_VM_02_0_VM8_RANGE                        15:14
#define GPIO_H_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_02_0
#define GPIO_H_SCR_02_0                 _MK_ADDR_CONST(0x1014)
#define GPIO_H_SCR_02_0_SECURE                  0x0
#define GPIO_H_SCR_02_0_SCR                     0
#define GPIO_H_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR7_SHIFT)
#define GPIO_H_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR6_SHIFT)
#define GPIO_H_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR5_SHIFT)
#define GPIO_H_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR4_SHIFT)
#define GPIO_H_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR3_SHIFT)
#define GPIO_H_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR2_SHIFT)
#define GPIO_H_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR1_SHIFT)
#define GPIO_H_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR0_SHIFT)
#define GPIO_H_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7W_SHIFT)
#define GPIO_H_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6W_SHIFT)
#define GPIO_H_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5W_SHIFT)
#define GPIO_H_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4W_SHIFT)
#define GPIO_H_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3W_SHIFT)
#define GPIO_H_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2W_SHIFT)
#define GPIO_H_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1W_SHIFT)
#define GPIO_H_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0W_SHIFT)
#define GPIO_H_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7R_SHIFT)
#define GPIO_H_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6R_SHIFT)
#define GPIO_H_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5R_SHIFT)
#define GPIO_H_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4R_SHIFT)
#define GPIO_H_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3R_SHIFT)
#define GPIO_H_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2R_SHIFT)
#define GPIO_H_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1R_SHIFT)
#define GPIO_H_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0R_SHIFT)
#define GPIO_H_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_03_0
#define GPIO_H_VM_03_0                  _MK_ADDR_CONST(0x1018)
#define GPIO_H_VM_03_0_SECURE                   0x0
#define GPIO_H_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_03_0_WORD_COUNT                       0x1
#define GPIO_H_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM1_SHIFT)
#define GPIO_H_VM_03_0_VM1_RANGE                        1:0
#define GPIO_H_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM2_SHIFT)
#define GPIO_H_VM_03_0_VM2_RANGE                        3:2
#define GPIO_H_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM3_SHIFT)
#define GPIO_H_VM_03_0_VM3_RANGE                        5:4
#define GPIO_H_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM4_SHIFT)
#define GPIO_H_VM_03_0_VM4_RANGE                        7:6
#define GPIO_H_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM5_SHIFT)
#define GPIO_H_VM_03_0_VM5_RANGE                        9:8
#define GPIO_H_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM6_SHIFT)
#define GPIO_H_VM_03_0_VM6_RANGE                        11:10
#define GPIO_H_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM7_SHIFT)
#define GPIO_H_VM_03_0_VM7_RANGE                        13:12
#define GPIO_H_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM8_SHIFT)
#define GPIO_H_VM_03_0_VM8_RANGE                        15:14
#define GPIO_H_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_03_0
#define GPIO_H_SCR_03_0                 _MK_ADDR_CONST(0x101c)
#define GPIO_H_SCR_03_0_SECURE                  0x0
#define GPIO_H_SCR_03_0_SCR                     0
#define GPIO_H_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR7_SHIFT)
#define GPIO_H_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR6_SHIFT)
#define GPIO_H_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR5_SHIFT)
#define GPIO_H_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR4_SHIFT)
#define GPIO_H_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR3_SHIFT)
#define GPIO_H_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR2_SHIFT)
#define GPIO_H_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR1_SHIFT)
#define GPIO_H_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR0_SHIFT)
#define GPIO_H_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7W_SHIFT)
#define GPIO_H_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6W_SHIFT)
#define GPIO_H_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5W_SHIFT)
#define GPIO_H_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4W_SHIFT)
#define GPIO_H_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3W_SHIFT)
#define GPIO_H_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2W_SHIFT)
#define GPIO_H_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1W_SHIFT)
#define GPIO_H_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0W_SHIFT)
#define GPIO_H_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7R_SHIFT)
#define GPIO_H_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6R_SHIFT)
#define GPIO_H_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5R_SHIFT)
#define GPIO_H_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4R_SHIFT)
#define GPIO_H_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3R_SHIFT)
#define GPIO_H_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2R_SHIFT)
#define GPIO_H_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1R_SHIFT)
#define GPIO_H_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0R_SHIFT)
#define GPIO_H_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_04_0
#define GPIO_H_VM_04_0                  _MK_ADDR_CONST(0x1020)
#define GPIO_H_VM_04_0_SECURE                   0x0
#define GPIO_H_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_04_0_WORD_COUNT                       0x1
#define GPIO_H_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM1_SHIFT)
#define GPIO_H_VM_04_0_VM1_RANGE                        1:0
#define GPIO_H_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM2_SHIFT)
#define GPIO_H_VM_04_0_VM2_RANGE                        3:2
#define GPIO_H_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM3_SHIFT)
#define GPIO_H_VM_04_0_VM3_RANGE                        5:4
#define GPIO_H_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM4_SHIFT)
#define GPIO_H_VM_04_0_VM4_RANGE                        7:6
#define GPIO_H_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM5_SHIFT)
#define GPIO_H_VM_04_0_VM5_RANGE                        9:8
#define GPIO_H_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM6_SHIFT)
#define GPIO_H_VM_04_0_VM6_RANGE                        11:10
#define GPIO_H_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM7_SHIFT)
#define GPIO_H_VM_04_0_VM7_RANGE                        13:12
#define GPIO_H_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM8_SHIFT)
#define GPIO_H_VM_04_0_VM8_RANGE                        15:14
#define GPIO_H_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_04_0
#define GPIO_H_SCR_04_0                 _MK_ADDR_CONST(0x1024)
#define GPIO_H_SCR_04_0_SECURE                  0x0
#define GPIO_H_SCR_04_0_SCR                     0
#define GPIO_H_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR7_SHIFT)
#define GPIO_H_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR6_SHIFT)
#define GPIO_H_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR5_SHIFT)
#define GPIO_H_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR4_SHIFT)
#define GPIO_H_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR3_SHIFT)
#define GPIO_H_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR2_SHIFT)
#define GPIO_H_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR1_SHIFT)
#define GPIO_H_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR0_SHIFT)
#define GPIO_H_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7W_SHIFT)
#define GPIO_H_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6W_SHIFT)
#define GPIO_H_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5W_SHIFT)
#define GPIO_H_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4W_SHIFT)
#define GPIO_H_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3W_SHIFT)
#define GPIO_H_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2W_SHIFT)
#define GPIO_H_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1W_SHIFT)
#define GPIO_H_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0W_SHIFT)
#define GPIO_H_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7R_SHIFT)
#define GPIO_H_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6R_SHIFT)
#define GPIO_H_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5R_SHIFT)
#define GPIO_H_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4R_SHIFT)
#define GPIO_H_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3R_SHIFT)
#define GPIO_H_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2R_SHIFT)
#define GPIO_H_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1R_SHIFT)
#define GPIO_H_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0R_SHIFT)
#define GPIO_H_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_05_0
#define GPIO_H_VM_05_0                  _MK_ADDR_CONST(0x1028)
#define GPIO_H_VM_05_0_SECURE                   0x0
#define GPIO_H_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_05_0_WORD_COUNT                       0x1
#define GPIO_H_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM1_SHIFT)
#define GPIO_H_VM_05_0_VM1_RANGE                        1:0
#define GPIO_H_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM2_SHIFT)
#define GPIO_H_VM_05_0_VM2_RANGE                        3:2
#define GPIO_H_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM3_SHIFT)
#define GPIO_H_VM_05_0_VM3_RANGE                        5:4
#define GPIO_H_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM4_SHIFT)
#define GPIO_H_VM_05_0_VM4_RANGE                        7:6
#define GPIO_H_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM5_SHIFT)
#define GPIO_H_VM_05_0_VM5_RANGE                        9:8
#define GPIO_H_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM6_SHIFT)
#define GPIO_H_VM_05_0_VM6_RANGE                        11:10
#define GPIO_H_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM7_SHIFT)
#define GPIO_H_VM_05_0_VM7_RANGE                        13:12
#define GPIO_H_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM8_SHIFT)
#define GPIO_H_VM_05_0_VM8_RANGE                        15:14
#define GPIO_H_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_05_0
#define GPIO_H_SCR_05_0                 _MK_ADDR_CONST(0x102c)
#define GPIO_H_SCR_05_0_SECURE                  0x0
#define GPIO_H_SCR_05_0_SCR                     0
#define GPIO_H_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR7_SHIFT)
#define GPIO_H_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR6_SHIFT)
#define GPIO_H_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR5_SHIFT)
#define GPIO_H_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR4_SHIFT)
#define GPIO_H_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR3_SHIFT)
#define GPIO_H_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR2_SHIFT)
#define GPIO_H_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR1_SHIFT)
#define GPIO_H_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR0_SHIFT)
#define GPIO_H_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7W_SHIFT)
#define GPIO_H_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6W_SHIFT)
#define GPIO_H_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5W_SHIFT)
#define GPIO_H_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4W_SHIFT)
#define GPIO_H_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3W_SHIFT)
#define GPIO_H_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2W_SHIFT)
#define GPIO_H_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1W_SHIFT)
#define GPIO_H_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0W_SHIFT)
#define GPIO_H_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7R_SHIFT)
#define GPIO_H_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6R_SHIFT)
#define GPIO_H_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5R_SHIFT)
#define GPIO_H_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4R_SHIFT)
#define GPIO_H_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3R_SHIFT)
#define GPIO_H_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2R_SHIFT)
#define GPIO_H_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1R_SHIFT)
#define GPIO_H_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0R_SHIFT)
#define GPIO_H_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_H_VM_06_0
#define GPIO_H_VM_06_0                  _MK_ADDR_CONST(0x1030)
#define GPIO_H_VM_06_0_SECURE                   0x0
#define GPIO_H_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_H_VM_06_0_WORD_COUNT                       0x1
#define GPIO_H_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM1_SHIFT)
#define GPIO_H_VM_06_0_VM1_RANGE                        1:0
#define GPIO_H_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM2_SHIFT)
#define GPIO_H_VM_06_0_VM2_RANGE                        3:2
#define GPIO_H_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM3_SHIFT)
#define GPIO_H_VM_06_0_VM3_RANGE                        5:4
#define GPIO_H_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM4_SHIFT)
#define GPIO_H_VM_06_0_VM4_RANGE                        7:6
#define GPIO_H_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM5_SHIFT)
#define GPIO_H_VM_06_0_VM5_RANGE                        9:8
#define GPIO_H_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM6_SHIFT)
#define GPIO_H_VM_06_0_VM6_RANGE                        11:10
#define GPIO_H_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM7_SHIFT)
#define GPIO_H_VM_06_0_VM7_RANGE                        13:12
#define GPIO_H_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_H_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM8_SHIFT)
#define GPIO_H_VM_06_0_VM8_RANGE                        15:14
#define GPIO_H_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_SCR_06_0
#define GPIO_H_SCR_06_0                 _MK_ADDR_CONST(0x1034)
#define GPIO_H_SCR_06_0_SECURE                  0x0
#define GPIO_H_SCR_06_0_SCR                     0
#define GPIO_H_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR7_SHIFT)
#define GPIO_H_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR6_SHIFT)
#define GPIO_H_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR5_SHIFT)
#define GPIO_H_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR4_SHIFT)
#define GPIO_H_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR3_SHIFT)
#define GPIO_H_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR2_SHIFT)
#define GPIO_H_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR1_SHIFT)
#define GPIO_H_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR0_SHIFT)
#define GPIO_H_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7W_SHIFT)
#define GPIO_H_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6W_SHIFT)
#define GPIO_H_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5W_SHIFT)
#define GPIO_H_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4W_SHIFT)
#define GPIO_H_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3W_SHIFT)
#define GPIO_H_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2W_SHIFT)
#define GPIO_H_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1W_SHIFT)
#define GPIO_H_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0W_SHIFT)
#define GPIO_H_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7R_SHIFT)
#define GPIO_H_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6R_SHIFT)
#define GPIO_H_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5R_SHIFT)
#define GPIO_H_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4R_SHIFT)
#define GPIO_H_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3R_SHIFT)
#define GPIO_H_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2R_SHIFT)
#define GPIO_H_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1R_SHIFT)
#define GPIO_H_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_H_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0R_SHIFT)
#define GPIO_H_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 4152 [0x1038]

// Reserved address 4156 [0x103c]

// Register GPIO_L_VM_00_0
#define GPIO_L_VM_00_0                  _MK_ADDR_CONST(0x1040)
#define GPIO_L_VM_00_0_SECURE                   0x0
#define GPIO_L_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_00_0_WORD_COUNT                       0x1
#define GPIO_L_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM1_SHIFT)
#define GPIO_L_VM_00_0_VM1_RANGE                        1:0
#define GPIO_L_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM2_SHIFT)
#define GPIO_L_VM_00_0_VM2_RANGE                        3:2
#define GPIO_L_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM3_SHIFT)
#define GPIO_L_VM_00_0_VM3_RANGE                        5:4
#define GPIO_L_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM4_SHIFT)
#define GPIO_L_VM_00_0_VM4_RANGE                        7:6
#define GPIO_L_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM5_SHIFT)
#define GPIO_L_VM_00_0_VM5_RANGE                        9:8
#define GPIO_L_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM6_SHIFT)
#define GPIO_L_VM_00_0_VM6_RANGE                        11:10
#define GPIO_L_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM7_SHIFT)
#define GPIO_L_VM_00_0_VM7_RANGE                        13:12
#define GPIO_L_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM8_SHIFT)
#define GPIO_L_VM_00_0_VM8_RANGE                        15:14
#define GPIO_L_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_00_0
#define GPIO_L_SCR_00_0                 _MK_ADDR_CONST(0x1044)
#define GPIO_L_SCR_00_0_SECURE                  0x0
#define GPIO_L_SCR_00_0_SCR                     0
#define GPIO_L_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR7_SHIFT)
#define GPIO_L_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR6_SHIFT)
#define GPIO_L_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR5_SHIFT)
#define GPIO_L_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR4_SHIFT)
#define GPIO_L_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR3_SHIFT)
#define GPIO_L_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR2_SHIFT)
#define GPIO_L_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR1_SHIFT)
#define GPIO_L_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR0_SHIFT)
#define GPIO_L_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7W_SHIFT)
#define GPIO_L_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6W_SHIFT)
#define GPIO_L_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5W_SHIFT)
#define GPIO_L_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4W_SHIFT)
#define GPIO_L_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3W_SHIFT)
#define GPIO_L_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2W_SHIFT)
#define GPIO_L_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1W_SHIFT)
#define GPIO_L_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0W_SHIFT)
#define GPIO_L_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7R_SHIFT)
#define GPIO_L_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6R_SHIFT)
#define GPIO_L_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5R_SHIFT)
#define GPIO_L_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4R_SHIFT)
#define GPIO_L_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3R_SHIFT)
#define GPIO_L_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2R_SHIFT)
#define GPIO_L_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1R_SHIFT)
#define GPIO_L_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0R_SHIFT)
#define GPIO_L_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_01_0
#define GPIO_L_VM_01_0                  _MK_ADDR_CONST(0x1048)
#define GPIO_L_VM_01_0_SECURE                   0x0
#define GPIO_L_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_01_0_WORD_COUNT                       0x1
#define GPIO_L_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM1_SHIFT)
#define GPIO_L_VM_01_0_VM1_RANGE                        1:0
#define GPIO_L_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM2_SHIFT)
#define GPIO_L_VM_01_0_VM2_RANGE                        3:2
#define GPIO_L_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM3_SHIFT)
#define GPIO_L_VM_01_0_VM3_RANGE                        5:4
#define GPIO_L_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM4_SHIFT)
#define GPIO_L_VM_01_0_VM4_RANGE                        7:6
#define GPIO_L_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM5_SHIFT)
#define GPIO_L_VM_01_0_VM5_RANGE                        9:8
#define GPIO_L_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM6_SHIFT)
#define GPIO_L_VM_01_0_VM6_RANGE                        11:10
#define GPIO_L_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM7_SHIFT)
#define GPIO_L_VM_01_0_VM7_RANGE                        13:12
#define GPIO_L_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM8_SHIFT)
#define GPIO_L_VM_01_0_VM8_RANGE                        15:14
#define GPIO_L_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_01_0
#define GPIO_L_SCR_01_0                 _MK_ADDR_CONST(0x104c)
#define GPIO_L_SCR_01_0_SECURE                  0x0
#define GPIO_L_SCR_01_0_SCR                     0
#define GPIO_L_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR7_SHIFT)
#define GPIO_L_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR6_SHIFT)
#define GPIO_L_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR5_SHIFT)
#define GPIO_L_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR4_SHIFT)
#define GPIO_L_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR3_SHIFT)
#define GPIO_L_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR2_SHIFT)
#define GPIO_L_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR1_SHIFT)
#define GPIO_L_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR0_SHIFT)
#define GPIO_L_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7W_SHIFT)
#define GPIO_L_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6W_SHIFT)
#define GPIO_L_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5W_SHIFT)
#define GPIO_L_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4W_SHIFT)
#define GPIO_L_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3W_SHIFT)
#define GPIO_L_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2W_SHIFT)
#define GPIO_L_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1W_SHIFT)
#define GPIO_L_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0W_SHIFT)
#define GPIO_L_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7R_SHIFT)
#define GPIO_L_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6R_SHIFT)
#define GPIO_L_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5R_SHIFT)
#define GPIO_L_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4R_SHIFT)
#define GPIO_L_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3R_SHIFT)
#define GPIO_L_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2R_SHIFT)
#define GPIO_L_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1R_SHIFT)
#define GPIO_L_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0R_SHIFT)
#define GPIO_L_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_02_0
#define GPIO_L_VM_02_0                  _MK_ADDR_CONST(0x1050)
#define GPIO_L_VM_02_0_SECURE                   0x0
#define GPIO_L_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_02_0_WORD_COUNT                       0x1
#define GPIO_L_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM1_SHIFT)
#define GPIO_L_VM_02_0_VM1_RANGE                        1:0
#define GPIO_L_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM2_SHIFT)
#define GPIO_L_VM_02_0_VM2_RANGE                        3:2
#define GPIO_L_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM3_SHIFT)
#define GPIO_L_VM_02_0_VM3_RANGE                        5:4
#define GPIO_L_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM4_SHIFT)
#define GPIO_L_VM_02_0_VM4_RANGE                        7:6
#define GPIO_L_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM5_SHIFT)
#define GPIO_L_VM_02_0_VM5_RANGE                        9:8
#define GPIO_L_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM6_SHIFT)
#define GPIO_L_VM_02_0_VM6_RANGE                        11:10
#define GPIO_L_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM7_SHIFT)
#define GPIO_L_VM_02_0_VM7_RANGE                        13:12
#define GPIO_L_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM8_SHIFT)
#define GPIO_L_VM_02_0_VM8_RANGE                        15:14
#define GPIO_L_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_02_0
#define GPIO_L_SCR_02_0                 _MK_ADDR_CONST(0x1054)
#define GPIO_L_SCR_02_0_SECURE                  0x0
#define GPIO_L_SCR_02_0_SCR                     0
#define GPIO_L_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR7_SHIFT)
#define GPIO_L_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR6_SHIFT)
#define GPIO_L_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR5_SHIFT)
#define GPIO_L_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR4_SHIFT)
#define GPIO_L_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR3_SHIFT)
#define GPIO_L_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR2_SHIFT)
#define GPIO_L_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR1_SHIFT)
#define GPIO_L_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR0_SHIFT)
#define GPIO_L_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7W_SHIFT)
#define GPIO_L_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6W_SHIFT)
#define GPIO_L_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5W_SHIFT)
#define GPIO_L_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4W_SHIFT)
#define GPIO_L_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3W_SHIFT)
#define GPIO_L_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2W_SHIFT)
#define GPIO_L_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1W_SHIFT)
#define GPIO_L_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0W_SHIFT)
#define GPIO_L_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7R_SHIFT)
#define GPIO_L_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6R_SHIFT)
#define GPIO_L_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5R_SHIFT)
#define GPIO_L_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4R_SHIFT)
#define GPIO_L_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3R_SHIFT)
#define GPIO_L_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2R_SHIFT)
#define GPIO_L_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1R_SHIFT)
#define GPIO_L_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0R_SHIFT)
#define GPIO_L_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_03_0
#define GPIO_L_VM_03_0                  _MK_ADDR_CONST(0x1058)
#define GPIO_L_VM_03_0_SECURE                   0x0
#define GPIO_L_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_03_0_WORD_COUNT                       0x1
#define GPIO_L_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM1_SHIFT)
#define GPIO_L_VM_03_0_VM1_RANGE                        1:0
#define GPIO_L_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM2_SHIFT)
#define GPIO_L_VM_03_0_VM2_RANGE                        3:2
#define GPIO_L_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM3_SHIFT)
#define GPIO_L_VM_03_0_VM3_RANGE                        5:4
#define GPIO_L_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM4_SHIFT)
#define GPIO_L_VM_03_0_VM4_RANGE                        7:6
#define GPIO_L_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM5_SHIFT)
#define GPIO_L_VM_03_0_VM5_RANGE                        9:8
#define GPIO_L_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM6_SHIFT)
#define GPIO_L_VM_03_0_VM6_RANGE                        11:10
#define GPIO_L_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM7_SHIFT)
#define GPIO_L_VM_03_0_VM7_RANGE                        13:12
#define GPIO_L_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM8_SHIFT)
#define GPIO_L_VM_03_0_VM8_RANGE                        15:14
#define GPIO_L_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_03_0
#define GPIO_L_SCR_03_0                 _MK_ADDR_CONST(0x105c)
#define GPIO_L_SCR_03_0_SECURE                  0x0
#define GPIO_L_SCR_03_0_SCR                     0
#define GPIO_L_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR7_SHIFT)
#define GPIO_L_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR6_SHIFT)
#define GPIO_L_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR5_SHIFT)
#define GPIO_L_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR4_SHIFT)
#define GPIO_L_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR3_SHIFT)
#define GPIO_L_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR2_SHIFT)
#define GPIO_L_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR1_SHIFT)
#define GPIO_L_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR0_SHIFT)
#define GPIO_L_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7W_SHIFT)
#define GPIO_L_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6W_SHIFT)
#define GPIO_L_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5W_SHIFT)
#define GPIO_L_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4W_SHIFT)
#define GPIO_L_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3W_SHIFT)
#define GPIO_L_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2W_SHIFT)
#define GPIO_L_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1W_SHIFT)
#define GPIO_L_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0W_SHIFT)
#define GPIO_L_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7R_SHIFT)
#define GPIO_L_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6R_SHIFT)
#define GPIO_L_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5R_SHIFT)
#define GPIO_L_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4R_SHIFT)
#define GPIO_L_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3R_SHIFT)
#define GPIO_L_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2R_SHIFT)
#define GPIO_L_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1R_SHIFT)
#define GPIO_L_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0R_SHIFT)
#define GPIO_L_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_04_0
#define GPIO_L_VM_04_0                  _MK_ADDR_CONST(0x1060)
#define GPIO_L_VM_04_0_SECURE                   0x0
#define GPIO_L_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_04_0_WORD_COUNT                       0x1
#define GPIO_L_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM1_SHIFT)
#define GPIO_L_VM_04_0_VM1_RANGE                        1:0
#define GPIO_L_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM2_SHIFT)
#define GPIO_L_VM_04_0_VM2_RANGE                        3:2
#define GPIO_L_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM3_SHIFT)
#define GPIO_L_VM_04_0_VM3_RANGE                        5:4
#define GPIO_L_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM4_SHIFT)
#define GPIO_L_VM_04_0_VM4_RANGE                        7:6
#define GPIO_L_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM5_SHIFT)
#define GPIO_L_VM_04_0_VM5_RANGE                        9:8
#define GPIO_L_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM6_SHIFT)
#define GPIO_L_VM_04_0_VM6_RANGE                        11:10
#define GPIO_L_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM7_SHIFT)
#define GPIO_L_VM_04_0_VM7_RANGE                        13:12
#define GPIO_L_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_04_0_VM8_SHIFT)
#define GPIO_L_VM_04_0_VM8_RANGE                        15:14
#define GPIO_L_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_04_0
#define GPIO_L_SCR_04_0                 _MK_ADDR_CONST(0x1064)
#define GPIO_L_SCR_04_0_SECURE                  0x0
#define GPIO_L_SCR_04_0_SCR                     0
#define GPIO_L_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR7_SHIFT)
#define GPIO_L_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR6_SHIFT)
#define GPIO_L_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR5_SHIFT)
#define GPIO_L_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR4_SHIFT)
#define GPIO_L_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR3_SHIFT)
#define GPIO_L_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR2_SHIFT)
#define GPIO_L_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR1_SHIFT)
#define GPIO_L_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_PR0_SHIFT)
#define GPIO_L_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G7W_SHIFT)
#define GPIO_L_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G6W_SHIFT)
#define GPIO_L_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G5W_SHIFT)
#define GPIO_L_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G4W_SHIFT)
#define GPIO_L_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G3W_SHIFT)
#define GPIO_L_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G2W_SHIFT)
#define GPIO_L_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G1W_SHIFT)
#define GPIO_L_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G0W_SHIFT)
#define GPIO_L_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G7R_SHIFT)
#define GPIO_L_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G6R_SHIFT)
#define GPIO_L_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G5R_SHIFT)
#define GPIO_L_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G4R_SHIFT)
#define GPIO_L_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G3R_SHIFT)
#define GPIO_L_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G2R_SHIFT)
#define GPIO_L_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G1R_SHIFT)
#define GPIO_L_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_04_0_G0R_SHIFT)
#define GPIO_L_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_05_0
#define GPIO_L_VM_05_0                  _MK_ADDR_CONST(0x1068)
#define GPIO_L_VM_05_0_SECURE                   0x0
#define GPIO_L_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_05_0_WORD_COUNT                       0x1
#define GPIO_L_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM1_SHIFT)
#define GPIO_L_VM_05_0_VM1_RANGE                        1:0
#define GPIO_L_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM2_SHIFT)
#define GPIO_L_VM_05_0_VM2_RANGE                        3:2
#define GPIO_L_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM3_SHIFT)
#define GPIO_L_VM_05_0_VM3_RANGE                        5:4
#define GPIO_L_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM4_SHIFT)
#define GPIO_L_VM_05_0_VM4_RANGE                        7:6
#define GPIO_L_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM5_SHIFT)
#define GPIO_L_VM_05_0_VM5_RANGE                        9:8
#define GPIO_L_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM6_SHIFT)
#define GPIO_L_VM_05_0_VM6_RANGE                        11:10
#define GPIO_L_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM7_SHIFT)
#define GPIO_L_VM_05_0_VM7_RANGE                        13:12
#define GPIO_L_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_05_0_VM8_SHIFT)
#define GPIO_L_VM_05_0_VM8_RANGE                        15:14
#define GPIO_L_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_05_0
#define GPIO_L_SCR_05_0                 _MK_ADDR_CONST(0x106c)
#define GPIO_L_SCR_05_0_SECURE                  0x0
#define GPIO_L_SCR_05_0_SCR                     0
#define GPIO_L_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR7_SHIFT)
#define GPIO_L_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR6_SHIFT)
#define GPIO_L_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR5_SHIFT)
#define GPIO_L_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR4_SHIFT)
#define GPIO_L_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR3_SHIFT)
#define GPIO_L_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR2_SHIFT)
#define GPIO_L_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR1_SHIFT)
#define GPIO_L_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_PR0_SHIFT)
#define GPIO_L_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G7W_SHIFT)
#define GPIO_L_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G6W_SHIFT)
#define GPIO_L_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G5W_SHIFT)
#define GPIO_L_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G4W_SHIFT)
#define GPIO_L_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G3W_SHIFT)
#define GPIO_L_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G2W_SHIFT)
#define GPIO_L_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G1W_SHIFT)
#define GPIO_L_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G0W_SHIFT)
#define GPIO_L_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G7R_SHIFT)
#define GPIO_L_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G6R_SHIFT)
#define GPIO_L_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G5R_SHIFT)
#define GPIO_L_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G4R_SHIFT)
#define GPIO_L_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G3R_SHIFT)
#define GPIO_L_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G2R_SHIFT)
#define GPIO_L_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G1R_SHIFT)
#define GPIO_L_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_05_0_G0R_SHIFT)
#define GPIO_L_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_06_0
#define GPIO_L_VM_06_0                  _MK_ADDR_CONST(0x1070)
#define GPIO_L_VM_06_0_SECURE                   0x0
#define GPIO_L_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_06_0_WORD_COUNT                       0x1
#define GPIO_L_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM1_SHIFT)
#define GPIO_L_VM_06_0_VM1_RANGE                        1:0
#define GPIO_L_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM2_SHIFT)
#define GPIO_L_VM_06_0_VM2_RANGE                        3:2
#define GPIO_L_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM3_SHIFT)
#define GPIO_L_VM_06_0_VM3_RANGE                        5:4
#define GPIO_L_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM4_SHIFT)
#define GPIO_L_VM_06_0_VM4_RANGE                        7:6
#define GPIO_L_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM5_SHIFT)
#define GPIO_L_VM_06_0_VM5_RANGE                        9:8
#define GPIO_L_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM6_SHIFT)
#define GPIO_L_VM_06_0_VM6_RANGE                        11:10
#define GPIO_L_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM7_SHIFT)
#define GPIO_L_VM_06_0_VM7_RANGE                        13:12
#define GPIO_L_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_06_0_VM8_SHIFT)
#define GPIO_L_VM_06_0_VM8_RANGE                        15:14
#define GPIO_L_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_06_0
#define GPIO_L_SCR_06_0                 _MK_ADDR_CONST(0x1074)
#define GPIO_L_SCR_06_0_SECURE                  0x0
#define GPIO_L_SCR_06_0_SCR                     0
#define GPIO_L_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR7_SHIFT)
#define GPIO_L_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR6_SHIFT)
#define GPIO_L_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR5_SHIFT)
#define GPIO_L_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR4_SHIFT)
#define GPIO_L_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR3_SHIFT)
#define GPIO_L_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR2_SHIFT)
#define GPIO_L_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR1_SHIFT)
#define GPIO_L_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_PR0_SHIFT)
#define GPIO_L_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G7W_SHIFT)
#define GPIO_L_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G6W_SHIFT)
#define GPIO_L_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G5W_SHIFT)
#define GPIO_L_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G4W_SHIFT)
#define GPIO_L_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G3W_SHIFT)
#define GPIO_L_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G2W_SHIFT)
#define GPIO_L_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G1W_SHIFT)
#define GPIO_L_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G0W_SHIFT)
#define GPIO_L_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G7R_SHIFT)
#define GPIO_L_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G6R_SHIFT)
#define GPIO_L_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G5R_SHIFT)
#define GPIO_L_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G4R_SHIFT)
#define GPIO_L_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G3R_SHIFT)
#define GPIO_L_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G2R_SHIFT)
#define GPIO_L_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G1R_SHIFT)
#define GPIO_L_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_06_0_G0R_SHIFT)
#define GPIO_L_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_L_VM_07_0
#define GPIO_L_VM_07_0                  _MK_ADDR_CONST(0x1078)
#define GPIO_L_VM_07_0_SECURE                   0x0
#define GPIO_L_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_L_VM_07_0_WORD_COUNT                       0x1
#define GPIO_L_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM1_SHIFT)
#define GPIO_L_VM_07_0_VM1_RANGE                        1:0
#define GPIO_L_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM2_SHIFT)
#define GPIO_L_VM_07_0_VM2_RANGE                        3:2
#define GPIO_L_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM3_SHIFT)
#define GPIO_L_VM_07_0_VM3_RANGE                        5:4
#define GPIO_L_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM4_SHIFT)
#define GPIO_L_VM_07_0_VM4_RANGE                        7:6
#define GPIO_L_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM5_SHIFT)
#define GPIO_L_VM_07_0_VM5_RANGE                        9:8
#define GPIO_L_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM6_SHIFT)
#define GPIO_L_VM_07_0_VM6_RANGE                        11:10
#define GPIO_L_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM7_SHIFT)
#define GPIO_L_VM_07_0_VM7_RANGE                        13:12
#define GPIO_L_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_L_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_07_0_VM8_SHIFT)
#define GPIO_L_VM_07_0_VM8_RANGE                        15:14
#define GPIO_L_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_SCR_07_0
#define GPIO_L_SCR_07_0                 _MK_ADDR_CONST(0x107c)
#define GPIO_L_SCR_07_0_SECURE                  0x0
#define GPIO_L_SCR_07_0_SCR                     0
#define GPIO_L_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR7_SHIFT)
#define GPIO_L_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR6_SHIFT)
#define GPIO_L_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR5_SHIFT)
#define GPIO_L_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR4_SHIFT)
#define GPIO_L_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR3_SHIFT)
#define GPIO_L_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR2_SHIFT)
#define GPIO_L_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR1_SHIFT)
#define GPIO_L_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_PR0_SHIFT)
#define GPIO_L_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G7W_SHIFT)
#define GPIO_L_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G6W_SHIFT)
#define GPIO_L_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G5W_SHIFT)
#define GPIO_L_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G4W_SHIFT)
#define GPIO_L_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G3W_SHIFT)
#define GPIO_L_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G2W_SHIFT)
#define GPIO_L_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G1W_SHIFT)
#define GPIO_L_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G0W_SHIFT)
#define GPIO_L_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G7R_SHIFT)
#define GPIO_L_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G6R_SHIFT)
#define GPIO_L_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G5R_SHIFT)
#define GPIO_L_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G4R_SHIFT)
#define GPIO_L_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G3R_SHIFT)
#define GPIO_L_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G2R_SHIFT)
#define GPIO_L_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G1R_SHIFT)
#define GPIO_L_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_L_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_07_0_G0R_SHIFT)
#define GPIO_L_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_00_0
#define GPIO_X_VM_00_0                  _MK_ADDR_CONST(0x1080)
#define GPIO_X_VM_00_0_SECURE                   0x0
#define GPIO_X_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_00_0_WORD_COUNT                       0x1
#define GPIO_X_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM1_SHIFT)
#define GPIO_X_VM_00_0_VM1_RANGE                        1:0
#define GPIO_X_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM2_SHIFT)
#define GPIO_X_VM_00_0_VM2_RANGE                        3:2
#define GPIO_X_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM3_SHIFT)
#define GPIO_X_VM_00_0_VM3_RANGE                        5:4
#define GPIO_X_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM4_SHIFT)
#define GPIO_X_VM_00_0_VM4_RANGE                        7:6
#define GPIO_X_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM5_SHIFT)
#define GPIO_X_VM_00_0_VM5_RANGE                        9:8
#define GPIO_X_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM6_SHIFT)
#define GPIO_X_VM_00_0_VM6_RANGE                        11:10
#define GPIO_X_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM7_SHIFT)
#define GPIO_X_VM_00_0_VM7_RANGE                        13:12
#define GPIO_X_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM8_SHIFT)
#define GPIO_X_VM_00_0_VM8_RANGE                        15:14
#define GPIO_X_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_00_0
#define GPIO_X_SCR_00_0                 _MK_ADDR_CONST(0x1084)
#define GPIO_X_SCR_00_0_SECURE                  0x0
#define GPIO_X_SCR_00_0_SCR                     0
#define GPIO_X_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR7_SHIFT)
#define GPIO_X_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR6_SHIFT)
#define GPIO_X_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR5_SHIFT)
#define GPIO_X_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR4_SHIFT)
#define GPIO_X_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR3_SHIFT)
#define GPIO_X_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR2_SHIFT)
#define GPIO_X_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR1_SHIFT)
#define GPIO_X_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR0_SHIFT)
#define GPIO_X_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7W_SHIFT)
#define GPIO_X_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6W_SHIFT)
#define GPIO_X_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5W_SHIFT)
#define GPIO_X_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4W_SHIFT)
#define GPIO_X_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3W_SHIFT)
#define GPIO_X_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2W_SHIFT)
#define GPIO_X_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1W_SHIFT)
#define GPIO_X_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0W_SHIFT)
#define GPIO_X_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7R_SHIFT)
#define GPIO_X_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6R_SHIFT)
#define GPIO_X_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5R_SHIFT)
#define GPIO_X_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4R_SHIFT)
#define GPIO_X_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3R_SHIFT)
#define GPIO_X_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2R_SHIFT)
#define GPIO_X_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1R_SHIFT)
#define GPIO_X_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0R_SHIFT)
#define GPIO_X_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_01_0
#define GPIO_X_VM_01_0                  _MK_ADDR_CONST(0x1088)
#define GPIO_X_VM_01_0_SECURE                   0x0
#define GPIO_X_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_01_0_WORD_COUNT                       0x1
#define GPIO_X_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM1_SHIFT)
#define GPIO_X_VM_01_0_VM1_RANGE                        1:0
#define GPIO_X_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM2_SHIFT)
#define GPIO_X_VM_01_0_VM2_RANGE                        3:2
#define GPIO_X_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM3_SHIFT)
#define GPIO_X_VM_01_0_VM3_RANGE                        5:4
#define GPIO_X_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM4_SHIFT)
#define GPIO_X_VM_01_0_VM4_RANGE                        7:6
#define GPIO_X_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM5_SHIFT)
#define GPIO_X_VM_01_0_VM5_RANGE                        9:8
#define GPIO_X_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM6_SHIFT)
#define GPIO_X_VM_01_0_VM6_RANGE                        11:10
#define GPIO_X_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM7_SHIFT)
#define GPIO_X_VM_01_0_VM7_RANGE                        13:12
#define GPIO_X_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM8_SHIFT)
#define GPIO_X_VM_01_0_VM8_RANGE                        15:14
#define GPIO_X_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_01_0
#define GPIO_X_SCR_01_0                 _MK_ADDR_CONST(0x108c)
#define GPIO_X_SCR_01_0_SECURE                  0x0
#define GPIO_X_SCR_01_0_SCR                     0
#define GPIO_X_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR7_SHIFT)
#define GPIO_X_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR6_SHIFT)
#define GPIO_X_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR5_SHIFT)
#define GPIO_X_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR4_SHIFT)
#define GPIO_X_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR3_SHIFT)
#define GPIO_X_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR2_SHIFT)
#define GPIO_X_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR1_SHIFT)
#define GPIO_X_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR0_SHIFT)
#define GPIO_X_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7W_SHIFT)
#define GPIO_X_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6W_SHIFT)
#define GPIO_X_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5W_SHIFT)
#define GPIO_X_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4W_SHIFT)
#define GPIO_X_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3W_SHIFT)
#define GPIO_X_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2W_SHIFT)
#define GPIO_X_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1W_SHIFT)
#define GPIO_X_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0W_SHIFT)
#define GPIO_X_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7R_SHIFT)
#define GPIO_X_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6R_SHIFT)
#define GPIO_X_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5R_SHIFT)
#define GPIO_X_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4R_SHIFT)
#define GPIO_X_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3R_SHIFT)
#define GPIO_X_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2R_SHIFT)
#define GPIO_X_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1R_SHIFT)
#define GPIO_X_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0R_SHIFT)
#define GPIO_X_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_02_0
#define GPIO_X_VM_02_0                  _MK_ADDR_CONST(0x1090)
#define GPIO_X_VM_02_0_SECURE                   0x0
#define GPIO_X_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_02_0_WORD_COUNT                       0x1
#define GPIO_X_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM1_SHIFT)
#define GPIO_X_VM_02_0_VM1_RANGE                        1:0
#define GPIO_X_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM2_SHIFT)
#define GPIO_X_VM_02_0_VM2_RANGE                        3:2
#define GPIO_X_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM3_SHIFT)
#define GPIO_X_VM_02_0_VM3_RANGE                        5:4
#define GPIO_X_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM4_SHIFT)
#define GPIO_X_VM_02_0_VM4_RANGE                        7:6
#define GPIO_X_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM5_SHIFT)
#define GPIO_X_VM_02_0_VM5_RANGE                        9:8
#define GPIO_X_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM6_SHIFT)
#define GPIO_X_VM_02_0_VM6_RANGE                        11:10
#define GPIO_X_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM7_SHIFT)
#define GPIO_X_VM_02_0_VM7_RANGE                        13:12
#define GPIO_X_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM8_SHIFT)
#define GPIO_X_VM_02_0_VM8_RANGE                        15:14
#define GPIO_X_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_02_0
#define GPIO_X_SCR_02_0                 _MK_ADDR_CONST(0x1094)
#define GPIO_X_SCR_02_0_SECURE                  0x0
#define GPIO_X_SCR_02_0_SCR                     0
#define GPIO_X_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR7_SHIFT)
#define GPIO_X_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR6_SHIFT)
#define GPIO_X_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR5_SHIFT)
#define GPIO_X_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR4_SHIFT)
#define GPIO_X_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR3_SHIFT)
#define GPIO_X_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR2_SHIFT)
#define GPIO_X_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR1_SHIFT)
#define GPIO_X_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR0_SHIFT)
#define GPIO_X_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7W_SHIFT)
#define GPIO_X_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6W_SHIFT)
#define GPIO_X_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5W_SHIFT)
#define GPIO_X_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4W_SHIFT)
#define GPIO_X_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3W_SHIFT)
#define GPIO_X_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2W_SHIFT)
#define GPIO_X_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1W_SHIFT)
#define GPIO_X_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0W_SHIFT)
#define GPIO_X_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7R_SHIFT)
#define GPIO_X_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6R_SHIFT)
#define GPIO_X_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5R_SHIFT)
#define GPIO_X_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4R_SHIFT)
#define GPIO_X_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3R_SHIFT)
#define GPIO_X_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2R_SHIFT)
#define GPIO_X_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1R_SHIFT)
#define GPIO_X_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0R_SHIFT)
#define GPIO_X_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_03_0
#define GPIO_X_VM_03_0                  _MK_ADDR_CONST(0x1098)
#define GPIO_X_VM_03_0_SECURE                   0x0
#define GPIO_X_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_03_0_WORD_COUNT                       0x1
#define GPIO_X_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM1_SHIFT)
#define GPIO_X_VM_03_0_VM1_RANGE                        1:0
#define GPIO_X_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM2_SHIFT)
#define GPIO_X_VM_03_0_VM2_RANGE                        3:2
#define GPIO_X_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM3_SHIFT)
#define GPIO_X_VM_03_0_VM3_RANGE                        5:4
#define GPIO_X_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM4_SHIFT)
#define GPIO_X_VM_03_0_VM4_RANGE                        7:6
#define GPIO_X_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM5_SHIFT)
#define GPIO_X_VM_03_0_VM5_RANGE                        9:8
#define GPIO_X_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM6_SHIFT)
#define GPIO_X_VM_03_0_VM6_RANGE                        11:10
#define GPIO_X_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM7_SHIFT)
#define GPIO_X_VM_03_0_VM7_RANGE                        13:12
#define GPIO_X_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM8_SHIFT)
#define GPIO_X_VM_03_0_VM8_RANGE                        15:14
#define GPIO_X_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_03_0
#define GPIO_X_SCR_03_0                 _MK_ADDR_CONST(0x109c)
#define GPIO_X_SCR_03_0_SECURE                  0x0
#define GPIO_X_SCR_03_0_SCR                     0
#define GPIO_X_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR7_SHIFT)
#define GPIO_X_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR6_SHIFT)
#define GPIO_X_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR5_SHIFT)
#define GPIO_X_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR4_SHIFT)
#define GPIO_X_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR3_SHIFT)
#define GPIO_X_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR2_SHIFT)
#define GPIO_X_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR1_SHIFT)
#define GPIO_X_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR0_SHIFT)
#define GPIO_X_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7W_SHIFT)
#define GPIO_X_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6W_SHIFT)
#define GPIO_X_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5W_SHIFT)
#define GPIO_X_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4W_SHIFT)
#define GPIO_X_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3W_SHIFT)
#define GPIO_X_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2W_SHIFT)
#define GPIO_X_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1W_SHIFT)
#define GPIO_X_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0W_SHIFT)
#define GPIO_X_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7R_SHIFT)
#define GPIO_X_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6R_SHIFT)
#define GPIO_X_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5R_SHIFT)
#define GPIO_X_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4R_SHIFT)
#define GPIO_X_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3R_SHIFT)
#define GPIO_X_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2R_SHIFT)
#define GPIO_X_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1R_SHIFT)
#define GPIO_X_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0R_SHIFT)
#define GPIO_X_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_04_0
#define GPIO_X_VM_04_0                  _MK_ADDR_CONST(0x10a0)
#define GPIO_X_VM_04_0_SECURE                   0x0
#define GPIO_X_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_04_0_WORD_COUNT                       0x1
#define GPIO_X_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM1_SHIFT)
#define GPIO_X_VM_04_0_VM1_RANGE                        1:0
#define GPIO_X_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM2_SHIFT)
#define GPIO_X_VM_04_0_VM2_RANGE                        3:2
#define GPIO_X_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM3_SHIFT)
#define GPIO_X_VM_04_0_VM3_RANGE                        5:4
#define GPIO_X_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM4_SHIFT)
#define GPIO_X_VM_04_0_VM4_RANGE                        7:6
#define GPIO_X_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM5_SHIFT)
#define GPIO_X_VM_04_0_VM5_RANGE                        9:8
#define GPIO_X_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM6_SHIFT)
#define GPIO_X_VM_04_0_VM6_RANGE                        11:10
#define GPIO_X_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM7_SHIFT)
#define GPIO_X_VM_04_0_VM7_RANGE                        13:12
#define GPIO_X_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM8_SHIFT)
#define GPIO_X_VM_04_0_VM8_RANGE                        15:14
#define GPIO_X_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_04_0
#define GPIO_X_SCR_04_0                 _MK_ADDR_CONST(0x10a4)
#define GPIO_X_SCR_04_0_SECURE                  0x0
#define GPIO_X_SCR_04_0_SCR                     0
#define GPIO_X_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR7_SHIFT)
#define GPIO_X_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR6_SHIFT)
#define GPIO_X_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR5_SHIFT)
#define GPIO_X_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR4_SHIFT)
#define GPIO_X_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR3_SHIFT)
#define GPIO_X_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR2_SHIFT)
#define GPIO_X_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR1_SHIFT)
#define GPIO_X_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR0_SHIFT)
#define GPIO_X_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7W_SHIFT)
#define GPIO_X_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6W_SHIFT)
#define GPIO_X_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5W_SHIFT)
#define GPIO_X_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4W_SHIFT)
#define GPIO_X_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3W_SHIFT)
#define GPIO_X_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2W_SHIFT)
#define GPIO_X_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1W_SHIFT)
#define GPIO_X_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0W_SHIFT)
#define GPIO_X_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7R_SHIFT)
#define GPIO_X_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6R_SHIFT)
#define GPIO_X_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5R_SHIFT)
#define GPIO_X_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4R_SHIFT)
#define GPIO_X_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3R_SHIFT)
#define GPIO_X_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2R_SHIFT)
#define GPIO_X_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1R_SHIFT)
#define GPIO_X_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0R_SHIFT)
#define GPIO_X_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_05_0
#define GPIO_X_VM_05_0                  _MK_ADDR_CONST(0x10a8)
#define GPIO_X_VM_05_0_SECURE                   0x0
#define GPIO_X_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_05_0_WORD_COUNT                       0x1
#define GPIO_X_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM1_SHIFT)
#define GPIO_X_VM_05_0_VM1_RANGE                        1:0
#define GPIO_X_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM2_SHIFT)
#define GPIO_X_VM_05_0_VM2_RANGE                        3:2
#define GPIO_X_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM3_SHIFT)
#define GPIO_X_VM_05_0_VM3_RANGE                        5:4
#define GPIO_X_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM4_SHIFT)
#define GPIO_X_VM_05_0_VM4_RANGE                        7:6
#define GPIO_X_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM5_SHIFT)
#define GPIO_X_VM_05_0_VM5_RANGE                        9:8
#define GPIO_X_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM6_SHIFT)
#define GPIO_X_VM_05_0_VM6_RANGE                        11:10
#define GPIO_X_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM7_SHIFT)
#define GPIO_X_VM_05_0_VM7_RANGE                        13:12
#define GPIO_X_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM8_SHIFT)
#define GPIO_X_VM_05_0_VM8_RANGE                        15:14
#define GPIO_X_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_05_0
#define GPIO_X_SCR_05_0                 _MK_ADDR_CONST(0x10ac)
#define GPIO_X_SCR_05_0_SECURE                  0x0
#define GPIO_X_SCR_05_0_SCR                     0
#define GPIO_X_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR7_SHIFT)
#define GPIO_X_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR6_SHIFT)
#define GPIO_X_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR5_SHIFT)
#define GPIO_X_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR4_SHIFT)
#define GPIO_X_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR3_SHIFT)
#define GPIO_X_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR2_SHIFT)
#define GPIO_X_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR1_SHIFT)
#define GPIO_X_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR0_SHIFT)
#define GPIO_X_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7W_SHIFT)
#define GPIO_X_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6W_SHIFT)
#define GPIO_X_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5W_SHIFT)
#define GPIO_X_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4W_SHIFT)
#define GPIO_X_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3W_SHIFT)
#define GPIO_X_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2W_SHIFT)
#define GPIO_X_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1W_SHIFT)
#define GPIO_X_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0W_SHIFT)
#define GPIO_X_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7R_SHIFT)
#define GPIO_X_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6R_SHIFT)
#define GPIO_X_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5R_SHIFT)
#define GPIO_X_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4R_SHIFT)
#define GPIO_X_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3R_SHIFT)
#define GPIO_X_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2R_SHIFT)
#define GPIO_X_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1R_SHIFT)
#define GPIO_X_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0R_SHIFT)
#define GPIO_X_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_06_0
#define GPIO_X_VM_06_0                  _MK_ADDR_CONST(0x10b0)
#define GPIO_X_VM_06_0_SECURE                   0x0
#define GPIO_X_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_06_0_WORD_COUNT                       0x1
#define GPIO_X_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM1_SHIFT)
#define GPIO_X_VM_06_0_VM1_RANGE                        1:0
#define GPIO_X_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM2_SHIFT)
#define GPIO_X_VM_06_0_VM2_RANGE                        3:2
#define GPIO_X_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM3_SHIFT)
#define GPIO_X_VM_06_0_VM3_RANGE                        5:4
#define GPIO_X_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM4_SHIFT)
#define GPIO_X_VM_06_0_VM4_RANGE                        7:6
#define GPIO_X_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM5_SHIFT)
#define GPIO_X_VM_06_0_VM5_RANGE                        9:8
#define GPIO_X_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM6_SHIFT)
#define GPIO_X_VM_06_0_VM6_RANGE                        11:10
#define GPIO_X_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM7_SHIFT)
#define GPIO_X_VM_06_0_VM7_RANGE                        13:12
#define GPIO_X_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM8_SHIFT)
#define GPIO_X_VM_06_0_VM8_RANGE                        15:14
#define GPIO_X_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_06_0
#define GPIO_X_SCR_06_0                 _MK_ADDR_CONST(0x10b4)
#define GPIO_X_SCR_06_0_SECURE                  0x0
#define GPIO_X_SCR_06_0_SCR                     0
#define GPIO_X_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR7_SHIFT)
#define GPIO_X_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR6_SHIFT)
#define GPIO_X_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR5_SHIFT)
#define GPIO_X_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR4_SHIFT)
#define GPIO_X_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR3_SHIFT)
#define GPIO_X_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR2_SHIFT)
#define GPIO_X_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR1_SHIFT)
#define GPIO_X_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR0_SHIFT)
#define GPIO_X_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7W_SHIFT)
#define GPIO_X_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6W_SHIFT)
#define GPIO_X_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5W_SHIFT)
#define GPIO_X_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4W_SHIFT)
#define GPIO_X_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3W_SHIFT)
#define GPIO_X_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2W_SHIFT)
#define GPIO_X_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1W_SHIFT)
#define GPIO_X_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0W_SHIFT)
#define GPIO_X_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7R_SHIFT)
#define GPIO_X_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6R_SHIFT)
#define GPIO_X_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5R_SHIFT)
#define GPIO_X_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4R_SHIFT)
#define GPIO_X_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3R_SHIFT)
#define GPIO_X_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2R_SHIFT)
#define GPIO_X_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1R_SHIFT)
#define GPIO_X_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0R_SHIFT)
#define GPIO_X_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_X_VM_07_0
#define GPIO_X_VM_07_0                  _MK_ADDR_CONST(0x10b8)
#define GPIO_X_VM_07_0_SECURE                   0x0
#define GPIO_X_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_07_0_WORD_COUNT                       0x1
#define GPIO_X_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM1_SHIFT)
#define GPIO_X_VM_07_0_VM1_RANGE                        1:0
#define GPIO_X_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM2_SHIFT)
#define GPIO_X_VM_07_0_VM2_RANGE                        3:2
#define GPIO_X_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM3_SHIFT)
#define GPIO_X_VM_07_0_VM3_RANGE                        5:4
#define GPIO_X_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM4_SHIFT)
#define GPIO_X_VM_07_0_VM4_RANGE                        7:6
#define GPIO_X_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM5_SHIFT)
#define GPIO_X_VM_07_0_VM5_RANGE                        9:8
#define GPIO_X_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM6_SHIFT)
#define GPIO_X_VM_07_0_VM6_RANGE                        11:10
#define GPIO_X_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM7_SHIFT)
#define GPIO_X_VM_07_0_VM7_RANGE                        13:12
#define GPIO_X_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_X_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM8_SHIFT)
#define GPIO_X_VM_07_0_VM8_RANGE                        15:14
#define GPIO_X_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_SCR_07_0
#define GPIO_X_SCR_07_0                 _MK_ADDR_CONST(0x10bc)
#define GPIO_X_SCR_07_0_SECURE                  0x0
#define GPIO_X_SCR_07_0_SCR                     0
#define GPIO_X_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR7_SHIFT)
#define GPIO_X_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR6_SHIFT)
#define GPIO_X_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR5_SHIFT)
#define GPIO_X_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR4_SHIFT)
#define GPIO_X_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR3_SHIFT)
#define GPIO_X_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR2_SHIFT)
#define GPIO_X_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR1_SHIFT)
#define GPIO_X_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR0_SHIFT)
#define GPIO_X_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7W_SHIFT)
#define GPIO_X_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6W_SHIFT)
#define GPIO_X_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5W_SHIFT)
#define GPIO_X_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4W_SHIFT)
#define GPIO_X_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3W_SHIFT)
#define GPIO_X_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2W_SHIFT)
#define GPIO_X_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1W_SHIFT)
#define GPIO_X_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0W_SHIFT)
#define GPIO_X_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7R_SHIFT)
#define GPIO_X_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6R_SHIFT)
#define GPIO_X_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5R_SHIFT)
#define GPIO_X_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4R_SHIFT)
#define GPIO_X_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3R_SHIFT)
#define GPIO_X_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2R_SHIFT)
#define GPIO_X_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1R_SHIFT)
#define GPIO_X_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_X_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0R_SHIFT)
#define GPIO_X_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_00_0
#define GPIO_Y_VM_00_0                  _MK_ADDR_CONST(0x10c0)
#define GPIO_Y_VM_00_0_SECURE                   0x0
#define GPIO_Y_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM1_SHIFT)
#define GPIO_Y_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM2_SHIFT)
#define GPIO_Y_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM3_SHIFT)
#define GPIO_Y_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM4_SHIFT)
#define GPIO_Y_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM5_SHIFT)
#define GPIO_Y_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM6_SHIFT)
#define GPIO_Y_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM7_SHIFT)
#define GPIO_Y_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM8_SHIFT)
#define GPIO_Y_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_00_0
#define GPIO_Y_SCR_00_0                 _MK_ADDR_CONST(0x10c4)
#define GPIO_Y_SCR_00_0_SECURE                  0x0
#define GPIO_Y_SCR_00_0_SCR                     0
#define GPIO_Y_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR7_SHIFT)
#define GPIO_Y_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR6_SHIFT)
#define GPIO_Y_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR5_SHIFT)
#define GPIO_Y_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR4_SHIFT)
#define GPIO_Y_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR3_SHIFT)
#define GPIO_Y_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR2_SHIFT)
#define GPIO_Y_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR1_SHIFT)
#define GPIO_Y_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR0_SHIFT)
#define GPIO_Y_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7W_SHIFT)
#define GPIO_Y_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6W_SHIFT)
#define GPIO_Y_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5W_SHIFT)
#define GPIO_Y_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4W_SHIFT)
#define GPIO_Y_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3W_SHIFT)
#define GPIO_Y_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2W_SHIFT)
#define GPIO_Y_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1W_SHIFT)
#define GPIO_Y_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0W_SHIFT)
#define GPIO_Y_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7R_SHIFT)
#define GPIO_Y_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6R_SHIFT)
#define GPIO_Y_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5R_SHIFT)
#define GPIO_Y_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4R_SHIFT)
#define GPIO_Y_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3R_SHIFT)
#define GPIO_Y_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2R_SHIFT)
#define GPIO_Y_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1R_SHIFT)
#define GPIO_Y_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0R_SHIFT)
#define GPIO_Y_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_01_0
#define GPIO_Y_VM_01_0                  _MK_ADDR_CONST(0x10c8)
#define GPIO_Y_VM_01_0_SECURE                   0x0
#define GPIO_Y_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM1_SHIFT)
#define GPIO_Y_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM2_SHIFT)
#define GPIO_Y_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM3_SHIFT)
#define GPIO_Y_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM4_SHIFT)
#define GPIO_Y_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM5_SHIFT)
#define GPIO_Y_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM6_SHIFT)
#define GPIO_Y_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM7_SHIFT)
#define GPIO_Y_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM8_SHIFT)
#define GPIO_Y_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_01_0
#define GPIO_Y_SCR_01_0                 _MK_ADDR_CONST(0x10cc)
#define GPIO_Y_SCR_01_0_SECURE                  0x0
#define GPIO_Y_SCR_01_0_SCR                     0
#define GPIO_Y_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR7_SHIFT)
#define GPIO_Y_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR6_SHIFT)
#define GPIO_Y_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR5_SHIFT)
#define GPIO_Y_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR4_SHIFT)
#define GPIO_Y_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR3_SHIFT)
#define GPIO_Y_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR2_SHIFT)
#define GPIO_Y_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR1_SHIFT)
#define GPIO_Y_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR0_SHIFT)
#define GPIO_Y_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7W_SHIFT)
#define GPIO_Y_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6W_SHIFT)
#define GPIO_Y_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5W_SHIFT)
#define GPIO_Y_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4W_SHIFT)
#define GPIO_Y_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3W_SHIFT)
#define GPIO_Y_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2W_SHIFT)
#define GPIO_Y_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1W_SHIFT)
#define GPIO_Y_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0W_SHIFT)
#define GPIO_Y_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7R_SHIFT)
#define GPIO_Y_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6R_SHIFT)
#define GPIO_Y_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5R_SHIFT)
#define GPIO_Y_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4R_SHIFT)
#define GPIO_Y_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3R_SHIFT)
#define GPIO_Y_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2R_SHIFT)
#define GPIO_Y_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1R_SHIFT)
#define GPIO_Y_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0R_SHIFT)
#define GPIO_Y_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_02_0
#define GPIO_Y_VM_02_0                  _MK_ADDR_CONST(0x10d0)
#define GPIO_Y_VM_02_0_SECURE                   0x0
#define GPIO_Y_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM1_SHIFT)
#define GPIO_Y_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM2_SHIFT)
#define GPIO_Y_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM3_SHIFT)
#define GPIO_Y_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM4_SHIFT)
#define GPIO_Y_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM5_SHIFT)
#define GPIO_Y_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM6_SHIFT)
#define GPIO_Y_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM7_SHIFT)
#define GPIO_Y_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM8_SHIFT)
#define GPIO_Y_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_02_0
#define GPIO_Y_SCR_02_0                 _MK_ADDR_CONST(0x10d4)
#define GPIO_Y_SCR_02_0_SECURE                  0x0
#define GPIO_Y_SCR_02_0_SCR                     0
#define GPIO_Y_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR7_SHIFT)
#define GPIO_Y_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR6_SHIFT)
#define GPIO_Y_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR5_SHIFT)
#define GPIO_Y_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR4_SHIFT)
#define GPIO_Y_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR3_SHIFT)
#define GPIO_Y_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR2_SHIFT)
#define GPIO_Y_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR1_SHIFT)
#define GPIO_Y_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR0_SHIFT)
#define GPIO_Y_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7W_SHIFT)
#define GPIO_Y_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6W_SHIFT)
#define GPIO_Y_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5W_SHIFT)
#define GPIO_Y_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4W_SHIFT)
#define GPIO_Y_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3W_SHIFT)
#define GPIO_Y_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2W_SHIFT)
#define GPIO_Y_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1W_SHIFT)
#define GPIO_Y_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0W_SHIFT)
#define GPIO_Y_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7R_SHIFT)
#define GPIO_Y_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6R_SHIFT)
#define GPIO_Y_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5R_SHIFT)
#define GPIO_Y_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4R_SHIFT)
#define GPIO_Y_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3R_SHIFT)
#define GPIO_Y_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2R_SHIFT)
#define GPIO_Y_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1R_SHIFT)
#define GPIO_Y_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0R_SHIFT)
#define GPIO_Y_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_03_0
#define GPIO_Y_VM_03_0                  _MK_ADDR_CONST(0x10d8)
#define GPIO_Y_VM_03_0_SECURE                   0x0
#define GPIO_Y_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM1_SHIFT)
#define GPIO_Y_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM2_SHIFT)
#define GPIO_Y_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM3_SHIFT)
#define GPIO_Y_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM4_SHIFT)
#define GPIO_Y_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM5_SHIFT)
#define GPIO_Y_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM6_SHIFT)
#define GPIO_Y_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM7_SHIFT)
#define GPIO_Y_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM8_SHIFT)
#define GPIO_Y_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_03_0
#define GPIO_Y_SCR_03_0                 _MK_ADDR_CONST(0x10dc)
#define GPIO_Y_SCR_03_0_SECURE                  0x0
#define GPIO_Y_SCR_03_0_SCR                     0
#define GPIO_Y_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR7_SHIFT)
#define GPIO_Y_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR6_SHIFT)
#define GPIO_Y_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR5_SHIFT)
#define GPIO_Y_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR4_SHIFT)
#define GPIO_Y_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR3_SHIFT)
#define GPIO_Y_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR2_SHIFT)
#define GPIO_Y_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR1_SHIFT)
#define GPIO_Y_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR0_SHIFT)
#define GPIO_Y_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7W_SHIFT)
#define GPIO_Y_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6W_SHIFT)
#define GPIO_Y_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5W_SHIFT)
#define GPIO_Y_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4W_SHIFT)
#define GPIO_Y_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3W_SHIFT)
#define GPIO_Y_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2W_SHIFT)
#define GPIO_Y_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1W_SHIFT)
#define GPIO_Y_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0W_SHIFT)
#define GPIO_Y_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7R_SHIFT)
#define GPIO_Y_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6R_SHIFT)
#define GPIO_Y_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5R_SHIFT)
#define GPIO_Y_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4R_SHIFT)
#define GPIO_Y_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3R_SHIFT)
#define GPIO_Y_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2R_SHIFT)
#define GPIO_Y_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1R_SHIFT)
#define GPIO_Y_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0R_SHIFT)
#define GPIO_Y_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_04_0
#define GPIO_Y_VM_04_0                  _MK_ADDR_CONST(0x10e0)
#define GPIO_Y_VM_04_0_SECURE                   0x0
#define GPIO_Y_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM1_SHIFT)
#define GPIO_Y_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM2_SHIFT)
#define GPIO_Y_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM3_SHIFT)
#define GPIO_Y_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM4_SHIFT)
#define GPIO_Y_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM5_SHIFT)
#define GPIO_Y_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM6_SHIFT)
#define GPIO_Y_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM7_SHIFT)
#define GPIO_Y_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM8_SHIFT)
#define GPIO_Y_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_04_0
#define GPIO_Y_SCR_04_0                 _MK_ADDR_CONST(0x10e4)
#define GPIO_Y_SCR_04_0_SECURE                  0x0
#define GPIO_Y_SCR_04_0_SCR                     0
#define GPIO_Y_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR7_SHIFT)
#define GPIO_Y_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR6_SHIFT)
#define GPIO_Y_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR5_SHIFT)
#define GPIO_Y_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR4_SHIFT)
#define GPIO_Y_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR3_SHIFT)
#define GPIO_Y_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR2_SHIFT)
#define GPIO_Y_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR1_SHIFT)
#define GPIO_Y_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR0_SHIFT)
#define GPIO_Y_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7W_SHIFT)
#define GPIO_Y_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6W_SHIFT)
#define GPIO_Y_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5W_SHIFT)
#define GPIO_Y_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4W_SHIFT)
#define GPIO_Y_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3W_SHIFT)
#define GPIO_Y_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2W_SHIFT)
#define GPIO_Y_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1W_SHIFT)
#define GPIO_Y_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0W_SHIFT)
#define GPIO_Y_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7R_SHIFT)
#define GPIO_Y_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6R_SHIFT)
#define GPIO_Y_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5R_SHIFT)
#define GPIO_Y_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4R_SHIFT)
#define GPIO_Y_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3R_SHIFT)
#define GPIO_Y_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2R_SHIFT)
#define GPIO_Y_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1R_SHIFT)
#define GPIO_Y_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0R_SHIFT)
#define GPIO_Y_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_05_0
#define GPIO_Y_VM_05_0                  _MK_ADDR_CONST(0x10e8)
#define GPIO_Y_VM_05_0_SECURE                   0x0
#define GPIO_Y_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM1_SHIFT)
#define GPIO_Y_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM2_SHIFT)
#define GPIO_Y_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM3_SHIFT)
#define GPIO_Y_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM4_SHIFT)
#define GPIO_Y_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM5_SHIFT)
#define GPIO_Y_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM6_SHIFT)
#define GPIO_Y_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM7_SHIFT)
#define GPIO_Y_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM8_SHIFT)
#define GPIO_Y_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_05_0
#define GPIO_Y_SCR_05_0                 _MK_ADDR_CONST(0x10ec)
#define GPIO_Y_SCR_05_0_SECURE                  0x0
#define GPIO_Y_SCR_05_0_SCR                     0
#define GPIO_Y_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR7_SHIFT)
#define GPIO_Y_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR6_SHIFT)
#define GPIO_Y_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR5_SHIFT)
#define GPIO_Y_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR4_SHIFT)
#define GPIO_Y_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR3_SHIFT)
#define GPIO_Y_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR2_SHIFT)
#define GPIO_Y_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR1_SHIFT)
#define GPIO_Y_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR0_SHIFT)
#define GPIO_Y_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7W_SHIFT)
#define GPIO_Y_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6W_SHIFT)
#define GPIO_Y_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5W_SHIFT)
#define GPIO_Y_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4W_SHIFT)
#define GPIO_Y_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3W_SHIFT)
#define GPIO_Y_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2W_SHIFT)
#define GPIO_Y_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1W_SHIFT)
#define GPIO_Y_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0W_SHIFT)
#define GPIO_Y_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7R_SHIFT)
#define GPIO_Y_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6R_SHIFT)
#define GPIO_Y_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5R_SHIFT)
#define GPIO_Y_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4R_SHIFT)
#define GPIO_Y_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3R_SHIFT)
#define GPIO_Y_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2R_SHIFT)
#define GPIO_Y_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1R_SHIFT)
#define GPIO_Y_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0R_SHIFT)
#define GPIO_Y_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_Y_VM_06_0
#define GPIO_Y_VM_06_0                  _MK_ADDR_CONST(0x10f0)
#define GPIO_Y_VM_06_0_SECURE                   0x0
#define GPIO_Y_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM1_SHIFT)
#define GPIO_Y_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM2_SHIFT)
#define GPIO_Y_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM3_SHIFT)
#define GPIO_Y_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM4_SHIFT)
#define GPIO_Y_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM5_SHIFT)
#define GPIO_Y_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM6_SHIFT)
#define GPIO_Y_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM7_SHIFT)
#define GPIO_Y_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_Y_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM8_SHIFT)
#define GPIO_Y_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_SCR_06_0
#define GPIO_Y_SCR_06_0                 _MK_ADDR_CONST(0x10f4)
#define GPIO_Y_SCR_06_0_SECURE                  0x0
#define GPIO_Y_SCR_06_0_SCR                     0
#define GPIO_Y_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR7_SHIFT)
#define GPIO_Y_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR6_SHIFT)
#define GPIO_Y_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR5_SHIFT)
#define GPIO_Y_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR4_SHIFT)
#define GPIO_Y_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR3_SHIFT)
#define GPIO_Y_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR2_SHIFT)
#define GPIO_Y_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR1_SHIFT)
#define GPIO_Y_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR0_SHIFT)
#define GPIO_Y_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7W_SHIFT)
#define GPIO_Y_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6W_SHIFT)
#define GPIO_Y_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5W_SHIFT)
#define GPIO_Y_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4W_SHIFT)
#define GPIO_Y_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3W_SHIFT)
#define GPIO_Y_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2W_SHIFT)
#define GPIO_Y_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1W_SHIFT)
#define GPIO_Y_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0W_SHIFT)
#define GPIO_Y_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7R_SHIFT)
#define GPIO_Y_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6R_SHIFT)
#define GPIO_Y_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5R_SHIFT)
#define GPIO_Y_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4R_SHIFT)
#define GPIO_Y_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3R_SHIFT)
#define GPIO_Y_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2R_SHIFT)
#define GPIO_Y_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1R_SHIFT)
#define GPIO_Y_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_Y_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0R_SHIFT)
#define GPIO_Y_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 4344 [0x10f8]

// Reserved address 4348 [0x10fc]

// Register GPIO_CTL1_VM_SCR_0
#define GPIO_CTL1_VM_SCR_0                      _MK_ADDR_CONST(0x1800)
#define GPIO_CTL1_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL1_VM_SCR_0_SCR                  0
#define GPIO_CTL1_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL1_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL1_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL1_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL1_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL1_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL1_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL1_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL1_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL1_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL1_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL1_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL1_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL1_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL1_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL1_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL1_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL1_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL1_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL1_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL1_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL1_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL1_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL1_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL1_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL1_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL1_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL1_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL1_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL1_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL1_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL1_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL1_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL1_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL1_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL1_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL1_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL1_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL1_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL1_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL1_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL1_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL1_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL1_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL1_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL1_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL1_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL1_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL1_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL1_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL1_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL1_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x1804)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x1808)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL1_SCR_0
#define GPIO_CTL1_SCR_0                 _MK_ADDR_CONST(0x180c)
#define GPIO_CTL1_SCR_0_SECURE                  0x0
#define GPIO_CTL1_SCR_0_SCR                     0
#define GPIO_CTL1_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL1_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL1_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL1_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL1_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL1_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL1_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL1_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL1_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL1_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL1_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL1_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL1_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL1_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL1_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL1_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL1_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL1_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL1_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL1_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL1_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL1_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL1_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL1_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL1_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL1_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL1_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL1_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL1_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL1_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL1_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL1_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL1_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL1_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL1_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL1_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL1_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL1_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL1_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL1_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL1_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL1_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL1_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL1_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL1_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL1_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL1_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL1_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL1_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL1_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL1_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL1_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL1_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL1_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL1_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL1_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL1_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL1_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL1_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL1_ICG_EN_OVERRIDE_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x1810)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL1_SPARE_0
#define GPIO_CTL1_SPARE_0                       _MK_ADDR_CONST(0x1814)
#define GPIO_CTL1_SPARE_0_SECURE                        0x0
#define GPIO_CTL1_SPARE_0_SCR                   0
#define GPIO_CTL1_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL1_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL1_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL1_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL1_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL1_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_00_0
#define GPIO_A_VM_00_0                  _MK_ADDR_CONST(0x2000)
#define GPIO_A_VM_00_0_SECURE                   0x0
#define GPIO_A_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_00_0_WORD_COUNT                       0x1
#define GPIO_A_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM1_SHIFT)
#define GPIO_A_VM_00_0_VM1_RANGE                        1:0
#define GPIO_A_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM2_SHIFT)
#define GPIO_A_VM_00_0_VM2_RANGE                        3:2
#define GPIO_A_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM3_SHIFT)
#define GPIO_A_VM_00_0_VM3_RANGE                        5:4
#define GPIO_A_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM4_SHIFT)
#define GPIO_A_VM_00_0_VM4_RANGE                        7:6
#define GPIO_A_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM5_SHIFT)
#define GPIO_A_VM_00_0_VM5_RANGE                        9:8
#define GPIO_A_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM6_SHIFT)
#define GPIO_A_VM_00_0_VM6_RANGE                        11:10
#define GPIO_A_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM7_SHIFT)
#define GPIO_A_VM_00_0_VM7_RANGE                        13:12
#define GPIO_A_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM8_SHIFT)
#define GPIO_A_VM_00_0_VM8_RANGE                        15:14
#define GPIO_A_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_00_0
#define GPIO_A_SCR_00_0                 _MK_ADDR_CONST(0x2004)
#define GPIO_A_SCR_00_0_SECURE                  0x0
#define GPIO_A_SCR_00_0_SCR                     0
#define GPIO_A_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR7_SHIFT)
#define GPIO_A_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR6_SHIFT)
#define GPIO_A_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR5_SHIFT)
#define GPIO_A_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR4_SHIFT)
#define GPIO_A_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR3_SHIFT)
#define GPIO_A_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR2_SHIFT)
#define GPIO_A_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR1_SHIFT)
#define GPIO_A_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR0_SHIFT)
#define GPIO_A_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7W_SHIFT)
#define GPIO_A_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6W_SHIFT)
#define GPIO_A_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5W_SHIFT)
#define GPIO_A_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4W_SHIFT)
#define GPIO_A_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3W_SHIFT)
#define GPIO_A_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2W_SHIFT)
#define GPIO_A_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1W_SHIFT)
#define GPIO_A_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0W_SHIFT)
#define GPIO_A_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7R_SHIFT)
#define GPIO_A_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6R_SHIFT)
#define GPIO_A_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5R_SHIFT)
#define GPIO_A_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4R_SHIFT)
#define GPIO_A_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3R_SHIFT)
#define GPIO_A_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2R_SHIFT)
#define GPIO_A_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1R_SHIFT)
#define GPIO_A_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0R_SHIFT)
#define GPIO_A_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_01_0
#define GPIO_A_VM_01_0                  _MK_ADDR_CONST(0x2008)
#define GPIO_A_VM_01_0_SECURE                   0x0
#define GPIO_A_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_01_0_WORD_COUNT                       0x1
#define GPIO_A_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM1_SHIFT)
#define GPIO_A_VM_01_0_VM1_RANGE                        1:0
#define GPIO_A_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM2_SHIFT)
#define GPIO_A_VM_01_0_VM2_RANGE                        3:2
#define GPIO_A_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM3_SHIFT)
#define GPIO_A_VM_01_0_VM3_RANGE                        5:4
#define GPIO_A_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM4_SHIFT)
#define GPIO_A_VM_01_0_VM4_RANGE                        7:6
#define GPIO_A_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM5_SHIFT)
#define GPIO_A_VM_01_0_VM5_RANGE                        9:8
#define GPIO_A_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM6_SHIFT)
#define GPIO_A_VM_01_0_VM6_RANGE                        11:10
#define GPIO_A_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM7_SHIFT)
#define GPIO_A_VM_01_0_VM7_RANGE                        13:12
#define GPIO_A_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM8_SHIFT)
#define GPIO_A_VM_01_0_VM8_RANGE                        15:14
#define GPIO_A_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_01_0
#define GPIO_A_SCR_01_0                 _MK_ADDR_CONST(0x200c)
#define GPIO_A_SCR_01_0_SECURE                  0x0
#define GPIO_A_SCR_01_0_SCR                     0
#define GPIO_A_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR7_SHIFT)
#define GPIO_A_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR6_SHIFT)
#define GPIO_A_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR5_SHIFT)
#define GPIO_A_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR4_SHIFT)
#define GPIO_A_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR3_SHIFT)
#define GPIO_A_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR2_SHIFT)
#define GPIO_A_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR1_SHIFT)
#define GPIO_A_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR0_SHIFT)
#define GPIO_A_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7W_SHIFT)
#define GPIO_A_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6W_SHIFT)
#define GPIO_A_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5W_SHIFT)
#define GPIO_A_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4W_SHIFT)
#define GPIO_A_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3W_SHIFT)
#define GPIO_A_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2W_SHIFT)
#define GPIO_A_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1W_SHIFT)
#define GPIO_A_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0W_SHIFT)
#define GPIO_A_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7R_SHIFT)
#define GPIO_A_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6R_SHIFT)
#define GPIO_A_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5R_SHIFT)
#define GPIO_A_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4R_SHIFT)
#define GPIO_A_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3R_SHIFT)
#define GPIO_A_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2R_SHIFT)
#define GPIO_A_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1R_SHIFT)
#define GPIO_A_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0R_SHIFT)
#define GPIO_A_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_02_0
#define GPIO_A_VM_02_0                  _MK_ADDR_CONST(0x2010)
#define GPIO_A_VM_02_0_SECURE                   0x0
#define GPIO_A_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_02_0_WORD_COUNT                       0x1
#define GPIO_A_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM1_SHIFT)
#define GPIO_A_VM_02_0_VM1_RANGE                        1:0
#define GPIO_A_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM2_SHIFT)
#define GPIO_A_VM_02_0_VM2_RANGE                        3:2
#define GPIO_A_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM3_SHIFT)
#define GPIO_A_VM_02_0_VM3_RANGE                        5:4
#define GPIO_A_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM4_SHIFT)
#define GPIO_A_VM_02_0_VM4_RANGE                        7:6
#define GPIO_A_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM5_SHIFT)
#define GPIO_A_VM_02_0_VM5_RANGE                        9:8
#define GPIO_A_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM6_SHIFT)
#define GPIO_A_VM_02_0_VM6_RANGE                        11:10
#define GPIO_A_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM7_SHIFT)
#define GPIO_A_VM_02_0_VM7_RANGE                        13:12
#define GPIO_A_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM8_SHIFT)
#define GPIO_A_VM_02_0_VM8_RANGE                        15:14
#define GPIO_A_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_02_0
#define GPIO_A_SCR_02_0                 _MK_ADDR_CONST(0x2014)
#define GPIO_A_SCR_02_0_SECURE                  0x0
#define GPIO_A_SCR_02_0_SCR                     0
#define GPIO_A_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR7_SHIFT)
#define GPIO_A_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR6_SHIFT)
#define GPIO_A_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR5_SHIFT)
#define GPIO_A_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR4_SHIFT)
#define GPIO_A_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR3_SHIFT)
#define GPIO_A_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR2_SHIFT)
#define GPIO_A_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR1_SHIFT)
#define GPIO_A_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR0_SHIFT)
#define GPIO_A_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7W_SHIFT)
#define GPIO_A_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6W_SHIFT)
#define GPIO_A_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5W_SHIFT)
#define GPIO_A_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4W_SHIFT)
#define GPIO_A_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3W_SHIFT)
#define GPIO_A_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2W_SHIFT)
#define GPIO_A_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1W_SHIFT)
#define GPIO_A_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0W_SHIFT)
#define GPIO_A_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7R_SHIFT)
#define GPIO_A_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6R_SHIFT)
#define GPIO_A_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5R_SHIFT)
#define GPIO_A_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4R_SHIFT)
#define GPIO_A_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3R_SHIFT)
#define GPIO_A_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2R_SHIFT)
#define GPIO_A_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1R_SHIFT)
#define GPIO_A_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0R_SHIFT)
#define GPIO_A_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_03_0
#define GPIO_A_VM_03_0                  _MK_ADDR_CONST(0x2018)
#define GPIO_A_VM_03_0_SECURE                   0x0
#define GPIO_A_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_03_0_WORD_COUNT                       0x1
#define GPIO_A_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM1_SHIFT)
#define GPIO_A_VM_03_0_VM1_RANGE                        1:0
#define GPIO_A_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM2_SHIFT)
#define GPIO_A_VM_03_0_VM2_RANGE                        3:2
#define GPIO_A_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM3_SHIFT)
#define GPIO_A_VM_03_0_VM3_RANGE                        5:4
#define GPIO_A_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM4_SHIFT)
#define GPIO_A_VM_03_0_VM4_RANGE                        7:6
#define GPIO_A_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM5_SHIFT)
#define GPIO_A_VM_03_0_VM5_RANGE                        9:8
#define GPIO_A_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM6_SHIFT)
#define GPIO_A_VM_03_0_VM6_RANGE                        11:10
#define GPIO_A_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM7_SHIFT)
#define GPIO_A_VM_03_0_VM7_RANGE                        13:12
#define GPIO_A_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM8_SHIFT)
#define GPIO_A_VM_03_0_VM8_RANGE                        15:14
#define GPIO_A_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_03_0
#define GPIO_A_SCR_03_0                 _MK_ADDR_CONST(0x201c)
#define GPIO_A_SCR_03_0_SECURE                  0x0
#define GPIO_A_SCR_03_0_SCR                     0
#define GPIO_A_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR7_SHIFT)
#define GPIO_A_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR6_SHIFT)
#define GPIO_A_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR5_SHIFT)
#define GPIO_A_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR4_SHIFT)
#define GPIO_A_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR3_SHIFT)
#define GPIO_A_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR2_SHIFT)
#define GPIO_A_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR1_SHIFT)
#define GPIO_A_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR0_SHIFT)
#define GPIO_A_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7W_SHIFT)
#define GPIO_A_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6W_SHIFT)
#define GPIO_A_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5W_SHIFT)
#define GPIO_A_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4W_SHIFT)
#define GPIO_A_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3W_SHIFT)
#define GPIO_A_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2W_SHIFT)
#define GPIO_A_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1W_SHIFT)
#define GPIO_A_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0W_SHIFT)
#define GPIO_A_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7R_SHIFT)
#define GPIO_A_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6R_SHIFT)
#define GPIO_A_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5R_SHIFT)
#define GPIO_A_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4R_SHIFT)
#define GPIO_A_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3R_SHIFT)
#define GPIO_A_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2R_SHIFT)
#define GPIO_A_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1R_SHIFT)
#define GPIO_A_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0R_SHIFT)
#define GPIO_A_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_04_0
#define GPIO_A_VM_04_0                  _MK_ADDR_CONST(0x2020)
#define GPIO_A_VM_04_0_SECURE                   0x0
#define GPIO_A_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_04_0_WORD_COUNT                       0x1
#define GPIO_A_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM1_SHIFT)
#define GPIO_A_VM_04_0_VM1_RANGE                        1:0
#define GPIO_A_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM2_SHIFT)
#define GPIO_A_VM_04_0_VM2_RANGE                        3:2
#define GPIO_A_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM3_SHIFT)
#define GPIO_A_VM_04_0_VM3_RANGE                        5:4
#define GPIO_A_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM4_SHIFT)
#define GPIO_A_VM_04_0_VM4_RANGE                        7:6
#define GPIO_A_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM5_SHIFT)
#define GPIO_A_VM_04_0_VM5_RANGE                        9:8
#define GPIO_A_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM6_SHIFT)
#define GPIO_A_VM_04_0_VM6_RANGE                        11:10
#define GPIO_A_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM7_SHIFT)
#define GPIO_A_VM_04_0_VM7_RANGE                        13:12
#define GPIO_A_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM8_SHIFT)
#define GPIO_A_VM_04_0_VM8_RANGE                        15:14
#define GPIO_A_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_04_0
#define GPIO_A_SCR_04_0                 _MK_ADDR_CONST(0x2024)
#define GPIO_A_SCR_04_0_SECURE                  0x0
#define GPIO_A_SCR_04_0_SCR                     0
#define GPIO_A_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR7_SHIFT)
#define GPIO_A_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR6_SHIFT)
#define GPIO_A_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR5_SHIFT)
#define GPIO_A_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR4_SHIFT)
#define GPIO_A_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR3_SHIFT)
#define GPIO_A_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR2_SHIFT)
#define GPIO_A_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR1_SHIFT)
#define GPIO_A_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR0_SHIFT)
#define GPIO_A_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7W_SHIFT)
#define GPIO_A_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6W_SHIFT)
#define GPIO_A_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5W_SHIFT)
#define GPIO_A_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4W_SHIFT)
#define GPIO_A_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3W_SHIFT)
#define GPIO_A_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2W_SHIFT)
#define GPIO_A_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1W_SHIFT)
#define GPIO_A_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0W_SHIFT)
#define GPIO_A_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7R_SHIFT)
#define GPIO_A_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6R_SHIFT)
#define GPIO_A_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5R_SHIFT)
#define GPIO_A_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4R_SHIFT)
#define GPIO_A_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3R_SHIFT)
#define GPIO_A_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2R_SHIFT)
#define GPIO_A_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1R_SHIFT)
#define GPIO_A_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0R_SHIFT)
#define GPIO_A_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_05_0
#define GPIO_A_VM_05_0                  _MK_ADDR_CONST(0x2028)
#define GPIO_A_VM_05_0_SECURE                   0x0
#define GPIO_A_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_05_0_WORD_COUNT                       0x1
#define GPIO_A_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM1_SHIFT)
#define GPIO_A_VM_05_0_VM1_RANGE                        1:0
#define GPIO_A_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM2_SHIFT)
#define GPIO_A_VM_05_0_VM2_RANGE                        3:2
#define GPIO_A_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM3_SHIFT)
#define GPIO_A_VM_05_0_VM3_RANGE                        5:4
#define GPIO_A_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM4_SHIFT)
#define GPIO_A_VM_05_0_VM4_RANGE                        7:6
#define GPIO_A_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM5_SHIFT)
#define GPIO_A_VM_05_0_VM5_RANGE                        9:8
#define GPIO_A_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM6_SHIFT)
#define GPIO_A_VM_05_0_VM6_RANGE                        11:10
#define GPIO_A_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM7_SHIFT)
#define GPIO_A_VM_05_0_VM7_RANGE                        13:12
#define GPIO_A_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM8_SHIFT)
#define GPIO_A_VM_05_0_VM8_RANGE                        15:14
#define GPIO_A_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_05_0
#define GPIO_A_SCR_05_0                 _MK_ADDR_CONST(0x202c)
#define GPIO_A_SCR_05_0_SECURE                  0x0
#define GPIO_A_SCR_05_0_SCR                     0
#define GPIO_A_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR7_SHIFT)
#define GPIO_A_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR6_SHIFT)
#define GPIO_A_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR5_SHIFT)
#define GPIO_A_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR4_SHIFT)
#define GPIO_A_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR3_SHIFT)
#define GPIO_A_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR2_SHIFT)
#define GPIO_A_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR1_SHIFT)
#define GPIO_A_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR0_SHIFT)
#define GPIO_A_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7W_SHIFT)
#define GPIO_A_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6W_SHIFT)
#define GPIO_A_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5W_SHIFT)
#define GPIO_A_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4W_SHIFT)
#define GPIO_A_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3W_SHIFT)
#define GPIO_A_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2W_SHIFT)
#define GPIO_A_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1W_SHIFT)
#define GPIO_A_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0W_SHIFT)
#define GPIO_A_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7R_SHIFT)
#define GPIO_A_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6R_SHIFT)
#define GPIO_A_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5R_SHIFT)
#define GPIO_A_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4R_SHIFT)
#define GPIO_A_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3R_SHIFT)
#define GPIO_A_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2R_SHIFT)
#define GPIO_A_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1R_SHIFT)
#define GPIO_A_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0R_SHIFT)
#define GPIO_A_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_A_VM_06_0
#define GPIO_A_VM_06_0                  _MK_ADDR_CONST(0x2030)
#define GPIO_A_VM_06_0_SECURE                   0x0
#define GPIO_A_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_A_VM_06_0_WORD_COUNT                       0x1
#define GPIO_A_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM1_SHIFT)
#define GPIO_A_VM_06_0_VM1_RANGE                        1:0
#define GPIO_A_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM2_SHIFT)
#define GPIO_A_VM_06_0_VM2_RANGE                        3:2
#define GPIO_A_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM3_SHIFT)
#define GPIO_A_VM_06_0_VM3_RANGE                        5:4
#define GPIO_A_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM4_SHIFT)
#define GPIO_A_VM_06_0_VM4_RANGE                        7:6
#define GPIO_A_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM5_SHIFT)
#define GPIO_A_VM_06_0_VM5_RANGE                        9:8
#define GPIO_A_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM6_SHIFT)
#define GPIO_A_VM_06_0_VM6_RANGE                        11:10
#define GPIO_A_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM7_SHIFT)
#define GPIO_A_VM_06_0_VM7_RANGE                        13:12
#define GPIO_A_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_A_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM8_SHIFT)
#define GPIO_A_VM_06_0_VM8_RANGE                        15:14
#define GPIO_A_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_SCR_06_0
#define GPIO_A_SCR_06_0                 _MK_ADDR_CONST(0x2034)
#define GPIO_A_SCR_06_0_SECURE                  0x0
#define GPIO_A_SCR_06_0_SCR                     0
#define GPIO_A_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR7_SHIFT)
#define GPIO_A_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR6_SHIFT)
#define GPIO_A_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR5_SHIFT)
#define GPIO_A_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR4_SHIFT)
#define GPIO_A_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR3_SHIFT)
#define GPIO_A_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR2_SHIFT)
#define GPIO_A_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR1_SHIFT)
#define GPIO_A_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR0_SHIFT)
#define GPIO_A_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7W_SHIFT)
#define GPIO_A_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6W_SHIFT)
#define GPIO_A_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5W_SHIFT)
#define GPIO_A_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4W_SHIFT)
#define GPIO_A_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3W_SHIFT)
#define GPIO_A_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2W_SHIFT)
#define GPIO_A_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1W_SHIFT)
#define GPIO_A_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0W_SHIFT)
#define GPIO_A_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7R_SHIFT)
#define GPIO_A_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6R_SHIFT)
#define GPIO_A_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5R_SHIFT)
#define GPIO_A_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4R_SHIFT)
#define GPIO_A_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3R_SHIFT)
#define GPIO_A_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2R_SHIFT)
#define GPIO_A_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1R_SHIFT)
#define GPIO_A_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_A_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0R_SHIFT)
#define GPIO_A_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 8248 [0x2038]

// Reserved address 8252 [0x203c]

// Register GPIO_E_VM_00_0
#define GPIO_E_VM_00_0                  _MK_ADDR_CONST(0x2040)
#define GPIO_E_VM_00_0_SECURE                   0x0
#define GPIO_E_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_00_0_WORD_COUNT                       0x1
#define GPIO_E_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM1_SHIFT)
#define GPIO_E_VM_00_0_VM1_RANGE                        1:0
#define GPIO_E_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM2_SHIFT)
#define GPIO_E_VM_00_0_VM2_RANGE                        3:2
#define GPIO_E_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM3_SHIFT)
#define GPIO_E_VM_00_0_VM3_RANGE                        5:4
#define GPIO_E_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM4_SHIFT)
#define GPIO_E_VM_00_0_VM4_RANGE                        7:6
#define GPIO_E_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM5_SHIFT)
#define GPIO_E_VM_00_0_VM5_RANGE                        9:8
#define GPIO_E_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM6_SHIFT)
#define GPIO_E_VM_00_0_VM6_RANGE                        11:10
#define GPIO_E_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM7_SHIFT)
#define GPIO_E_VM_00_0_VM7_RANGE                        13:12
#define GPIO_E_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM8_SHIFT)
#define GPIO_E_VM_00_0_VM8_RANGE                        15:14
#define GPIO_E_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_00_0
#define GPIO_E_SCR_00_0                 _MK_ADDR_CONST(0x2044)
#define GPIO_E_SCR_00_0_SECURE                  0x0
#define GPIO_E_SCR_00_0_SCR                     0
#define GPIO_E_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR7_SHIFT)
#define GPIO_E_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR6_SHIFT)
#define GPIO_E_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR5_SHIFT)
#define GPIO_E_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR4_SHIFT)
#define GPIO_E_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR3_SHIFT)
#define GPIO_E_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR2_SHIFT)
#define GPIO_E_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR1_SHIFT)
#define GPIO_E_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR0_SHIFT)
#define GPIO_E_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7W_SHIFT)
#define GPIO_E_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6W_SHIFT)
#define GPIO_E_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5W_SHIFT)
#define GPIO_E_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4W_SHIFT)
#define GPIO_E_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3W_SHIFT)
#define GPIO_E_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2W_SHIFT)
#define GPIO_E_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1W_SHIFT)
#define GPIO_E_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0W_SHIFT)
#define GPIO_E_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7R_SHIFT)
#define GPIO_E_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6R_SHIFT)
#define GPIO_E_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5R_SHIFT)
#define GPIO_E_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4R_SHIFT)
#define GPIO_E_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3R_SHIFT)
#define GPIO_E_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2R_SHIFT)
#define GPIO_E_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1R_SHIFT)
#define GPIO_E_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0R_SHIFT)
#define GPIO_E_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_01_0
#define GPIO_E_VM_01_0                  _MK_ADDR_CONST(0x2048)
#define GPIO_E_VM_01_0_SECURE                   0x0
#define GPIO_E_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_01_0_WORD_COUNT                       0x1
#define GPIO_E_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM1_SHIFT)
#define GPIO_E_VM_01_0_VM1_RANGE                        1:0
#define GPIO_E_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM2_SHIFT)
#define GPIO_E_VM_01_0_VM2_RANGE                        3:2
#define GPIO_E_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM3_SHIFT)
#define GPIO_E_VM_01_0_VM3_RANGE                        5:4
#define GPIO_E_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM4_SHIFT)
#define GPIO_E_VM_01_0_VM4_RANGE                        7:6
#define GPIO_E_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM5_SHIFT)
#define GPIO_E_VM_01_0_VM5_RANGE                        9:8
#define GPIO_E_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM6_SHIFT)
#define GPIO_E_VM_01_0_VM6_RANGE                        11:10
#define GPIO_E_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM7_SHIFT)
#define GPIO_E_VM_01_0_VM7_RANGE                        13:12
#define GPIO_E_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM8_SHIFT)
#define GPIO_E_VM_01_0_VM8_RANGE                        15:14
#define GPIO_E_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_01_0
#define GPIO_E_SCR_01_0                 _MK_ADDR_CONST(0x204c)
#define GPIO_E_SCR_01_0_SECURE                  0x0
#define GPIO_E_SCR_01_0_SCR                     0
#define GPIO_E_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR7_SHIFT)
#define GPIO_E_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR6_SHIFT)
#define GPIO_E_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR5_SHIFT)
#define GPIO_E_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR4_SHIFT)
#define GPIO_E_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR3_SHIFT)
#define GPIO_E_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR2_SHIFT)
#define GPIO_E_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR1_SHIFT)
#define GPIO_E_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR0_SHIFT)
#define GPIO_E_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7W_SHIFT)
#define GPIO_E_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6W_SHIFT)
#define GPIO_E_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5W_SHIFT)
#define GPIO_E_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4W_SHIFT)
#define GPIO_E_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3W_SHIFT)
#define GPIO_E_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2W_SHIFT)
#define GPIO_E_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1W_SHIFT)
#define GPIO_E_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0W_SHIFT)
#define GPIO_E_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7R_SHIFT)
#define GPIO_E_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6R_SHIFT)
#define GPIO_E_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5R_SHIFT)
#define GPIO_E_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4R_SHIFT)
#define GPIO_E_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3R_SHIFT)
#define GPIO_E_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2R_SHIFT)
#define GPIO_E_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1R_SHIFT)
#define GPIO_E_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0R_SHIFT)
#define GPIO_E_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_02_0
#define GPIO_E_VM_02_0                  _MK_ADDR_CONST(0x2050)
#define GPIO_E_VM_02_0_SECURE                   0x0
#define GPIO_E_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_02_0_WORD_COUNT                       0x1
#define GPIO_E_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM1_SHIFT)
#define GPIO_E_VM_02_0_VM1_RANGE                        1:0
#define GPIO_E_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM2_SHIFT)
#define GPIO_E_VM_02_0_VM2_RANGE                        3:2
#define GPIO_E_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM3_SHIFT)
#define GPIO_E_VM_02_0_VM3_RANGE                        5:4
#define GPIO_E_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM4_SHIFT)
#define GPIO_E_VM_02_0_VM4_RANGE                        7:6
#define GPIO_E_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM5_SHIFT)
#define GPIO_E_VM_02_0_VM5_RANGE                        9:8
#define GPIO_E_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM6_SHIFT)
#define GPIO_E_VM_02_0_VM6_RANGE                        11:10
#define GPIO_E_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM7_SHIFT)
#define GPIO_E_VM_02_0_VM7_RANGE                        13:12
#define GPIO_E_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM8_SHIFT)
#define GPIO_E_VM_02_0_VM8_RANGE                        15:14
#define GPIO_E_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_02_0
#define GPIO_E_SCR_02_0                 _MK_ADDR_CONST(0x2054)
#define GPIO_E_SCR_02_0_SECURE                  0x0
#define GPIO_E_SCR_02_0_SCR                     0
#define GPIO_E_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR7_SHIFT)
#define GPIO_E_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR6_SHIFT)
#define GPIO_E_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR5_SHIFT)
#define GPIO_E_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR4_SHIFT)
#define GPIO_E_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR3_SHIFT)
#define GPIO_E_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR2_SHIFT)
#define GPIO_E_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR1_SHIFT)
#define GPIO_E_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR0_SHIFT)
#define GPIO_E_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7W_SHIFT)
#define GPIO_E_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6W_SHIFT)
#define GPIO_E_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5W_SHIFT)
#define GPIO_E_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4W_SHIFT)
#define GPIO_E_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3W_SHIFT)
#define GPIO_E_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2W_SHIFT)
#define GPIO_E_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1W_SHIFT)
#define GPIO_E_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0W_SHIFT)
#define GPIO_E_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7R_SHIFT)
#define GPIO_E_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6R_SHIFT)
#define GPIO_E_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5R_SHIFT)
#define GPIO_E_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4R_SHIFT)
#define GPIO_E_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3R_SHIFT)
#define GPIO_E_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2R_SHIFT)
#define GPIO_E_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1R_SHIFT)
#define GPIO_E_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0R_SHIFT)
#define GPIO_E_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_03_0
#define GPIO_E_VM_03_0                  _MK_ADDR_CONST(0x2058)
#define GPIO_E_VM_03_0_SECURE                   0x0
#define GPIO_E_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_03_0_WORD_COUNT                       0x1
#define GPIO_E_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM1_SHIFT)
#define GPIO_E_VM_03_0_VM1_RANGE                        1:0
#define GPIO_E_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM2_SHIFT)
#define GPIO_E_VM_03_0_VM2_RANGE                        3:2
#define GPIO_E_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM3_SHIFT)
#define GPIO_E_VM_03_0_VM3_RANGE                        5:4
#define GPIO_E_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM4_SHIFT)
#define GPIO_E_VM_03_0_VM4_RANGE                        7:6
#define GPIO_E_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM5_SHIFT)
#define GPIO_E_VM_03_0_VM5_RANGE                        9:8
#define GPIO_E_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM6_SHIFT)
#define GPIO_E_VM_03_0_VM6_RANGE                        11:10
#define GPIO_E_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM7_SHIFT)
#define GPIO_E_VM_03_0_VM7_RANGE                        13:12
#define GPIO_E_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM8_SHIFT)
#define GPIO_E_VM_03_0_VM8_RANGE                        15:14
#define GPIO_E_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_03_0
#define GPIO_E_SCR_03_0                 _MK_ADDR_CONST(0x205c)
#define GPIO_E_SCR_03_0_SECURE                  0x0
#define GPIO_E_SCR_03_0_SCR                     0
#define GPIO_E_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR7_SHIFT)
#define GPIO_E_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR6_SHIFT)
#define GPIO_E_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR5_SHIFT)
#define GPIO_E_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR4_SHIFT)
#define GPIO_E_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR3_SHIFT)
#define GPIO_E_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR2_SHIFT)
#define GPIO_E_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR1_SHIFT)
#define GPIO_E_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR0_SHIFT)
#define GPIO_E_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7W_SHIFT)
#define GPIO_E_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6W_SHIFT)
#define GPIO_E_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5W_SHIFT)
#define GPIO_E_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4W_SHIFT)
#define GPIO_E_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3W_SHIFT)
#define GPIO_E_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2W_SHIFT)
#define GPIO_E_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1W_SHIFT)
#define GPIO_E_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0W_SHIFT)
#define GPIO_E_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7R_SHIFT)
#define GPIO_E_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6R_SHIFT)
#define GPIO_E_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5R_SHIFT)
#define GPIO_E_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4R_SHIFT)
#define GPIO_E_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3R_SHIFT)
#define GPIO_E_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2R_SHIFT)
#define GPIO_E_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1R_SHIFT)
#define GPIO_E_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0R_SHIFT)
#define GPIO_E_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_04_0
#define GPIO_E_VM_04_0                  _MK_ADDR_CONST(0x2060)
#define GPIO_E_VM_04_0_SECURE                   0x0
#define GPIO_E_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_04_0_WORD_COUNT                       0x1
#define GPIO_E_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM1_SHIFT)
#define GPIO_E_VM_04_0_VM1_RANGE                        1:0
#define GPIO_E_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM2_SHIFT)
#define GPIO_E_VM_04_0_VM2_RANGE                        3:2
#define GPIO_E_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM3_SHIFT)
#define GPIO_E_VM_04_0_VM3_RANGE                        5:4
#define GPIO_E_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM4_SHIFT)
#define GPIO_E_VM_04_0_VM4_RANGE                        7:6
#define GPIO_E_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM5_SHIFT)
#define GPIO_E_VM_04_0_VM5_RANGE                        9:8
#define GPIO_E_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM6_SHIFT)
#define GPIO_E_VM_04_0_VM6_RANGE                        11:10
#define GPIO_E_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM7_SHIFT)
#define GPIO_E_VM_04_0_VM7_RANGE                        13:12
#define GPIO_E_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM8_SHIFT)
#define GPIO_E_VM_04_0_VM8_RANGE                        15:14
#define GPIO_E_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_04_0
#define GPIO_E_SCR_04_0                 _MK_ADDR_CONST(0x2064)
#define GPIO_E_SCR_04_0_SECURE                  0x0
#define GPIO_E_SCR_04_0_SCR                     0
#define GPIO_E_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR7_SHIFT)
#define GPIO_E_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR6_SHIFT)
#define GPIO_E_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR5_SHIFT)
#define GPIO_E_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR4_SHIFT)
#define GPIO_E_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR3_SHIFT)
#define GPIO_E_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR2_SHIFT)
#define GPIO_E_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR1_SHIFT)
#define GPIO_E_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR0_SHIFT)
#define GPIO_E_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7W_SHIFT)
#define GPIO_E_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6W_SHIFT)
#define GPIO_E_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5W_SHIFT)
#define GPIO_E_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4W_SHIFT)
#define GPIO_E_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3W_SHIFT)
#define GPIO_E_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2W_SHIFT)
#define GPIO_E_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1W_SHIFT)
#define GPIO_E_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0W_SHIFT)
#define GPIO_E_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7R_SHIFT)
#define GPIO_E_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6R_SHIFT)
#define GPIO_E_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5R_SHIFT)
#define GPIO_E_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4R_SHIFT)
#define GPIO_E_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3R_SHIFT)
#define GPIO_E_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2R_SHIFT)
#define GPIO_E_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1R_SHIFT)
#define GPIO_E_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0R_SHIFT)
#define GPIO_E_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_05_0
#define GPIO_E_VM_05_0                  _MK_ADDR_CONST(0x2068)
#define GPIO_E_VM_05_0_SECURE                   0x0
#define GPIO_E_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_05_0_WORD_COUNT                       0x1
#define GPIO_E_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM1_SHIFT)
#define GPIO_E_VM_05_0_VM1_RANGE                        1:0
#define GPIO_E_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM2_SHIFT)
#define GPIO_E_VM_05_0_VM2_RANGE                        3:2
#define GPIO_E_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM3_SHIFT)
#define GPIO_E_VM_05_0_VM3_RANGE                        5:4
#define GPIO_E_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM4_SHIFT)
#define GPIO_E_VM_05_0_VM4_RANGE                        7:6
#define GPIO_E_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM5_SHIFT)
#define GPIO_E_VM_05_0_VM5_RANGE                        9:8
#define GPIO_E_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM6_SHIFT)
#define GPIO_E_VM_05_0_VM6_RANGE                        11:10
#define GPIO_E_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM7_SHIFT)
#define GPIO_E_VM_05_0_VM7_RANGE                        13:12
#define GPIO_E_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM8_SHIFT)
#define GPIO_E_VM_05_0_VM8_RANGE                        15:14
#define GPIO_E_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_05_0
#define GPIO_E_SCR_05_0                 _MK_ADDR_CONST(0x206c)
#define GPIO_E_SCR_05_0_SECURE                  0x0
#define GPIO_E_SCR_05_0_SCR                     0
#define GPIO_E_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR7_SHIFT)
#define GPIO_E_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR6_SHIFT)
#define GPIO_E_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR5_SHIFT)
#define GPIO_E_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR4_SHIFT)
#define GPIO_E_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR3_SHIFT)
#define GPIO_E_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR2_SHIFT)
#define GPIO_E_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR1_SHIFT)
#define GPIO_E_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR0_SHIFT)
#define GPIO_E_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7W_SHIFT)
#define GPIO_E_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6W_SHIFT)
#define GPIO_E_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5W_SHIFT)
#define GPIO_E_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4W_SHIFT)
#define GPIO_E_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3W_SHIFT)
#define GPIO_E_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2W_SHIFT)
#define GPIO_E_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1W_SHIFT)
#define GPIO_E_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0W_SHIFT)
#define GPIO_E_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7R_SHIFT)
#define GPIO_E_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6R_SHIFT)
#define GPIO_E_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5R_SHIFT)
#define GPIO_E_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4R_SHIFT)
#define GPIO_E_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3R_SHIFT)
#define GPIO_E_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2R_SHIFT)
#define GPIO_E_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1R_SHIFT)
#define GPIO_E_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0R_SHIFT)
#define GPIO_E_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_06_0
#define GPIO_E_VM_06_0                  _MK_ADDR_CONST(0x2070)
#define GPIO_E_VM_06_0_SECURE                   0x0
#define GPIO_E_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_06_0_WORD_COUNT                       0x1
#define GPIO_E_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM1_SHIFT)
#define GPIO_E_VM_06_0_VM1_RANGE                        1:0
#define GPIO_E_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM2_SHIFT)
#define GPIO_E_VM_06_0_VM2_RANGE                        3:2
#define GPIO_E_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM3_SHIFT)
#define GPIO_E_VM_06_0_VM3_RANGE                        5:4
#define GPIO_E_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM4_SHIFT)
#define GPIO_E_VM_06_0_VM4_RANGE                        7:6
#define GPIO_E_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM5_SHIFT)
#define GPIO_E_VM_06_0_VM5_RANGE                        9:8
#define GPIO_E_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM6_SHIFT)
#define GPIO_E_VM_06_0_VM6_RANGE                        11:10
#define GPIO_E_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM7_SHIFT)
#define GPIO_E_VM_06_0_VM7_RANGE                        13:12
#define GPIO_E_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM8_SHIFT)
#define GPIO_E_VM_06_0_VM8_RANGE                        15:14
#define GPIO_E_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_06_0
#define GPIO_E_SCR_06_0                 _MK_ADDR_CONST(0x2074)
#define GPIO_E_SCR_06_0_SECURE                  0x0
#define GPIO_E_SCR_06_0_SCR                     0
#define GPIO_E_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR7_SHIFT)
#define GPIO_E_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR6_SHIFT)
#define GPIO_E_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR5_SHIFT)
#define GPIO_E_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR4_SHIFT)
#define GPIO_E_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR3_SHIFT)
#define GPIO_E_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR2_SHIFT)
#define GPIO_E_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR1_SHIFT)
#define GPIO_E_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR0_SHIFT)
#define GPIO_E_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7W_SHIFT)
#define GPIO_E_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6W_SHIFT)
#define GPIO_E_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5W_SHIFT)
#define GPIO_E_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4W_SHIFT)
#define GPIO_E_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3W_SHIFT)
#define GPIO_E_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2W_SHIFT)
#define GPIO_E_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1W_SHIFT)
#define GPIO_E_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0W_SHIFT)
#define GPIO_E_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7R_SHIFT)
#define GPIO_E_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6R_SHIFT)
#define GPIO_E_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5R_SHIFT)
#define GPIO_E_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4R_SHIFT)
#define GPIO_E_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3R_SHIFT)
#define GPIO_E_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2R_SHIFT)
#define GPIO_E_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1R_SHIFT)
#define GPIO_E_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0R_SHIFT)
#define GPIO_E_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_E_VM_07_0
#define GPIO_E_VM_07_0                  _MK_ADDR_CONST(0x2078)
#define GPIO_E_VM_07_0_SECURE                   0x0
#define GPIO_E_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_E_VM_07_0_WORD_COUNT                       0x1
#define GPIO_E_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM1_SHIFT)
#define GPIO_E_VM_07_0_VM1_RANGE                        1:0
#define GPIO_E_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM2_SHIFT)
#define GPIO_E_VM_07_0_VM2_RANGE                        3:2
#define GPIO_E_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM3_SHIFT)
#define GPIO_E_VM_07_0_VM3_RANGE                        5:4
#define GPIO_E_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM4_SHIFT)
#define GPIO_E_VM_07_0_VM4_RANGE                        7:6
#define GPIO_E_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM5_SHIFT)
#define GPIO_E_VM_07_0_VM5_RANGE                        9:8
#define GPIO_E_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM6_SHIFT)
#define GPIO_E_VM_07_0_VM6_RANGE                        11:10
#define GPIO_E_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM7_SHIFT)
#define GPIO_E_VM_07_0_VM7_RANGE                        13:12
#define GPIO_E_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_E_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM8_SHIFT)
#define GPIO_E_VM_07_0_VM8_RANGE                        15:14
#define GPIO_E_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_SCR_07_0
#define GPIO_E_SCR_07_0                 _MK_ADDR_CONST(0x207c)
#define GPIO_E_SCR_07_0_SECURE                  0x0
#define GPIO_E_SCR_07_0_SCR                     0
#define GPIO_E_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR7_SHIFT)
#define GPIO_E_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR6_SHIFT)
#define GPIO_E_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR5_SHIFT)
#define GPIO_E_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR4_SHIFT)
#define GPIO_E_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR3_SHIFT)
#define GPIO_E_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR2_SHIFT)
#define GPIO_E_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR1_SHIFT)
#define GPIO_E_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR0_SHIFT)
#define GPIO_E_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7W_SHIFT)
#define GPIO_E_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6W_SHIFT)
#define GPIO_E_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5W_SHIFT)
#define GPIO_E_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4W_SHIFT)
#define GPIO_E_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3W_SHIFT)
#define GPIO_E_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2W_SHIFT)
#define GPIO_E_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1W_SHIFT)
#define GPIO_E_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0W_SHIFT)
#define GPIO_E_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7R_SHIFT)
#define GPIO_E_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6R_SHIFT)
#define GPIO_E_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5R_SHIFT)
#define GPIO_E_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4R_SHIFT)
#define GPIO_E_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3R_SHIFT)
#define GPIO_E_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2R_SHIFT)
#define GPIO_E_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1R_SHIFT)
#define GPIO_E_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_E_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0R_SHIFT)
#define GPIO_E_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_00_0
#define GPIO_F_VM_00_0                  _MK_ADDR_CONST(0x2080)
#define GPIO_F_VM_00_0_SECURE                   0x0
#define GPIO_F_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_00_0_WORD_COUNT                       0x1
#define GPIO_F_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM1_SHIFT)
#define GPIO_F_VM_00_0_VM1_RANGE                        1:0
#define GPIO_F_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM2_SHIFT)
#define GPIO_F_VM_00_0_VM2_RANGE                        3:2
#define GPIO_F_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM3_SHIFT)
#define GPIO_F_VM_00_0_VM3_RANGE                        5:4
#define GPIO_F_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM4_SHIFT)
#define GPIO_F_VM_00_0_VM4_RANGE                        7:6
#define GPIO_F_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM5_SHIFT)
#define GPIO_F_VM_00_0_VM5_RANGE                        9:8
#define GPIO_F_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM6_SHIFT)
#define GPIO_F_VM_00_0_VM6_RANGE                        11:10
#define GPIO_F_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM7_SHIFT)
#define GPIO_F_VM_00_0_VM7_RANGE                        13:12
#define GPIO_F_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM8_SHIFT)
#define GPIO_F_VM_00_0_VM8_RANGE                        15:14
#define GPIO_F_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_00_0
#define GPIO_F_SCR_00_0                 _MK_ADDR_CONST(0x2084)
#define GPIO_F_SCR_00_0_SECURE                  0x0
#define GPIO_F_SCR_00_0_SCR                     0
#define GPIO_F_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR7_SHIFT)
#define GPIO_F_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR6_SHIFT)
#define GPIO_F_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR5_SHIFT)
#define GPIO_F_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR4_SHIFT)
#define GPIO_F_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR3_SHIFT)
#define GPIO_F_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR2_SHIFT)
#define GPIO_F_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR1_SHIFT)
#define GPIO_F_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR0_SHIFT)
#define GPIO_F_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7W_SHIFT)
#define GPIO_F_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6W_SHIFT)
#define GPIO_F_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5W_SHIFT)
#define GPIO_F_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4W_SHIFT)
#define GPIO_F_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3W_SHIFT)
#define GPIO_F_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2W_SHIFT)
#define GPIO_F_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1W_SHIFT)
#define GPIO_F_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0W_SHIFT)
#define GPIO_F_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7R_SHIFT)
#define GPIO_F_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6R_SHIFT)
#define GPIO_F_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5R_SHIFT)
#define GPIO_F_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4R_SHIFT)
#define GPIO_F_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3R_SHIFT)
#define GPIO_F_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2R_SHIFT)
#define GPIO_F_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1R_SHIFT)
#define GPIO_F_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0R_SHIFT)
#define GPIO_F_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_01_0
#define GPIO_F_VM_01_0                  _MK_ADDR_CONST(0x2088)
#define GPIO_F_VM_01_0_SECURE                   0x0
#define GPIO_F_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_01_0_WORD_COUNT                       0x1
#define GPIO_F_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM1_SHIFT)
#define GPIO_F_VM_01_0_VM1_RANGE                        1:0
#define GPIO_F_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM2_SHIFT)
#define GPIO_F_VM_01_0_VM2_RANGE                        3:2
#define GPIO_F_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM3_SHIFT)
#define GPIO_F_VM_01_0_VM3_RANGE                        5:4
#define GPIO_F_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM4_SHIFT)
#define GPIO_F_VM_01_0_VM4_RANGE                        7:6
#define GPIO_F_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM5_SHIFT)
#define GPIO_F_VM_01_0_VM5_RANGE                        9:8
#define GPIO_F_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM6_SHIFT)
#define GPIO_F_VM_01_0_VM6_RANGE                        11:10
#define GPIO_F_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM7_SHIFT)
#define GPIO_F_VM_01_0_VM7_RANGE                        13:12
#define GPIO_F_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM8_SHIFT)
#define GPIO_F_VM_01_0_VM8_RANGE                        15:14
#define GPIO_F_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_01_0
#define GPIO_F_SCR_01_0                 _MK_ADDR_CONST(0x208c)
#define GPIO_F_SCR_01_0_SECURE                  0x0
#define GPIO_F_SCR_01_0_SCR                     0
#define GPIO_F_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR7_SHIFT)
#define GPIO_F_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR6_SHIFT)
#define GPIO_F_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR5_SHIFT)
#define GPIO_F_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR4_SHIFT)
#define GPIO_F_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR3_SHIFT)
#define GPIO_F_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR2_SHIFT)
#define GPIO_F_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR1_SHIFT)
#define GPIO_F_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR0_SHIFT)
#define GPIO_F_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7W_SHIFT)
#define GPIO_F_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6W_SHIFT)
#define GPIO_F_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5W_SHIFT)
#define GPIO_F_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4W_SHIFT)
#define GPIO_F_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3W_SHIFT)
#define GPIO_F_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2W_SHIFT)
#define GPIO_F_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1W_SHIFT)
#define GPIO_F_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0W_SHIFT)
#define GPIO_F_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7R_SHIFT)
#define GPIO_F_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6R_SHIFT)
#define GPIO_F_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5R_SHIFT)
#define GPIO_F_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4R_SHIFT)
#define GPIO_F_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3R_SHIFT)
#define GPIO_F_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2R_SHIFT)
#define GPIO_F_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1R_SHIFT)
#define GPIO_F_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0R_SHIFT)
#define GPIO_F_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_02_0
#define GPIO_F_VM_02_0                  _MK_ADDR_CONST(0x2090)
#define GPIO_F_VM_02_0_SECURE                   0x0
#define GPIO_F_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_02_0_WORD_COUNT                       0x1
#define GPIO_F_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM1_SHIFT)
#define GPIO_F_VM_02_0_VM1_RANGE                        1:0
#define GPIO_F_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM2_SHIFT)
#define GPIO_F_VM_02_0_VM2_RANGE                        3:2
#define GPIO_F_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM3_SHIFT)
#define GPIO_F_VM_02_0_VM3_RANGE                        5:4
#define GPIO_F_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM4_SHIFT)
#define GPIO_F_VM_02_0_VM4_RANGE                        7:6
#define GPIO_F_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM5_SHIFT)
#define GPIO_F_VM_02_0_VM5_RANGE                        9:8
#define GPIO_F_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM6_SHIFT)
#define GPIO_F_VM_02_0_VM6_RANGE                        11:10
#define GPIO_F_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM7_SHIFT)
#define GPIO_F_VM_02_0_VM7_RANGE                        13:12
#define GPIO_F_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM8_SHIFT)
#define GPIO_F_VM_02_0_VM8_RANGE                        15:14
#define GPIO_F_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_02_0
#define GPIO_F_SCR_02_0                 _MK_ADDR_CONST(0x2094)
#define GPIO_F_SCR_02_0_SECURE                  0x0
#define GPIO_F_SCR_02_0_SCR                     0
#define GPIO_F_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR7_SHIFT)
#define GPIO_F_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR6_SHIFT)
#define GPIO_F_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR5_SHIFT)
#define GPIO_F_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR4_SHIFT)
#define GPIO_F_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR3_SHIFT)
#define GPIO_F_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR2_SHIFT)
#define GPIO_F_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR1_SHIFT)
#define GPIO_F_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR0_SHIFT)
#define GPIO_F_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7W_SHIFT)
#define GPIO_F_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6W_SHIFT)
#define GPIO_F_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5W_SHIFT)
#define GPIO_F_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4W_SHIFT)
#define GPIO_F_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3W_SHIFT)
#define GPIO_F_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2W_SHIFT)
#define GPIO_F_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1W_SHIFT)
#define GPIO_F_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0W_SHIFT)
#define GPIO_F_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7R_SHIFT)
#define GPIO_F_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6R_SHIFT)
#define GPIO_F_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5R_SHIFT)
#define GPIO_F_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4R_SHIFT)
#define GPIO_F_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3R_SHIFT)
#define GPIO_F_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2R_SHIFT)
#define GPIO_F_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1R_SHIFT)
#define GPIO_F_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0R_SHIFT)
#define GPIO_F_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_03_0
#define GPIO_F_VM_03_0                  _MK_ADDR_CONST(0x2098)
#define GPIO_F_VM_03_0_SECURE                   0x0
#define GPIO_F_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_03_0_WORD_COUNT                       0x1
#define GPIO_F_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM1_SHIFT)
#define GPIO_F_VM_03_0_VM1_RANGE                        1:0
#define GPIO_F_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM2_SHIFT)
#define GPIO_F_VM_03_0_VM2_RANGE                        3:2
#define GPIO_F_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM3_SHIFT)
#define GPIO_F_VM_03_0_VM3_RANGE                        5:4
#define GPIO_F_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM4_SHIFT)
#define GPIO_F_VM_03_0_VM4_RANGE                        7:6
#define GPIO_F_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM5_SHIFT)
#define GPIO_F_VM_03_0_VM5_RANGE                        9:8
#define GPIO_F_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM6_SHIFT)
#define GPIO_F_VM_03_0_VM6_RANGE                        11:10
#define GPIO_F_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM7_SHIFT)
#define GPIO_F_VM_03_0_VM7_RANGE                        13:12
#define GPIO_F_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM8_SHIFT)
#define GPIO_F_VM_03_0_VM8_RANGE                        15:14
#define GPIO_F_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_03_0
#define GPIO_F_SCR_03_0                 _MK_ADDR_CONST(0x209c)
#define GPIO_F_SCR_03_0_SECURE                  0x0
#define GPIO_F_SCR_03_0_SCR                     0
#define GPIO_F_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR7_SHIFT)
#define GPIO_F_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR6_SHIFT)
#define GPIO_F_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR5_SHIFT)
#define GPIO_F_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR4_SHIFT)
#define GPIO_F_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR3_SHIFT)
#define GPIO_F_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR2_SHIFT)
#define GPIO_F_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR1_SHIFT)
#define GPIO_F_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR0_SHIFT)
#define GPIO_F_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7W_SHIFT)
#define GPIO_F_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6W_SHIFT)
#define GPIO_F_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5W_SHIFT)
#define GPIO_F_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4W_SHIFT)
#define GPIO_F_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3W_SHIFT)
#define GPIO_F_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2W_SHIFT)
#define GPIO_F_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1W_SHIFT)
#define GPIO_F_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0W_SHIFT)
#define GPIO_F_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7R_SHIFT)
#define GPIO_F_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6R_SHIFT)
#define GPIO_F_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5R_SHIFT)
#define GPIO_F_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4R_SHIFT)
#define GPIO_F_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3R_SHIFT)
#define GPIO_F_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2R_SHIFT)
#define GPIO_F_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1R_SHIFT)
#define GPIO_F_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0R_SHIFT)
#define GPIO_F_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_04_0
#define GPIO_F_VM_04_0                  _MK_ADDR_CONST(0x20a0)
#define GPIO_F_VM_04_0_SECURE                   0x0
#define GPIO_F_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_04_0_WORD_COUNT                       0x1
#define GPIO_F_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM1_SHIFT)
#define GPIO_F_VM_04_0_VM1_RANGE                        1:0
#define GPIO_F_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM2_SHIFT)
#define GPIO_F_VM_04_0_VM2_RANGE                        3:2
#define GPIO_F_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM3_SHIFT)
#define GPIO_F_VM_04_0_VM3_RANGE                        5:4
#define GPIO_F_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM4_SHIFT)
#define GPIO_F_VM_04_0_VM4_RANGE                        7:6
#define GPIO_F_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM5_SHIFT)
#define GPIO_F_VM_04_0_VM5_RANGE                        9:8
#define GPIO_F_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM6_SHIFT)
#define GPIO_F_VM_04_0_VM6_RANGE                        11:10
#define GPIO_F_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM7_SHIFT)
#define GPIO_F_VM_04_0_VM7_RANGE                        13:12
#define GPIO_F_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM8_SHIFT)
#define GPIO_F_VM_04_0_VM8_RANGE                        15:14
#define GPIO_F_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_04_0
#define GPIO_F_SCR_04_0                 _MK_ADDR_CONST(0x20a4)
#define GPIO_F_SCR_04_0_SECURE                  0x0
#define GPIO_F_SCR_04_0_SCR                     0
#define GPIO_F_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR7_SHIFT)
#define GPIO_F_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR6_SHIFT)
#define GPIO_F_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR5_SHIFT)
#define GPIO_F_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR4_SHIFT)
#define GPIO_F_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR3_SHIFT)
#define GPIO_F_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR2_SHIFT)
#define GPIO_F_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR1_SHIFT)
#define GPIO_F_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR0_SHIFT)
#define GPIO_F_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7W_SHIFT)
#define GPIO_F_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6W_SHIFT)
#define GPIO_F_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5W_SHIFT)
#define GPIO_F_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4W_SHIFT)
#define GPIO_F_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3W_SHIFT)
#define GPIO_F_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2W_SHIFT)
#define GPIO_F_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1W_SHIFT)
#define GPIO_F_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0W_SHIFT)
#define GPIO_F_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7R_SHIFT)
#define GPIO_F_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6R_SHIFT)
#define GPIO_F_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5R_SHIFT)
#define GPIO_F_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4R_SHIFT)
#define GPIO_F_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3R_SHIFT)
#define GPIO_F_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2R_SHIFT)
#define GPIO_F_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1R_SHIFT)
#define GPIO_F_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0R_SHIFT)
#define GPIO_F_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_F_VM_05_0
#define GPIO_F_VM_05_0                  _MK_ADDR_CONST(0x20a8)
#define GPIO_F_VM_05_0_SECURE                   0x0
#define GPIO_F_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_F_VM_05_0_WORD_COUNT                       0x1
#define GPIO_F_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM1_SHIFT)
#define GPIO_F_VM_05_0_VM1_RANGE                        1:0
#define GPIO_F_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM2_SHIFT)
#define GPIO_F_VM_05_0_VM2_RANGE                        3:2
#define GPIO_F_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM3_SHIFT)
#define GPIO_F_VM_05_0_VM3_RANGE                        5:4
#define GPIO_F_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM4_SHIFT)
#define GPIO_F_VM_05_0_VM4_RANGE                        7:6
#define GPIO_F_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM5_SHIFT)
#define GPIO_F_VM_05_0_VM5_RANGE                        9:8
#define GPIO_F_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM6_SHIFT)
#define GPIO_F_VM_05_0_VM6_RANGE                        11:10
#define GPIO_F_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM7_SHIFT)
#define GPIO_F_VM_05_0_VM7_RANGE                        13:12
#define GPIO_F_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_F_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM8_SHIFT)
#define GPIO_F_VM_05_0_VM8_RANGE                        15:14
#define GPIO_F_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_SCR_05_0
#define GPIO_F_SCR_05_0                 _MK_ADDR_CONST(0x20ac)
#define GPIO_F_SCR_05_0_SECURE                  0x0
#define GPIO_F_SCR_05_0_SCR                     0
#define GPIO_F_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR7_SHIFT)
#define GPIO_F_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR6_SHIFT)
#define GPIO_F_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR5_SHIFT)
#define GPIO_F_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR4_SHIFT)
#define GPIO_F_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR3_SHIFT)
#define GPIO_F_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR2_SHIFT)
#define GPIO_F_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR1_SHIFT)
#define GPIO_F_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR0_SHIFT)
#define GPIO_F_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7W_SHIFT)
#define GPIO_F_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6W_SHIFT)
#define GPIO_F_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5W_SHIFT)
#define GPIO_F_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4W_SHIFT)
#define GPIO_F_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3W_SHIFT)
#define GPIO_F_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2W_SHIFT)
#define GPIO_F_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1W_SHIFT)
#define GPIO_F_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0W_SHIFT)
#define GPIO_F_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7R_SHIFT)
#define GPIO_F_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6R_SHIFT)
#define GPIO_F_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5R_SHIFT)
#define GPIO_F_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4R_SHIFT)
#define GPIO_F_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3R_SHIFT)
#define GPIO_F_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2R_SHIFT)
#define GPIO_F_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1R_SHIFT)
#define GPIO_F_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_F_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0R_SHIFT)
#define GPIO_F_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 8368 [0x20b0]

// Reserved address 8372 [0x20b4]

// Reserved address 8376 [0x20b8]

// Reserved address 8380 [0x20bc]

// Register GPIO_BB_VM_00_0
#define GPIO_BB_VM_00_0                 _MK_ADDR_CONST(0x20c0)
#define GPIO_BB_VM_00_0_SECURE                  0x0
#define GPIO_BB_VM_00_0_SCR                     GPIO_CTL2_VM_SCR_0
#define GPIO_BB_VM_00_0_WORD_COUNT                      0x1
#define GPIO_BB_VM_00_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_00_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_00_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_00_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_VM_00_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM1_SHIFT)
#define GPIO_BB_VM_00_0_VM1_RANGE                       1:0
#define GPIO_BB_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_BB_VM_00_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM2_SHIFT)
#define GPIO_BB_VM_00_0_VM2_RANGE                       3:2
#define GPIO_BB_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_BB_VM_00_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM3_SHIFT)
#define GPIO_BB_VM_00_0_VM3_RANGE                       5:4
#define GPIO_BB_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_BB_VM_00_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM4_SHIFT)
#define GPIO_BB_VM_00_0_VM4_RANGE                       7:6
#define GPIO_BB_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_BB_VM_00_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM5_SHIFT)
#define GPIO_BB_VM_00_0_VM5_RANGE                       9:8
#define GPIO_BB_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_BB_VM_00_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM6_SHIFT)
#define GPIO_BB_VM_00_0_VM6_RANGE                       11:10
#define GPIO_BB_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_BB_VM_00_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM7_SHIFT)
#define GPIO_BB_VM_00_0_VM7_RANGE                       13:12
#define GPIO_BB_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_00_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_BB_VM_00_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_00_0_VM8_SHIFT)
#define GPIO_BB_VM_00_0_VM8_RANGE                       15:14
#define GPIO_BB_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_BB_VM_00_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_00_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_00_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_SCR_00_0
#define GPIO_BB_SCR_00_0                        _MK_ADDR_CONST(0x20c4)
#define GPIO_BB_SCR_00_0_SECURE                         0x0
#define GPIO_BB_SCR_00_0_SCR                    0
#define GPIO_BB_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_BB_SCR_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_00_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_00_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_BB_SCR_00_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_BB_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_BB_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_BB_SCR_00_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_BB_SCR_00_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_BB_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_BB_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_BB_SCR_00_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_BB_SCR_00_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_BB_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_BB_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_BB_SCR_00_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_BB_SCR_00_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_BB_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_BB_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_BB_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_BB_SCR_00_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_BB_SCR_00_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_BB_SCR_00_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR7_SHIFT)
#define GPIO_BB_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_BB_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_BB_SCR_00_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR6_SHIFT)
#define GPIO_BB_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_BB_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_BB_SCR_00_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR5_SHIFT)
#define GPIO_BB_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_BB_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_BB_SCR_00_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR4_SHIFT)
#define GPIO_BB_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_BB_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_BB_SCR_00_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR3_SHIFT)
#define GPIO_BB_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_BB_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_BB_SCR_00_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR2_SHIFT)
#define GPIO_BB_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_BB_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_BB_SCR_00_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR1_SHIFT)
#define GPIO_BB_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_BB_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_BB_SCR_00_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_PR0_SHIFT)
#define GPIO_BB_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_BB_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_BB_SCR_00_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G7W_SHIFT)
#define GPIO_BB_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_BB_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_BB_SCR_00_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G6W_SHIFT)
#define GPIO_BB_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_BB_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_BB_SCR_00_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G5W_SHIFT)
#define GPIO_BB_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_BB_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_BB_SCR_00_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G4W_SHIFT)
#define GPIO_BB_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_BB_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_BB_SCR_00_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G3W_SHIFT)
#define GPIO_BB_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_BB_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_BB_SCR_00_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G2W_SHIFT)
#define GPIO_BB_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_BB_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_BB_SCR_00_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G1W_SHIFT)
#define GPIO_BB_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_BB_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_BB_SCR_00_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G0W_SHIFT)
#define GPIO_BB_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_BB_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_BB_SCR_00_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G7R_SHIFT)
#define GPIO_BB_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_BB_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_BB_SCR_00_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G6R_SHIFT)
#define GPIO_BB_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_BB_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_BB_SCR_00_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G5R_SHIFT)
#define GPIO_BB_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_BB_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_BB_SCR_00_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G4R_SHIFT)
#define GPIO_BB_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_BB_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_BB_SCR_00_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G3R_SHIFT)
#define GPIO_BB_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_BB_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_BB_SCR_00_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G2R_SHIFT)
#define GPIO_BB_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_BB_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_BB_SCR_00_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G1R_SHIFT)
#define GPIO_BB_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_BB_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_00_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_BB_SCR_00_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_00_0_G0R_SHIFT)
#define GPIO_BB_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_BB_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_BB_SCR_00_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_00_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_00_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register GPIO_BB_VM_01_0
#define GPIO_BB_VM_01_0                 _MK_ADDR_CONST(0x20c8)
#define GPIO_BB_VM_01_0_SECURE                  0x0
#define GPIO_BB_VM_01_0_SCR                     GPIO_CTL2_VM_SCR_0
#define GPIO_BB_VM_01_0_WORD_COUNT                      0x1
#define GPIO_BB_VM_01_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_01_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_01_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_BB_VM_01_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_VM_01_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM1_SHIFT)
#define GPIO_BB_VM_01_0_VM1_RANGE                       1:0
#define GPIO_BB_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_BB_VM_01_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM2_SHIFT)
#define GPIO_BB_VM_01_0_VM2_RANGE                       3:2
#define GPIO_BB_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_BB_VM_01_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM3_SHIFT)
#define GPIO_BB_VM_01_0_VM3_RANGE                       5:4
#define GPIO_BB_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_BB_VM_01_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM4_SHIFT)
#define GPIO_BB_VM_01_0_VM4_RANGE                       7:6
#define GPIO_BB_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_BB_VM_01_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM5_SHIFT)
#define GPIO_BB_VM_01_0_VM5_RANGE                       9:8
#define GPIO_BB_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_BB_VM_01_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM6_SHIFT)
#define GPIO_BB_VM_01_0_VM6_RANGE                       11:10
#define GPIO_BB_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_BB_VM_01_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM7_SHIFT)
#define GPIO_BB_VM_01_0_VM7_RANGE                       13:12
#define GPIO_BB_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_BB_VM_01_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_BB_VM_01_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_VM_01_0_VM8_SHIFT)
#define GPIO_BB_VM_01_0_VM8_RANGE                       15:14
#define GPIO_BB_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_BB_VM_01_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_VM_01_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_VM_01_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_SCR_01_0
#define GPIO_BB_SCR_01_0                        _MK_ADDR_CONST(0x20cc)
#define GPIO_BB_SCR_01_0_SECURE                         0x0
#define GPIO_BB_SCR_01_0_SCR                    0
#define GPIO_BB_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_BB_SCR_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_01_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_BB_SCR_01_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_BB_SCR_01_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_BB_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_BB_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_BB_SCR_01_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_BB_SCR_01_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_BB_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_BB_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_BB_SCR_01_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_BB_SCR_01_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_BB_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_BB_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_BB_SCR_01_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_BB_SCR_01_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_BB_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_BB_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_BB_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_BB_SCR_01_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_BB_SCR_01_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_BB_SCR_01_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR7_SHIFT)
#define GPIO_BB_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_BB_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_BB_SCR_01_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR6_SHIFT)
#define GPIO_BB_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_BB_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_BB_SCR_01_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR5_SHIFT)
#define GPIO_BB_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_BB_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_BB_SCR_01_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR4_SHIFT)
#define GPIO_BB_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_BB_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_BB_SCR_01_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR3_SHIFT)
#define GPIO_BB_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_BB_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_BB_SCR_01_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR2_SHIFT)
#define GPIO_BB_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_BB_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_BB_SCR_01_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR1_SHIFT)
#define GPIO_BB_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_BB_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_BB_SCR_01_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_PR0_SHIFT)
#define GPIO_BB_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_BB_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_BB_SCR_01_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G7W_SHIFT)
#define GPIO_BB_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_BB_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_BB_SCR_01_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G6W_SHIFT)
#define GPIO_BB_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_BB_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_BB_SCR_01_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G5W_SHIFT)
#define GPIO_BB_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_BB_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_BB_SCR_01_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G4W_SHIFT)
#define GPIO_BB_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_BB_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_BB_SCR_01_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G3W_SHIFT)
#define GPIO_BB_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_BB_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_BB_SCR_01_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G2W_SHIFT)
#define GPIO_BB_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_BB_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_BB_SCR_01_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G1W_SHIFT)
#define GPIO_BB_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_BB_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_BB_SCR_01_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G0W_SHIFT)
#define GPIO_BB_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_BB_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_BB_SCR_01_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G7R_SHIFT)
#define GPIO_BB_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_BB_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_BB_SCR_01_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G6R_SHIFT)
#define GPIO_BB_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_BB_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_BB_SCR_01_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G5R_SHIFT)
#define GPIO_BB_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_BB_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_BB_SCR_01_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G4R_SHIFT)
#define GPIO_BB_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_BB_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_BB_SCR_01_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G3R_SHIFT)
#define GPIO_BB_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_BB_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_BB_SCR_01_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G2R_SHIFT)
#define GPIO_BB_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_BB_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_BB_SCR_01_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G1R_SHIFT)
#define GPIO_BB_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_BB_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_BB_SCR_01_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_BB_SCR_01_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_SCR_01_0_G0R_SHIFT)
#define GPIO_BB_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_BB_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_BB_SCR_01_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_SCR_01_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_SCR_01_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 8400 [0x20d0]

// Reserved address 8404 [0x20d4]

// Reserved address 8408 [0x20d8]

// Reserved address 8412 [0x20dc]

// Reserved address 8416 [0x20e0]

// Reserved address 8420 [0x20e4]

// Reserved address 8424 [0x20e8]

// Reserved address 8428 [0x20ec]

// Reserved address 8432 [0x20f0]

// Reserved address 8436 [0x20f4]

// Reserved address 8440 [0x20f8]

// Reserved address 8444 [0x20fc]

// Register GPIO_CTL2_VM_SCR_0
#define GPIO_CTL2_VM_SCR_0                      _MK_ADDR_CONST(0x2800)
#define GPIO_CTL2_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL2_VM_SCR_0_SCR                  0
#define GPIO_CTL2_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL2_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL2_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL2_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL2_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL2_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL2_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL2_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL2_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL2_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL2_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL2_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL2_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL2_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL2_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL2_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL2_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL2_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL2_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL2_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL2_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL2_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL2_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL2_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL2_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL2_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL2_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL2_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL2_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL2_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL2_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL2_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL2_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL2_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL2_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL2_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL2_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL2_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL2_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL2_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL2_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL2_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL2_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL2_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL2_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL2_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL2_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL2_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL2_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL2_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL2_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL2_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x2804)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x2808)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL2_SCR_0
#define GPIO_CTL2_SCR_0                 _MK_ADDR_CONST(0x280c)
#define GPIO_CTL2_SCR_0_SECURE                  0x0
#define GPIO_CTL2_SCR_0_SCR                     0
#define GPIO_CTL2_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL2_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL2_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL2_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL2_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL2_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL2_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL2_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL2_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL2_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL2_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL2_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL2_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL2_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL2_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL2_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL2_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL2_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL2_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL2_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL2_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL2_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL2_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL2_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL2_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL2_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL2_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL2_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL2_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL2_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL2_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL2_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL2_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL2_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL2_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL2_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL2_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL2_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL2_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL2_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL2_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL2_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL2_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL2_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL2_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL2_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL2_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL2_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL2_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL2_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL2_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL2_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL2_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL2_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL2_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL2_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL2_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL2_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL2_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL2_ICG_EN_OVERRIDE_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x2810)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL2_SPARE_0
#define GPIO_CTL2_SPARE_0                       _MK_ADDR_CONST(0x2814)
#define GPIO_CTL2_SPARE_0_SECURE                        0x0
#define GPIO_CTL2_SPARE_0_SCR                   0
#define GPIO_CTL2_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL2_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL2_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL2_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL2_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL2_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_00_0
#define GPIO_B_VM_00_0                  _MK_ADDR_CONST(0x3000)
#define GPIO_B_VM_00_0_SECURE                   0x0
#define GPIO_B_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_00_0_WORD_COUNT                       0x1
#define GPIO_B_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM1_SHIFT)
#define GPIO_B_VM_00_0_VM1_RANGE                        1:0
#define GPIO_B_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM2_SHIFT)
#define GPIO_B_VM_00_0_VM2_RANGE                        3:2
#define GPIO_B_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM3_SHIFT)
#define GPIO_B_VM_00_0_VM3_RANGE                        5:4
#define GPIO_B_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM4_SHIFT)
#define GPIO_B_VM_00_0_VM4_RANGE                        7:6
#define GPIO_B_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM5_SHIFT)
#define GPIO_B_VM_00_0_VM5_RANGE                        9:8
#define GPIO_B_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM6_SHIFT)
#define GPIO_B_VM_00_0_VM6_RANGE                        11:10
#define GPIO_B_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM7_SHIFT)
#define GPIO_B_VM_00_0_VM7_RANGE                        13:12
#define GPIO_B_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM8_SHIFT)
#define GPIO_B_VM_00_0_VM8_RANGE                        15:14
#define GPIO_B_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_00_0
#define GPIO_B_SCR_00_0                 _MK_ADDR_CONST(0x3004)
#define GPIO_B_SCR_00_0_SECURE                  0x0
#define GPIO_B_SCR_00_0_SCR                     0
#define GPIO_B_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR7_SHIFT)
#define GPIO_B_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR6_SHIFT)
#define GPIO_B_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR5_SHIFT)
#define GPIO_B_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR4_SHIFT)
#define GPIO_B_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR3_SHIFT)
#define GPIO_B_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR2_SHIFT)
#define GPIO_B_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR1_SHIFT)
#define GPIO_B_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR0_SHIFT)
#define GPIO_B_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7W_SHIFT)
#define GPIO_B_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6W_SHIFT)
#define GPIO_B_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5W_SHIFT)
#define GPIO_B_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4W_SHIFT)
#define GPIO_B_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3W_SHIFT)
#define GPIO_B_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2W_SHIFT)
#define GPIO_B_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1W_SHIFT)
#define GPIO_B_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0W_SHIFT)
#define GPIO_B_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7R_SHIFT)
#define GPIO_B_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6R_SHIFT)
#define GPIO_B_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5R_SHIFT)
#define GPIO_B_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4R_SHIFT)
#define GPIO_B_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3R_SHIFT)
#define GPIO_B_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2R_SHIFT)
#define GPIO_B_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1R_SHIFT)
#define GPIO_B_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0R_SHIFT)
#define GPIO_B_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_01_0
#define GPIO_B_VM_01_0                  _MK_ADDR_CONST(0x3008)
#define GPIO_B_VM_01_0_SECURE                   0x0
#define GPIO_B_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_01_0_WORD_COUNT                       0x1
#define GPIO_B_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM1_SHIFT)
#define GPIO_B_VM_01_0_VM1_RANGE                        1:0
#define GPIO_B_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM2_SHIFT)
#define GPIO_B_VM_01_0_VM2_RANGE                        3:2
#define GPIO_B_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM3_SHIFT)
#define GPIO_B_VM_01_0_VM3_RANGE                        5:4
#define GPIO_B_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM4_SHIFT)
#define GPIO_B_VM_01_0_VM4_RANGE                        7:6
#define GPIO_B_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM5_SHIFT)
#define GPIO_B_VM_01_0_VM5_RANGE                        9:8
#define GPIO_B_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM6_SHIFT)
#define GPIO_B_VM_01_0_VM6_RANGE                        11:10
#define GPIO_B_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM7_SHIFT)
#define GPIO_B_VM_01_0_VM7_RANGE                        13:12
#define GPIO_B_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM8_SHIFT)
#define GPIO_B_VM_01_0_VM8_RANGE                        15:14
#define GPIO_B_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_01_0
#define GPIO_B_SCR_01_0                 _MK_ADDR_CONST(0x300c)
#define GPIO_B_SCR_01_0_SECURE                  0x0
#define GPIO_B_SCR_01_0_SCR                     0
#define GPIO_B_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR7_SHIFT)
#define GPIO_B_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR6_SHIFT)
#define GPIO_B_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR5_SHIFT)
#define GPIO_B_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR4_SHIFT)
#define GPIO_B_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR3_SHIFT)
#define GPIO_B_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR2_SHIFT)
#define GPIO_B_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR1_SHIFT)
#define GPIO_B_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR0_SHIFT)
#define GPIO_B_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G7W_SHIFT)
#define GPIO_B_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G6W_SHIFT)
#define GPIO_B_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G5W_SHIFT)
#define GPIO_B_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G4W_SHIFT)
#define GPIO_B_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G3W_SHIFT)
#define GPIO_B_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G2W_SHIFT)
#define GPIO_B_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G1W_SHIFT)
#define GPIO_B_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G0W_SHIFT)
#define GPIO_B_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G7R_SHIFT)
#define GPIO_B_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G6R_SHIFT)
#define GPIO_B_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G5R_SHIFT)
#define GPIO_B_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G4R_SHIFT)
#define GPIO_B_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G3R_SHIFT)
#define GPIO_B_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G2R_SHIFT)
#define GPIO_B_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G1R_SHIFT)
#define GPIO_B_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G0R_SHIFT)
#define GPIO_B_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_02_0
#define GPIO_B_VM_02_0                  _MK_ADDR_CONST(0x3010)
#define GPIO_B_VM_02_0_SECURE                   0x0
#define GPIO_B_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_02_0_WORD_COUNT                       0x1
#define GPIO_B_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM1_SHIFT)
#define GPIO_B_VM_02_0_VM1_RANGE                        1:0
#define GPIO_B_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM2_SHIFT)
#define GPIO_B_VM_02_0_VM2_RANGE                        3:2
#define GPIO_B_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM3_SHIFT)
#define GPIO_B_VM_02_0_VM3_RANGE                        5:4
#define GPIO_B_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM4_SHIFT)
#define GPIO_B_VM_02_0_VM4_RANGE                        7:6
#define GPIO_B_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM5_SHIFT)
#define GPIO_B_VM_02_0_VM5_RANGE                        9:8
#define GPIO_B_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM6_SHIFT)
#define GPIO_B_VM_02_0_VM6_RANGE                        11:10
#define GPIO_B_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM7_SHIFT)
#define GPIO_B_VM_02_0_VM7_RANGE                        13:12
#define GPIO_B_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_02_0_VM8_SHIFT)
#define GPIO_B_VM_02_0_VM8_RANGE                        15:14
#define GPIO_B_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_02_0
#define GPIO_B_SCR_02_0                 _MK_ADDR_CONST(0x3014)
#define GPIO_B_SCR_02_0_SECURE                  0x0
#define GPIO_B_SCR_02_0_SCR                     0
#define GPIO_B_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR7_SHIFT)
#define GPIO_B_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR6_SHIFT)
#define GPIO_B_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR5_SHIFT)
#define GPIO_B_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR4_SHIFT)
#define GPIO_B_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR3_SHIFT)
#define GPIO_B_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR2_SHIFT)
#define GPIO_B_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR1_SHIFT)
#define GPIO_B_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_PR0_SHIFT)
#define GPIO_B_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G7W_SHIFT)
#define GPIO_B_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G6W_SHIFT)
#define GPIO_B_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G5W_SHIFT)
#define GPIO_B_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G4W_SHIFT)
#define GPIO_B_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G3W_SHIFT)
#define GPIO_B_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G2W_SHIFT)
#define GPIO_B_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G1W_SHIFT)
#define GPIO_B_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G0W_SHIFT)
#define GPIO_B_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G7R_SHIFT)
#define GPIO_B_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G6R_SHIFT)
#define GPIO_B_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G5R_SHIFT)
#define GPIO_B_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G4R_SHIFT)
#define GPIO_B_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G3R_SHIFT)
#define GPIO_B_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G2R_SHIFT)
#define GPIO_B_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G1R_SHIFT)
#define GPIO_B_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_02_0_G0R_SHIFT)
#define GPIO_B_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_03_0
#define GPIO_B_VM_03_0                  _MK_ADDR_CONST(0x3018)
#define GPIO_B_VM_03_0_SECURE                   0x0
#define GPIO_B_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_03_0_WORD_COUNT                       0x1
#define GPIO_B_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM1_SHIFT)
#define GPIO_B_VM_03_0_VM1_RANGE                        1:0
#define GPIO_B_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM2_SHIFT)
#define GPIO_B_VM_03_0_VM2_RANGE                        3:2
#define GPIO_B_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM3_SHIFT)
#define GPIO_B_VM_03_0_VM3_RANGE                        5:4
#define GPIO_B_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM4_SHIFT)
#define GPIO_B_VM_03_0_VM4_RANGE                        7:6
#define GPIO_B_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM5_SHIFT)
#define GPIO_B_VM_03_0_VM5_RANGE                        9:8
#define GPIO_B_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM6_SHIFT)
#define GPIO_B_VM_03_0_VM6_RANGE                        11:10
#define GPIO_B_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM7_SHIFT)
#define GPIO_B_VM_03_0_VM7_RANGE                        13:12
#define GPIO_B_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_03_0_VM8_SHIFT)
#define GPIO_B_VM_03_0_VM8_RANGE                        15:14
#define GPIO_B_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_03_0
#define GPIO_B_SCR_03_0                 _MK_ADDR_CONST(0x301c)
#define GPIO_B_SCR_03_0_SECURE                  0x0
#define GPIO_B_SCR_03_0_SCR                     0
#define GPIO_B_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR7_SHIFT)
#define GPIO_B_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR6_SHIFT)
#define GPIO_B_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR5_SHIFT)
#define GPIO_B_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR4_SHIFT)
#define GPIO_B_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR3_SHIFT)
#define GPIO_B_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR2_SHIFT)
#define GPIO_B_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR1_SHIFT)
#define GPIO_B_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_PR0_SHIFT)
#define GPIO_B_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G7W_SHIFT)
#define GPIO_B_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G6W_SHIFT)
#define GPIO_B_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G5W_SHIFT)
#define GPIO_B_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G4W_SHIFT)
#define GPIO_B_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G3W_SHIFT)
#define GPIO_B_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G2W_SHIFT)
#define GPIO_B_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G1W_SHIFT)
#define GPIO_B_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G0W_SHIFT)
#define GPIO_B_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G7R_SHIFT)
#define GPIO_B_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G6R_SHIFT)
#define GPIO_B_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G5R_SHIFT)
#define GPIO_B_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G4R_SHIFT)
#define GPIO_B_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G3R_SHIFT)
#define GPIO_B_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G2R_SHIFT)
#define GPIO_B_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G1R_SHIFT)
#define GPIO_B_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_03_0_G0R_SHIFT)
#define GPIO_B_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_04_0
#define GPIO_B_VM_04_0                  _MK_ADDR_CONST(0x3020)
#define GPIO_B_VM_04_0_SECURE                   0x0
#define GPIO_B_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_04_0_WORD_COUNT                       0x1
#define GPIO_B_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM1_SHIFT)
#define GPIO_B_VM_04_0_VM1_RANGE                        1:0
#define GPIO_B_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM2_SHIFT)
#define GPIO_B_VM_04_0_VM2_RANGE                        3:2
#define GPIO_B_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM3_SHIFT)
#define GPIO_B_VM_04_0_VM3_RANGE                        5:4
#define GPIO_B_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM4_SHIFT)
#define GPIO_B_VM_04_0_VM4_RANGE                        7:6
#define GPIO_B_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM5_SHIFT)
#define GPIO_B_VM_04_0_VM5_RANGE                        9:8
#define GPIO_B_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM6_SHIFT)
#define GPIO_B_VM_04_0_VM6_RANGE                        11:10
#define GPIO_B_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM7_SHIFT)
#define GPIO_B_VM_04_0_VM7_RANGE                        13:12
#define GPIO_B_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_04_0_VM8_SHIFT)
#define GPIO_B_VM_04_0_VM8_RANGE                        15:14
#define GPIO_B_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_04_0
#define GPIO_B_SCR_04_0                 _MK_ADDR_CONST(0x3024)
#define GPIO_B_SCR_04_0_SECURE                  0x0
#define GPIO_B_SCR_04_0_SCR                     0
#define GPIO_B_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR7_SHIFT)
#define GPIO_B_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR6_SHIFT)
#define GPIO_B_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR5_SHIFT)
#define GPIO_B_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR4_SHIFT)
#define GPIO_B_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR3_SHIFT)
#define GPIO_B_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR2_SHIFT)
#define GPIO_B_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR1_SHIFT)
#define GPIO_B_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_PR0_SHIFT)
#define GPIO_B_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G7W_SHIFT)
#define GPIO_B_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G6W_SHIFT)
#define GPIO_B_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G5W_SHIFT)
#define GPIO_B_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G4W_SHIFT)
#define GPIO_B_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G3W_SHIFT)
#define GPIO_B_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G2W_SHIFT)
#define GPIO_B_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G1W_SHIFT)
#define GPIO_B_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G0W_SHIFT)
#define GPIO_B_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G7R_SHIFT)
#define GPIO_B_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G6R_SHIFT)
#define GPIO_B_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G5R_SHIFT)
#define GPIO_B_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G4R_SHIFT)
#define GPIO_B_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G3R_SHIFT)
#define GPIO_B_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G2R_SHIFT)
#define GPIO_B_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G1R_SHIFT)
#define GPIO_B_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_04_0_G0R_SHIFT)
#define GPIO_B_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_05_0
#define GPIO_B_VM_05_0                  _MK_ADDR_CONST(0x3028)
#define GPIO_B_VM_05_0_SECURE                   0x0
#define GPIO_B_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_05_0_WORD_COUNT                       0x1
#define GPIO_B_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM1_SHIFT)
#define GPIO_B_VM_05_0_VM1_RANGE                        1:0
#define GPIO_B_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM2_SHIFT)
#define GPIO_B_VM_05_0_VM2_RANGE                        3:2
#define GPIO_B_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM3_SHIFT)
#define GPIO_B_VM_05_0_VM3_RANGE                        5:4
#define GPIO_B_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM4_SHIFT)
#define GPIO_B_VM_05_0_VM4_RANGE                        7:6
#define GPIO_B_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM5_SHIFT)
#define GPIO_B_VM_05_0_VM5_RANGE                        9:8
#define GPIO_B_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM6_SHIFT)
#define GPIO_B_VM_05_0_VM6_RANGE                        11:10
#define GPIO_B_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM7_SHIFT)
#define GPIO_B_VM_05_0_VM7_RANGE                        13:12
#define GPIO_B_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_05_0_VM8_SHIFT)
#define GPIO_B_VM_05_0_VM8_RANGE                        15:14
#define GPIO_B_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_05_0
#define GPIO_B_SCR_05_0                 _MK_ADDR_CONST(0x302c)
#define GPIO_B_SCR_05_0_SECURE                  0x0
#define GPIO_B_SCR_05_0_SCR                     0
#define GPIO_B_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR7_SHIFT)
#define GPIO_B_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR6_SHIFT)
#define GPIO_B_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR5_SHIFT)
#define GPIO_B_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR4_SHIFT)
#define GPIO_B_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR3_SHIFT)
#define GPIO_B_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR2_SHIFT)
#define GPIO_B_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR1_SHIFT)
#define GPIO_B_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_PR0_SHIFT)
#define GPIO_B_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G7W_SHIFT)
#define GPIO_B_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G6W_SHIFT)
#define GPIO_B_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G5W_SHIFT)
#define GPIO_B_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G4W_SHIFT)
#define GPIO_B_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G3W_SHIFT)
#define GPIO_B_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G2W_SHIFT)
#define GPIO_B_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G1W_SHIFT)
#define GPIO_B_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G0W_SHIFT)
#define GPIO_B_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G7R_SHIFT)
#define GPIO_B_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G6R_SHIFT)
#define GPIO_B_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G5R_SHIFT)
#define GPIO_B_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G4R_SHIFT)
#define GPIO_B_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G3R_SHIFT)
#define GPIO_B_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G2R_SHIFT)
#define GPIO_B_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G1R_SHIFT)
#define GPIO_B_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_05_0_G0R_SHIFT)
#define GPIO_B_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_B_VM_06_0
#define GPIO_B_VM_06_0                  _MK_ADDR_CONST(0x3030)
#define GPIO_B_VM_06_0_SECURE                   0x0
#define GPIO_B_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_B_VM_06_0_WORD_COUNT                       0x1
#define GPIO_B_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM1_SHIFT)
#define GPIO_B_VM_06_0_VM1_RANGE                        1:0
#define GPIO_B_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM2_SHIFT)
#define GPIO_B_VM_06_0_VM2_RANGE                        3:2
#define GPIO_B_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM3_SHIFT)
#define GPIO_B_VM_06_0_VM3_RANGE                        5:4
#define GPIO_B_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM4_SHIFT)
#define GPIO_B_VM_06_0_VM4_RANGE                        7:6
#define GPIO_B_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM5_SHIFT)
#define GPIO_B_VM_06_0_VM5_RANGE                        9:8
#define GPIO_B_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM6_SHIFT)
#define GPIO_B_VM_06_0_VM6_RANGE                        11:10
#define GPIO_B_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM7_SHIFT)
#define GPIO_B_VM_06_0_VM7_RANGE                        13:12
#define GPIO_B_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_B_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_06_0_VM8_SHIFT)
#define GPIO_B_VM_06_0_VM8_RANGE                        15:14
#define GPIO_B_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_SCR_06_0
#define GPIO_B_SCR_06_0                 _MK_ADDR_CONST(0x3034)
#define GPIO_B_SCR_06_0_SECURE                  0x0
#define GPIO_B_SCR_06_0_SCR                     0
#define GPIO_B_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR7_SHIFT)
#define GPIO_B_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR6_SHIFT)
#define GPIO_B_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR5_SHIFT)
#define GPIO_B_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR4_SHIFT)
#define GPIO_B_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR3_SHIFT)
#define GPIO_B_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR2_SHIFT)
#define GPIO_B_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR1_SHIFT)
#define GPIO_B_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_PR0_SHIFT)
#define GPIO_B_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G7W_SHIFT)
#define GPIO_B_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G6W_SHIFT)
#define GPIO_B_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G5W_SHIFT)
#define GPIO_B_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G4W_SHIFT)
#define GPIO_B_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G3W_SHIFT)
#define GPIO_B_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G2W_SHIFT)
#define GPIO_B_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G1W_SHIFT)
#define GPIO_B_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G0W_SHIFT)
#define GPIO_B_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G7R_SHIFT)
#define GPIO_B_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G6R_SHIFT)
#define GPIO_B_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G5R_SHIFT)
#define GPIO_B_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G4R_SHIFT)
#define GPIO_B_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G3R_SHIFT)
#define GPIO_B_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G2R_SHIFT)
#define GPIO_B_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G1R_SHIFT)
#define GPIO_B_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_B_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_06_0_G0R_SHIFT)
#define GPIO_B_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 12344 [0x3038]

// Reserved address 12348 [0x303c]

// Register GPIO_C_VM_00_0
#define GPIO_C_VM_00_0                  _MK_ADDR_CONST(0x3040)
#define GPIO_C_VM_00_0_SECURE                   0x0
#define GPIO_C_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_00_0_WORD_COUNT                       0x1
#define GPIO_C_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM1_SHIFT)
#define GPIO_C_VM_00_0_VM1_RANGE                        1:0
#define GPIO_C_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM2_SHIFT)
#define GPIO_C_VM_00_0_VM2_RANGE                        3:2
#define GPIO_C_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM3_SHIFT)
#define GPIO_C_VM_00_0_VM3_RANGE                        5:4
#define GPIO_C_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM4_SHIFT)
#define GPIO_C_VM_00_0_VM4_RANGE                        7:6
#define GPIO_C_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM5_SHIFT)
#define GPIO_C_VM_00_0_VM5_RANGE                        9:8
#define GPIO_C_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM6_SHIFT)
#define GPIO_C_VM_00_0_VM6_RANGE                        11:10
#define GPIO_C_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM7_SHIFT)
#define GPIO_C_VM_00_0_VM7_RANGE                        13:12
#define GPIO_C_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM8_SHIFT)
#define GPIO_C_VM_00_0_VM8_RANGE                        15:14
#define GPIO_C_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_00_0
#define GPIO_C_SCR_00_0                 _MK_ADDR_CONST(0x3044)
#define GPIO_C_SCR_00_0_SECURE                  0x0
#define GPIO_C_SCR_00_0_SCR                     0
#define GPIO_C_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR7_SHIFT)
#define GPIO_C_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR6_SHIFT)
#define GPIO_C_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR5_SHIFT)
#define GPIO_C_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR4_SHIFT)
#define GPIO_C_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR3_SHIFT)
#define GPIO_C_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR2_SHIFT)
#define GPIO_C_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR1_SHIFT)
#define GPIO_C_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR0_SHIFT)
#define GPIO_C_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7W_SHIFT)
#define GPIO_C_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6W_SHIFT)
#define GPIO_C_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5W_SHIFT)
#define GPIO_C_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4W_SHIFT)
#define GPIO_C_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3W_SHIFT)
#define GPIO_C_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2W_SHIFT)
#define GPIO_C_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1W_SHIFT)
#define GPIO_C_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0W_SHIFT)
#define GPIO_C_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7R_SHIFT)
#define GPIO_C_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6R_SHIFT)
#define GPIO_C_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5R_SHIFT)
#define GPIO_C_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4R_SHIFT)
#define GPIO_C_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3R_SHIFT)
#define GPIO_C_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2R_SHIFT)
#define GPIO_C_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1R_SHIFT)
#define GPIO_C_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0R_SHIFT)
#define GPIO_C_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_01_0
#define GPIO_C_VM_01_0                  _MK_ADDR_CONST(0x3048)
#define GPIO_C_VM_01_0_SECURE                   0x0
#define GPIO_C_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_01_0_WORD_COUNT                       0x1
#define GPIO_C_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM1_SHIFT)
#define GPIO_C_VM_01_0_VM1_RANGE                        1:0
#define GPIO_C_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM2_SHIFT)
#define GPIO_C_VM_01_0_VM2_RANGE                        3:2
#define GPIO_C_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM3_SHIFT)
#define GPIO_C_VM_01_0_VM3_RANGE                        5:4
#define GPIO_C_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM4_SHIFT)
#define GPIO_C_VM_01_0_VM4_RANGE                        7:6
#define GPIO_C_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM5_SHIFT)
#define GPIO_C_VM_01_0_VM5_RANGE                        9:8
#define GPIO_C_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM6_SHIFT)
#define GPIO_C_VM_01_0_VM6_RANGE                        11:10
#define GPIO_C_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM7_SHIFT)
#define GPIO_C_VM_01_0_VM7_RANGE                        13:12
#define GPIO_C_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM8_SHIFT)
#define GPIO_C_VM_01_0_VM8_RANGE                        15:14
#define GPIO_C_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_01_0
#define GPIO_C_SCR_01_0                 _MK_ADDR_CONST(0x304c)
#define GPIO_C_SCR_01_0_SECURE                  0x0
#define GPIO_C_SCR_01_0_SCR                     0
#define GPIO_C_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR7_SHIFT)
#define GPIO_C_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR6_SHIFT)
#define GPIO_C_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR5_SHIFT)
#define GPIO_C_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR4_SHIFT)
#define GPIO_C_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR3_SHIFT)
#define GPIO_C_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR2_SHIFT)
#define GPIO_C_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR1_SHIFT)
#define GPIO_C_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR0_SHIFT)
#define GPIO_C_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7W_SHIFT)
#define GPIO_C_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6W_SHIFT)
#define GPIO_C_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5W_SHIFT)
#define GPIO_C_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4W_SHIFT)
#define GPIO_C_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3W_SHIFT)
#define GPIO_C_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2W_SHIFT)
#define GPIO_C_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1W_SHIFT)
#define GPIO_C_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0W_SHIFT)
#define GPIO_C_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7R_SHIFT)
#define GPIO_C_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6R_SHIFT)
#define GPIO_C_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5R_SHIFT)
#define GPIO_C_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4R_SHIFT)
#define GPIO_C_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3R_SHIFT)
#define GPIO_C_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2R_SHIFT)
#define GPIO_C_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1R_SHIFT)
#define GPIO_C_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0R_SHIFT)
#define GPIO_C_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_02_0
#define GPIO_C_VM_02_0                  _MK_ADDR_CONST(0x3050)
#define GPIO_C_VM_02_0_SECURE                   0x0
#define GPIO_C_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_02_0_WORD_COUNT                       0x1
#define GPIO_C_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM1_SHIFT)
#define GPIO_C_VM_02_0_VM1_RANGE                        1:0
#define GPIO_C_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM2_SHIFT)
#define GPIO_C_VM_02_0_VM2_RANGE                        3:2
#define GPIO_C_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM3_SHIFT)
#define GPIO_C_VM_02_0_VM3_RANGE                        5:4
#define GPIO_C_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM4_SHIFT)
#define GPIO_C_VM_02_0_VM4_RANGE                        7:6
#define GPIO_C_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM5_SHIFT)
#define GPIO_C_VM_02_0_VM5_RANGE                        9:8
#define GPIO_C_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM6_SHIFT)
#define GPIO_C_VM_02_0_VM6_RANGE                        11:10
#define GPIO_C_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM7_SHIFT)
#define GPIO_C_VM_02_0_VM7_RANGE                        13:12
#define GPIO_C_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM8_SHIFT)
#define GPIO_C_VM_02_0_VM8_RANGE                        15:14
#define GPIO_C_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_02_0
#define GPIO_C_SCR_02_0                 _MK_ADDR_CONST(0x3054)
#define GPIO_C_SCR_02_0_SECURE                  0x0
#define GPIO_C_SCR_02_0_SCR                     0
#define GPIO_C_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR7_SHIFT)
#define GPIO_C_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR6_SHIFT)
#define GPIO_C_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR5_SHIFT)
#define GPIO_C_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR4_SHIFT)
#define GPIO_C_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR3_SHIFT)
#define GPIO_C_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR2_SHIFT)
#define GPIO_C_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR1_SHIFT)
#define GPIO_C_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR0_SHIFT)
#define GPIO_C_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7W_SHIFT)
#define GPIO_C_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6W_SHIFT)
#define GPIO_C_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5W_SHIFT)
#define GPIO_C_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4W_SHIFT)
#define GPIO_C_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3W_SHIFT)
#define GPIO_C_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2W_SHIFT)
#define GPIO_C_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1W_SHIFT)
#define GPIO_C_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0W_SHIFT)
#define GPIO_C_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7R_SHIFT)
#define GPIO_C_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6R_SHIFT)
#define GPIO_C_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5R_SHIFT)
#define GPIO_C_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4R_SHIFT)
#define GPIO_C_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3R_SHIFT)
#define GPIO_C_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2R_SHIFT)
#define GPIO_C_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1R_SHIFT)
#define GPIO_C_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0R_SHIFT)
#define GPIO_C_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_03_0
#define GPIO_C_VM_03_0                  _MK_ADDR_CONST(0x3058)
#define GPIO_C_VM_03_0_SECURE                   0x0
#define GPIO_C_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_03_0_WORD_COUNT                       0x1
#define GPIO_C_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM1_SHIFT)
#define GPIO_C_VM_03_0_VM1_RANGE                        1:0
#define GPIO_C_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM2_SHIFT)
#define GPIO_C_VM_03_0_VM2_RANGE                        3:2
#define GPIO_C_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM3_SHIFT)
#define GPIO_C_VM_03_0_VM3_RANGE                        5:4
#define GPIO_C_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM4_SHIFT)
#define GPIO_C_VM_03_0_VM4_RANGE                        7:6
#define GPIO_C_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM5_SHIFT)
#define GPIO_C_VM_03_0_VM5_RANGE                        9:8
#define GPIO_C_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM6_SHIFT)
#define GPIO_C_VM_03_0_VM6_RANGE                        11:10
#define GPIO_C_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM7_SHIFT)
#define GPIO_C_VM_03_0_VM7_RANGE                        13:12
#define GPIO_C_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM8_SHIFT)
#define GPIO_C_VM_03_0_VM8_RANGE                        15:14
#define GPIO_C_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_03_0
#define GPIO_C_SCR_03_0                 _MK_ADDR_CONST(0x305c)
#define GPIO_C_SCR_03_0_SECURE                  0x0
#define GPIO_C_SCR_03_0_SCR                     0
#define GPIO_C_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR7_SHIFT)
#define GPIO_C_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR6_SHIFT)
#define GPIO_C_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR5_SHIFT)
#define GPIO_C_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR4_SHIFT)
#define GPIO_C_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR3_SHIFT)
#define GPIO_C_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR2_SHIFT)
#define GPIO_C_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR1_SHIFT)
#define GPIO_C_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR0_SHIFT)
#define GPIO_C_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7W_SHIFT)
#define GPIO_C_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6W_SHIFT)
#define GPIO_C_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5W_SHIFT)
#define GPIO_C_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4W_SHIFT)
#define GPIO_C_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3W_SHIFT)
#define GPIO_C_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2W_SHIFT)
#define GPIO_C_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1W_SHIFT)
#define GPIO_C_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0W_SHIFT)
#define GPIO_C_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7R_SHIFT)
#define GPIO_C_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6R_SHIFT)
#define GPIO_C_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5R_SHIFT)
#define GPIO_C_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4R_SHIFT)
#define GPIO_C_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3R_SHIFT)
#define GPIO_C_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2R_SHIFT)
#define GPIO_C_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1R_SHIFT)
#define GPIO_C_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0R_SHIFT)
#define GPIO_C_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_04_0
#define GPIO_C_VM_04_0                  _MK_ADDR_CONST(0x3060)
#define GPIO_C_VM_04_0_SECURE                   0x0
#define GPIO_C_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_04_0_WORD_COUNT                       0x1
#define GPIO_C_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM1_SHIFT)
#define GPIO_C_VM_04_0_VM1_RANGE                        1:0
#define GPIO_C_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM2_SHIFT)
#define GPIO_C_VM_04_0_VM2_RANGE                        3:2
#define GPIO_C_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM3_SHIFT)
#define GPIO_C_VM_04_0_VM3_RANGE                        5:4
#define GPIO_C_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM4_SHIFT)
#define GPIO_C_VM_04_0_VM4_RANGE                        7:6
#define GPIO_C_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM5_SHIFT)
#define GPIO_C_VM_04_0_VM5_RANGE                        9:8
#define GPIO_C_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM6_SHIFT)
#define GPIO_C_VM_04_0_VM6_RANGE                        11:10
#define GPIO_C_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM7_SHIFT)
#define GPIO_C_VM_04_0_VM7_RANGE                        13:12
#define GPIO_C_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM8_SHIFT)
#define GPIO_C_VM_04_0_VM8_RANGE                        15:14
#define GPIO_C_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_04_0
#define GPIO_C_SCR_04_0                 _MK_ADDR_CONST(0x3064)
#define GPIO_C_SCR_04_0_SECURE                  0x0
#define GPIO_C_SCR_04_0_SCR                     0
#define GPIO_C_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR7_SHIFT)
#define GPIO_C_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR6_SHIFT)
#define GPIO_C_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR5_SHIFT)
#define GPIO_C_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR4_SHIFT)
#define GPIO_C_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR3_SHIFT)
#define GPIO_C_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR2_SHIFT)
#define GPIO_C_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR1_SHIFT)
#define GPIO_C_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR0_SHIFT)
#define GPIO_C_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7W_SHIFT)
#define GPIO_C_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6W_SHIFT)
#define GPIO_C_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5W_SHIFT)
#define GPIO_C_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4W_SHIFT)
#define GPIO_C_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3W_SHIFT)
#define GPIO_C_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2W_SHIFT)
#define GPIO_C_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1W_SHIFT)
#define GPIO_C_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0W_SHIFT)
#define GPIO_C_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7R_SHIFT)
#define GPIO_C_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6R_SHIFT)
#define GPIO_C_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5R_SHIFT)
#define GPIO_C_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4R_SHIFT)
#define GPIO_C_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3R_SHIFT)
#define GPIO_C_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2R_SHIFT)
#define GPIO_C_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1R_SHIFT)
#define GPIO_C_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0R_SHIFT)
#define GPIO_C_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_05_0
#define GPIO_C_VM_05_0                  _MK_ADDR_CONST(0x3068)
#define GPIO_C_VM_05_0_SECURE                   0x0
#define GPIO_C_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_05_0_WORD_COUNT                       0x1
#define GPIO_C_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM1_SHIFT)
#define GPIO_C_VM_05_0_VM1_RANGE                        1:0
#define GPIO_C_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM2_SHIFT)
#define GPIO_C_VM_05_0_VM2_RANGE                        3:2
#define GPIO_C_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM3_SHIFT)
#define GPIO_C_VM_05_0_VM3_RANGE                        5:4
#define GPIO_C_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM4_SHIFT)
#define GPIO_C_VM_05_0_VM4_RANGE                        7:6
#define GPIO_C_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM5_SHIFT)
#define GPIO_C_VM_05_0_VM5_RANGE                        9:8
#define GPIO_C_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM6_SHIFT)
#define GPIO_C_VM_05_0_VM6_RANGE                        11:10
#define GPIO_C_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM7_SHIFT)
#define GPIO_C_VM_05_0_VM7_RANGE                        13:12
#define GPIO_C_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM8_SHIFT)
#define GPIO_C_VM_05_0_VM8_RANGE                        15:14
#define GPIO_C_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_05_0
#define GPIO_C_SCR_05_0                 _MK_ADDR_CONST(0x306c)
#define GPIO_C_SCR_05_0_SECURE                  0x0
#define GPIO_C_SCR_05_0_SCR                     0
#define GPIO_C_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR7_SHIFT)
#define GPIO_C_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR6_SHIFT)
#define GPIO_C_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR5_SHIFT)
#define GPIO_C_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR4_SHIFT)
#define GPIO_C_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR3_SHIFT)
#define GPIO_C_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR2_SHIFT)
#define GPIO_C_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR1_SHIFT)
#define GPIO_C_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR0_SHIFT)
#define GPIO_C_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7W_SHIFT)
#define GPIO_C_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6W_SHIFT)
#define GPIO_C_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5W_SHIFT)
#define GPIO_C_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4W_SHIFT)
#define GPIO_C_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3W_SHIFT)
#define GPIO_C_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2W_SHIFT)
#define GPIO_C_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1W_SHIFT)
#define GPIO_C_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0W_SHIFT)
#define GPIO_C_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7R_SHIFT)
#define GPIO_C_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6R_SHIFT)
#define GPIO_C_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5R_SHIFT)
#define GPIO_C_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4R_SHIFT)
#define GPIO_C_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3R_SHIFT)
#define GPIO_C_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2R_SHIFT)
#define GPIO_C_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1R_SHIFT)
#define GPIO_C_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0R_SHIFT)
#define GPIO_C_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_C_VM_06_0
#define GPIO_C_VM_06_0                  _MK_ADDR_CONST(0x3070)
#define GPIO_C_VM_06_0_SECURE                   0x0
#define GPIO_C_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_C_VM_06_0_WORD_COUNT                       0x1
#define GPIO_C_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM1_SHIFT)
#define GPIO_C_VM_06_0_VM1_RANGE                        1:0
#define GPIO_C_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM2_SHIFT)
#define GPIO_C_VM_06_0_VM2_RANGE                        3:2
#define GPIO_C_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM3_SHIFT)
#define GPIO_C_VM_06_0_VM3_RANGE                        5:4
#define GPIO_C_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM4_SHIFT)
#define GPIO_C_VM_06_0_VM4_RANGE                        7:6
#define GPIO_C_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM5_SHIFT)
#define GPIO_C_VM_06_0_VM5_RANGE                        9:8
#define GPIO_C_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM6_SHIFT)
#define GPIO_C_VM_06_0_VM6_RANGE                        11:10
#define GPIO_C_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM7_SHIFT)
#define GPIO_C_VM_06_0_VM7_RANGE                        13:12
#define GPIO_C_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_C_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM8_SHIFT)
#define GPIO_C_VM_06_0_VM8_RANGE                        15:14
#define GPIO_C_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_SCR_06_0
#define GPIO_C_SCR_06_0                 _MK_ADDR_CONST(0x3074)
#define GPIO_C_SCR_06_0_SECURE                  0x0
#define GPIO_C_SCR_06_0_SCR                     0
#define GPIO_C_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR7_SHIFT)
#define GPIO_C_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR6_SHIFT)
#define GPIO_C_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR5_SHIFT)
#define GPIO_C_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR4_SHIFT)
#define GPIO_C_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR3_SHIFT)
#define GPIO_C_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR2_SHIFT)
#define GPIO_C_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR1_SHIFT)
#define GPIO_C_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR0_SHIFT)
#define GPIO_C_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7W_SHIFT)
#define GPIO_C_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6W_SHIFT)
#define GPIO_C_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5W_SHIFT)
#define GPIO_C_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4W_SHIFT)
#define GPIO_C_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3W_SHIFT)
#define GPIO_C_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2W_SHIFT)
#define GPIO_C_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1W_SHIFT)
#define GPIO_C_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0W_SHIFT)
#define GPIO_C_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7R_SHIFT)
#define GPIO_C_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6R_SHIFT)
#define GPIO_C_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5R_SHIFT)
#define GPIO_C_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4R_SHIFT)
#define GPIO_C_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3R_SHIFT)
#define GPIO_C_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2R_SHIFT)
#define GPIO_C_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1R_SHIFT)
#define GPIO_C_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_C_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0R_SHIFT)
#define GPIO_C_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 12408 [0x3078]

// Reserved address 12412 [0x307c]

// Register GPIO_D_VM_00_0
#define GPIO_D_VM_00_0                  _MK_ADDR_CONST(0x3080)
#define GPIO_D_VM_00_0_SECURE                   0x0
#define GPIO_D_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_00_0_WORD_COUNT                       0x1
#define GPIO_D_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM1_SHIFT)
#define GPIO_D_VM_00_0_VM1_RANGE                        1:0
#define GPIO_D_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM2_SHIFT)
#define GPIO_D_VM_00_0_VM2_RANGE                        3:2
#define GPIO_D_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM3_SHIFT)
#define GPIO_D_VM_00_0_VM3_RANGE                        5:4
#define GPIO_D_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM4_SHIFT)
#define GPIO_D_VM_00_0_VM4_RANGE                        7:6
#define GPIO_D_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM5_SHIFT)
#define GPIO_D_VM_00_0_VM5_RANGE                        9:8
#define GPIO_D_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM6_SHIFT)
#define GPIO_D_VM_00_0_VM6_RANGE                        11:10
#define GPIO_D_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM7_SHIFT)
#define GPIO_D_VM_00_0_VM7_RANGE                        13:12
#define GPIO_D_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM8_SHIFT)
#define GPIO_D_VM_00_0_VM8_RANGE                        15:14
#define GPIO_D_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_00_0
#define GPIO_D_SCR_00_0                 _MK_ADDR_CONST(0x3084)
#define GPIO_D_SCR_00_0_SECURE                  0x0
#define GPIO_D_SCR_00_0_SCR                     0
#define GPIO_D_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR7_SHIFT)
#define GPIO_D_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR6_SHIFT)
#define GPIO_D_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR5_SHIFT)
#define GPIO_D_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR4_SHIFT)
#define GPIO_D_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR3_SHIFT)
#define GPIO_D_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR2_SHIFT)
#define GPIO_D_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR1_SHIFT)
#define GPIO_D_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR0_SHIFT)
#define GPIO_D_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7W_SHIFT)
#define GPIO_D_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6W_SHIFT)
#define GPIO_D_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5W_SHIFT)
#define GPIO_D_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4W_SHIFT)
#define GPIO_D_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3W_SHIFT)
#define GPIO_D_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2W_SHIFT)
#define GPIO_D_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1W_SHIFT)
#define GPIO_D_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0W_SHIFT)
#define GPIO_D_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7R_SHIFT)
#define GPIO_D_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6R_SHIFT)
#define GPIO_D_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5R_SHIFT)
#define GPIO_D_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4R_SHIFT)
#define GPIO_D_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3R_SHIFT)
#define GPIO_D_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2R_SHIFT)
#define GPIO_D_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1R_SHIFT)
#define GPIO_D_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0R_SHIFT)
#define GPIO_D_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_D_VM_01_0
#define GPIO_D_VM_01_0                  _MK_ADDR_CONST(0x3088)
#define GPIO_D_VM_01_0_SECURE                   0x0
#define GPIO_D_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_01_0_WORD_COUNT                       0x1
#define GPIO_D_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM1_SHIFT)
#define GPIO_D_VM_01_0_VM1_RANGE                        1:0
#define GPIO_D_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM2_SHIFT)
#define GPIO_D_VM_01_0_VM2_RANGE                        3:2
#define GPIO_D_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM3_SHIFT)
#define GPIO_D_VM_01_0_VM3_RANGE                        5:4
#define GPIO_D_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM4_SHIFT)
#define GPIO_D_VM_01_0_VM4_RANGE                        7:6
#define GPIO_D_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM5_SHIFT)
#define GPIO_D_VM_01_0_VM5_RANGE                        9:8
#define GPIO_D_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM6_SHIFT)
#define GPIO_D_VM_01_0_VM6_RANGE                        11:10
#define GPIO_D_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM7_SHIFT)
#define GPIO_D_VM_01_0_VM7_RANGE                        13:12
#define GPIO_D_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM8_SHIFT)
#define GPIO_D_VM_01_0_VM8_RANGE                        15:14
#define GPIO_D_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_01_0
#define GPIO_D_SCR_01_0                 _MK_ADDR_CONST(0x308c)
#define GPIO_D_SCR_01_0_SECURE                  0x0
#define GPIO_D_SCR_01_0_SCR                     0
#define GPIO_D_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR7_SHIFT)
#define GPIO_D_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR6_SHIFT)
#define GPIO_D_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR5_SHIFT)
#define GPIO_D_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR4_SHIFT)
#define GPIO_D_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR3_SHIFT)
#define GPIO_D_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR2_SHIFT)
#define GPIO_D_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR1_SHIFT)
#define GPIO_D_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR0_SHIFT)
#define GPIO_D_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7W_SHIFT)
#define GPIO_D_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6W_SHIFT)
#define GPIO_D_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5W_SHIFT)
#define GPIO_D_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4W_SHIFT)
#define GPIO_D_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3W_SHIFT)
#define GPIO_D_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2W_SHIFT)
#define GPIO_D_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1W_SHIFT)
#define GPIO_D_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0W_SHIFT)
#define GPIO_D_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7R_SHIFT)
#define GPIO_D_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6R_SHIFT)
#define GPIO_D_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5R_SHIFT)
#define GPIO_D_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4R_SHIFT)
#define GPIO_D_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3R_SHIFT)
#define GPIO_D_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2R_SHIFT)
#define GPIO_D_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1R_SHIFT)
#define GPIO_D_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0R_SHIFT)
#define GPIO_D_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_D_VM_02_0
#define GPIO_D_VM_02_0                  _MK_ADDR_CONST(0x3090)
#define GPIO_D_VM_02_0_SECURE                   0x0
#define GPIO_D_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_02_0_WORD_COUNT                       0x1
#define GPIO_D_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM1_SHIFT)
#define GPIO_D_VM_02_0_VM1_RANGE                        1:0
#define GPIO_D_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM2_SHIFT)
#define GPIO_D_VM_02_0_VM2_RANGE                        3:2
#define GPIO_D_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM3_SHIFT)
#define GPIO_D_VM_02_0_VM3_RANGE                        5:4
#define GPIO_D_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM4_SHIFT)
#define GPIO_D_VM_02_0_VM4_RANGE                        7:6
#define GPIO_D_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM5_SHIFT)
#define GPIO_D_VM_02_0_VM5_RANGE                        9:8
#define GPIO_D_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM6_SHIFT)
#define GPIO_D_VM_02_0_VM6_RANGE                        11:10
#define GPIO_D_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM7_SHIFT)
#define GPIO_D_VM_02_0_VM7_RANGE                        13:12
#define GPIO_D_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM8_SHIFT)
#define GPIO_D_VM_02_0_VM8_RANGE                        15:14
#define GPIO_D_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_02_0
#define GPIO_D_SCR_02_0                 _MK_ADDR_CONST(0x3094)
#define GPIO_D_SCR_02_0_SECURE                  0x0
#define GPIO_D_SCR_02_0_SCR                     0
#define GPIO_D_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR7_SHIFT)
#define GPIO_D_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR6_SHIFT)
#define GPIO_D_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR5_SHIFT)
#define GPIO_D_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR4_SHIFT)
#define GPIO_D_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR3_SHIFT)
#define GPIO_D_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR2_SHIFT)
#define GPIO_D_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR1_SHIFT)
#define GPIO_D_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR0_SHIFT)
#define GPIO_D_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7W_SHIFT)
#define GPIO_D_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6W_SHIFT)
#define GPIO_D_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5W_SHIFT)
#define GPIO_D_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4W_SHIFT)
#define GPIO_D_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3W_SHIFT)
#define GPIO_D_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2W_SHIFT)
#define GPIO_D_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1W_SHIFT)
#define GPIO_D_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0W_SHIFT)
#define GPIO_D_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7R_SHIFT)
#define GPIO_D_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6R_SHIFT)
#define GPIO_D_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5R_SHIFT)
#define GPIO_D_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4R_SHIFT)
#define GPIO_D_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3R_SHIFT)
#define GPIO_D_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2R_SHIFT)
#define GPIO_D_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1R_SHIFT)
#define GPIO_D_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0R_SHIFT)
#define GPIO_D_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_D_VM_03_0
#define GPIO_D_VM_03_0                  _MK_ADDR_CONST(0x3098)
#define GPIO_D_VM_03_0_SECURE                   0x0
#define GPIO_D_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_03_0_WORD_COUNT                       0x1
#define GPIO_D_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM1_SHIFT)
#define GPIO_D_VM_03_0_VM1_RANGE                        1:0
#define GPIO_D_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM2_SHIFT)
#define GPIO_D_VM_03_0_VM2_RANGE                        3:2
#define GPIO_D_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM3_SHIFT)
#define GPIO_D_VM_03_0_VM3_RANGE                        5:4
#define GPIO_D_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM4_SHIFT)
#define GPIO_D_VM_03_0_VM4_RANGE                        7:6
#define GPIO_D_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM5_SHIFT)
#define GPIO_D_VM_03_0_VM5_RANGE                        9:8
#define GPIO_D_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM6_SHIFT)
#define GPIO_D_VM_03_0_VM6_RANGE                        11:10
#define GPIO_D_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM7_SHIFT)
#define GPIO_D_VM_03_0_VM7_RANGE                        13:12
#define GPIO_D_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM8_SHIFT)
#define GPIO_D_VM_03_0_VM8_RANGE                        15:14
#define GPIO_D_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_03_0
#define GPIO_D_SCR_03_0                 _MK_ADDR_CONST(0x309c)
#define GPIO_D_SCR_03_0_SECURE                  0x0
#define GPIO_D_SCR_03_0_SCR                     0
#define GPIO_D_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR7_SHIFT)
#define GPIO_D_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR6_SHIFT)
#define GPIO_D_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR5_SHIFT)
#define GPIO_D_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR4_SHIFT)
#define GPIO_D_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR3_SHIFT)
#define GPIO_D_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR2_SHIFT)
#define GPIO_D_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR1_SHIFT)
#define GPIO_D_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR0_SHIFT)
#define GPIO_D_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7W_SHIFT)
#define GPIO_D_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6W_SHIFT)
#define GPIO_D_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5W_SHIFT)
#define GPIO_D_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4W_SHIFT)
#define GPIO_D_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3W_SHIFT)
#define GPIO_D_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2W_SHIFT)
#define GPIO_D_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1W_SHIFT)
#define GPIO_D_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0W_SHIFT)
#define GPIO_D_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7R_SHIFT)
#define GPIO_D_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6R_SHIFT)
#define GPIO_D_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5R_SHIFT)
#define GPIO_D_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4R_SHIFT)
#define GPIO_D_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3R_SHIFT)
#define GPIO_D_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2R_SHIFT)
#define GPIO_D_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1R_SHIFT)
#define GPIO_D_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0R_SHIFT)
#define GPIO_D_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_D_VM_04_0
#define GPIO_D_VM_04_0                  _MK_ADDR_CONST(0x30a0)
#define GPIO_D_VM_04_0_SECURE                   0x0
#define GPIO_D_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_04_0_WORD_COUNT                       0x1
#define GPIO_D_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM1_SHIFT)
#define GPIO_D_VM_04_0_VM1_RANGE                        1:0
#define GPIO_D_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM2_SHIFT)
#define GPIO_D_VM_04_0_VM2_RANGE                        3:2
#define GPIO_D_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM3_SHIFT)
#define GPIO_D_VM_04_0_VM3_RANGE                        5:4
#define GPIO_D_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM4_SHIFT)
#define GPIO_D_VM_04_0_VM4_RANGE                        7:6
#define GPIO_D_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM5_SHIFT)
#define GPIO_D_VM_04_0_VM5_RANGE                        9:8
#define GPIO_D_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM6_SHIFT)
#define GPIO_D_VM_04_0_VM6_RANGE                        11:10
#define GPIO_D_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM7_SHIFT)
#define GPIO_D_VM_04_0_VM7_RANGE                        13:12
#define GPIO_D_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_04_0_VM8_SHIFT)
#define GPIO_D_VM_04_0_VM8_RANGE                        15:14
#define GPIO_D_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_04_0
#define GPIO_D_SCR_04_0                 _MK_ADDR_CONST(0x30a4)
#define GPIO_D_SCR_04_0_SECURE                  0x0
#define GPIO_D_SCR_04_0_SCR                     0
#define GPIO_D_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR7_SHIFT)
#define GPIO_D_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR6_SHIFT)
#define GPIO_D_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR5_SHIFT)
#define GPIO_D_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR4_SHIFT)
#define GPIO_D_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR3_SHIFT)
#define GPIO_D_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR2_SHIFT)
#define GPIO_D_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR1_SHIFT)
#define GPIO_D_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_PR0_SHIFT)
#define GPIO_D_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G7W_SHIFT)
#define GPIO_D_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G6W_SHIFT)
#define GPIO_D_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G5W_SHIFT)
#define GPIO_D_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G4W_SHIFT)
#define GPIO_D_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G3W_SHIFT)
#define GPIO_D_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G2W_SHIFT)
#define GPIO_D_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G1W_SHIFT)
#define GPIO_D_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G0W_SHIFT)
#define GPIO_D_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G7R_SHIFT)
#define GPIO_D_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G6R_SHIFT)
#define GPIO_D_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G5R_SHIFT)
#define GPIO_D_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G4R_SHIFT)
#define GPIO_D_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G3R_SHIFT)
#define GPIO_D_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G2R_SHIFT)
#define GPIO_D_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G1R_SHIFT)
#define GPIO_D_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_04_0_G0R_SHIFT)
#define GPIO_D_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_D_VM_05_0
#define GPIO_D_VM_05_0                  _MK_ADDR_CONST(0x30a8)
#define GPIO_D_VM_05_0_SECURE                   0x0
#define GPIO_D_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_D_VM_05_0_WORD_COUNT                       0x1
#define GPIO_D_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM1_SHIFT)
#define GPIO_D_VM_05_0_VM1_RANGE                        1:0
#define GPIO_D_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM2_SHIFT)
#define GPIO_D_VM_05_0_VM2_RANGE                        3:2
#define GPIO_D_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM3_SHIFT)
#define GPIO_D_VM_05_0_VM3_RANGE                        5:4
#define GPIO_D_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM4_SHIFT)
#define GPIO_D_VM_05_0_VM4_RANGE                        7:6
#define GPIO_D_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM5_SHIFT)
#define GPIO_D_VM_05_0_VM5_RANGE                        9:8
#define GPIO_D_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM6_SHIFT)
#define GPIO_D_VM_05_0_VM6_RANGE                        11:10
#define GPIO_D_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM7_SHIFT)
#define GPIO_D_VM_05_0_VM7_RANGE                        13:12
#define GPIO_D_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_D_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_05_0_VM8_SHIFT)
#define GPIO_D_VM_05_0_VM8_RANGE                        15:14
#define GPIO_D_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_SCR_05_0
#define GPIO_D_SCR_05_0                 _MK_ADDR_CONST(0x30ac)
#define GPIO_D_SCR_05_0_SECURE                  0x0
#define GPIO_D_SCR_05_0_SCR                     0
#define GPIO_D_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR7_SHIFT)
#define GPIO_D_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR6_SHIFT)
#define GPIO_D_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR5_SHIFT)
#define GPIO_D_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR4_SHIFT)
#define GPIO_D_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR3_SHIFT)
#define GPIO_D_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR2_SHIFT)
#define GPIO_D_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR1_SHIFT)
#define GPIO_D_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_PR0_SHIFT)
#define GPIO_D_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G7W_SHIFT)
#define GPIO_D_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G6W_SHIFT)
#define GPIO_D_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G5W_SHIFT)
#define GPIO_D_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G4W_SHIFT)
#define GPIO_D_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G3W_SHIFT)
#define GPIO_D_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G2W_SHIFT)
#define GPIO_D_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G1W_SHIFT)
#define GPIO_D_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G0W_SHIFT)
#define GPIO_D_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G7R_SHIFT)
#define GPIO_D_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G6R_SHIFT)
#define GPIO_D_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G5R_SHIFT)
#define GPIO_D_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G4R_SHIFT)
#define GPIO_D_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G3R_SHIFT)
#define GPIO_D_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G2R_SHIFT)
#define GPIO_D_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G1R_SHIFT)
#define GPIO_D_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_D_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_05_0_G0R_SHIFT)
#define GPIO_D_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 12464 [0x30b0]

// Reserved address 12468 [0x30b4]

// Reserved address 12472 [0x30b8]

// Reserved address 12476 [0x30bc]

// Register GPIO_CTL3_VM_SCR_0
#define GPIO_CTL3_VM_SCR_0                      _MK_ADDR_CONST(0x3800)
#define GPIO_CTL3_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL3_VM_SCR_0_SCR                  0
#define GPIO_CTL3_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL3_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL3_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL3_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL3_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL3_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL3_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL3_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL3_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL3_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL3_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL3_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL3_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL3_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL3_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL3_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL3_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL3_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL3_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL3_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL3_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL3_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL3_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL3_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL3_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL3_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL3_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL3_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL3_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL3_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL3_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL3_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL3_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL3_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL3_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL3_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL3_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL3_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL3_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL3_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL3_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL3_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL3_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL3_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL3_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL3_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL3_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL3_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL3_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL3_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL3_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL3_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x3804)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x3808)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL3_SCR_0
#define GPIO_CTL3_SCR_0                 _MK_ADDR_CONST(0x380c)
#define GPIO_CTL3_SCR_0_SECURE                  0x0
#define GPIO_CTL3_SCR_0_SCR                     0
#define GPIO_CTL3_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL3_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL3_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL3_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL3_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL3_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL3_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL3_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL3_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL3_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL3_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL3_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL3_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL3_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL3_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL3_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL3_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL3_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL3_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL3_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL3_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL3_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL3_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL3_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL3_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL3_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL3_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL3_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL3_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL3_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL3_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL3_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL3_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL3_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL3_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL3_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL3_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL3_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL3_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL3_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL3_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL3_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL3_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL3_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL3_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL3_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL3_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL3_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL3_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL3_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL3_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL3_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL3_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL3_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL3_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL3_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL3_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL3_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL3_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL3_ICG_EN_OVERRIDE_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x3810)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL3_SPARE_0
#define GPIO_CTL3_SPARE_0                       _MK_ADDR_CONST(0x3814)
#define GPIO_CTL3_SPARE_0_SECURE                        0x0
#define GPIO_CTL3_SPARE_0_SCR                   0
#define GPIO_CTL3_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL3_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL3_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL3_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL3_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL3_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_00_0
#define GPIO_P_VM_00_0                  _MK_ADDR_CONST(0x4000)
#define GPIO_P_VM_00_0_SECURE                   0x0
#define GPIO_P_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_00_0_WORD_COUNT                       0x1
#define GPIO_P_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM1_SHIFT)
#define GPIO_P_VM_00_0_VM1_RANGE                        1:0
#define GPIO_P_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM2_SHIFT)
#define GPIO_P_VM_00_0_VM2_RANGE                        3:2
#define GPIO_P_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM3_SHIFT)
#define GPIO_P_VM_00_0_VM3_RANGE                        5:4
#define GPIO_P_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM4_SHIFT)
#define GPIO_P_VM_00_0_VM4_RANGE                        7:6
#define GPIO_P_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM5_SHIFT)
#define GPIO_P_VM_00_0_VM5_RANGE                        9:8
#define GPIO_P_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM6_SHIFT)
#define GPIO_P_VM_00_0_VM6_RANGE                        11:10
#define GPIO_P_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM7_SHIFT)
#define GPIO_P_VM_00_0_VM7_RANGE                        13:12
#define GPIO_P_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM8_SHIFT)
#define GPIO_P_VM_00_0_VM8_RANGE                        15:14
#define GPIO_P_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_00_0
#define GPIO_P_SCR_00_0                 _MK_ADDR_CONST(0x4004)
#define GPIO_P_SCR_00_0_SECURE                  0x0
#define GPIO_P_SCR_00_0_SCR                     0
#define GPIO_P_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR7_SHIFT)
#define GPIO_P_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR6_SHIFT)
#define GPIO_P_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR5_SHIFT)
#define GPIO_P_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR4_SHIFT)
#define GPIO_P_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR3_SHIFT)
#define GPIO_P_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR2_SHIFT)
#define GPIO_P_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR1_SHIFT)
#define GPIO_P_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR0_SHIFT)
#define GPIO_P_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7W_SHIFT)
#define GPIO_P_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6W_SHIFT)
#define GPIO_P_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5W_SHIFT)
#define GPIO_P_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4W_SHIFT)
#define GPIO_P_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3W_SHIFT)
#define GPIO_P_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2W_SHIFT)
#define GPIO_P_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1W_SHIFT)
#define GPIO_P_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0W_SHIFT)
#define GPIO_P_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7R_SHIFT)
#define GPIO_P_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6R_SHIFT)
#define GPIO_P_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5R_SHIFT)
#define GPIO_P_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4R_SHIFT)
#define GPIO_P_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3R_SHIFT)
#define GPIO_P_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2R_SHIFT)
#define GPIO_P_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1R_SHIFT)
#define GPIO_P_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0R_SHIFT)
#define GPIO_P_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_01_0
#define GPIO_P_VM_01_0                  _MK_ADDR_CONST(0x4008)
#define GPIO_P_VM_01_0_SECURE                   0x0
#define GPIO_P_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_01_0_WORD_COUNT                       0x1
#define GPIO_P_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM1_SHIFT)
#define GPIO_P_VM_01_0_VM1_RANGE                        1:0
#define GPIO_P_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM2_SHIFT)
#define GPIO_P_VM_01_0_VM2_RANGE                        3:2
#define GPIO_P_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM3_SHIFT)
#define GPIO_P_VM_01_0_VM3_RANGE                        5:4
#define GPIO_P_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM4_SHIFT)
#define GPIO_P_VM_01_0_VM4_RANGE                        7:6
#define GPIO_P_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM5_SHIFT)
#define GPIO_P_VM_01_0_VM5_RANGE                        9:8
#define GPIO_P_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM6_SHIFT)
#define GPIO_P_VM_01_0_VM6_RANGE                        11:10
#define GPIO_P_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM7_SHIFT)
#define GPIO_P_VM_01_0_VM7_RANGE                        13:12
#define GPIO_P_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM8_SHIFT)
#define GPIO_P_VM_01_0_VM8_RANGE                        15:14
#define GPIO_P_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_01_0
#define GPIO_P_SCR_01_0                 _MK_ADDR_CONST(0x400c)
#define GPIO_P_SCR_01_0_SECURE                  0x0
#define GPIO_P_SCR_01_0_SCR                     0
#define GPIO_P_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR7_SHIFT)
#define GPIO_P_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR6_SHIFT)
#define GPIO_P_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR5_SHIFT)
#define GPIO_P_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR4_SHIFT)
#define GPIO_P_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR3_SHIFT)
#define GPIO_P_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR2_SHIFT)
#define GPIO_P_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR1_SHIFT)
#define GPIO_P_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR0_SHIFT)
#define GPIO_P_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7W_SHIFT)
#define GPIO_P_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6W_SHIFT)
#define GPIO_P_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5W_SHIFT)
#define GPIO_P_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4W_SHIFT)
#define GPIO_P_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3W_SHIFT)
#define GPIO_P_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2W_SHIFT)
#define GPIO_P_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1W_SHIFT)
#define GPIO_P_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0W_SHIFT)
#define GPIO_P_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7R_SHIFT)
#define GPIO_P_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6R_SHIFT)
#define GPIO_P_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5R_SHIFT)
#define GPIO_P_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4R_SHIFT)
#define GPIO_P_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3R_SHIFT)
#define GPIO_P_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2R_SHIFT)
#define GPIO_P_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1R_SHIFT)
#define GPIO_P_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0R_SHIFT)
#define GPIO_P_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_02_0
#define GPIO_P_VM_02_0                  _MK_ADDR_CONST(0x4010)
#define GPIO_P_VM_02_0_SECURE                   0x0
#define GPIO_P_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_02_0_WORD_COUNT                       0x1
#define GPIO_P_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM1_SHIFT)
#define GPIO_P_VM_02_0_VM1_RANGE                        1:0
#define GPIO_P_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM2_SHIFT)
#define GPIO_P_VM_02_0_VM2_RANGE                        3:2
#define GPIO_P_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM3_SHIFT)
#define GPIO_P_VM_02_0_VM3_RANGE                        5:4
#define GPIO_P_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM4_SHIFT)
#define GPIO_P_VM_02_0_VM4_RANGE                        7:6
#define GPIO_P_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM5_SHIFT)
#define GPIO_P_VM_02_0_VM5_RANGE                        9:8
#define GPIO_P_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM6_SHIFT)
#define GPIO_P_VM_02_0_VM6_RANGE                        11:10
#define GPIO_P_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM7_SHIFT)
#define GPIO_P_VM_02_0_VM7_RANGE                        13:12
#define GPIO_P_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM8_SHIFT)
#define GPIO_P_VM_02_0_VM8_RANGE                        15:14
#define GPIO_P_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_02_0
#define GPIO_P_SCR_02_0                 _MK_ADDR_CONST(0x4014)
#define GPIO_P_SCR_02_0_SECURE                  0x0
#define GPIO_P_SCR_02_0_SCR                     0
#define GPIO_P_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR7_SHIFT)
#define GPIO_P_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR6_SHIFT)
#define GPIO_P_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR5_SHIFT)
#define GPIO_P_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR4_SHIFT)
#define GPIO_P_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR3_SHIFT)
#define GPIO_P_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR2_SHIFT)
#define GPIO_P_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR1_SHIFT)
#define GPIO_P_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR0_SHIFT)
#define GPIO_P_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7W_SHIFT)
#define GPIO_P_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6W_SHIFT)
#define GPIO_P_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5W_SHIFT)
#define GPIO_P_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4W_SHIFT)
#define GPIO_P_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3W_SHIFT)
#define GPIO_P_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2W_SHIFT)
#define GPIO_P_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1W_SHIFT)
#define GPIO_P_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0W_SHIFT)
#define GPIO_P_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7R_SHIFT)
#define GPIO_P_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6R_SHIFT)
#define GPIO_P_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5R_SHIFT)
#define GPIO_P_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4R_SHIFT)
#define GPIO_P_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3R_SHIFT)
#define GPIO_P_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2R_SHIFT)
#define GPIO_P_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1R_SHIFT)
#define GPIO_P_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0R_SHIFT)
#define GPIO_P_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_03_0
#define GPIO_P_VM_03_0                  _MK_ADDR_CONST(0x4018)
#define GPIO_P_VM_03_0_SECURE                   0x0
#define GPIO_P_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_03_0_WORD_COUNT                       0x1
#define GPIO_P_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM1_SHIFT)
#define GPIO_P_VM_03_0_VM1_RANGE                        1:0
#define GPIO_P_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM2_SHIFT)
#define GPIO_P_VM_03_0_VM2_RANGE                        3:2
#define GPIO_P_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM3_SHIFT)
#define GPIO_P_VM_03_0_VM3_RANGE                        5:4
#define GPIO_P_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM4_SHIFT)
#define GPIO_P_VM_03_0_VM4_RANGE                        7:6
#define GPIO_P_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM5_SHIFT)
#define GPIO_P_VM_03_0_VM5_RANGE                        9:8
#define GPIO_P_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM6_SHIFT)
#define GPIO_P_VM_03_0_VM6_RANGE                        11:10
#define GPIO_P_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM7_SHIFT)
#define GPIO_P_VM_03_0_VM7_RANGE                        13:12
#define GPIO_P_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM8_SHIFT)
#define GPIO_P_VM_03_0_VM8_RANGE                        15:14
#define GPIO_P_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_03_0
#define GPIO_P_SCR_03_0                 _MK_ADDR_CONST(0x401c)
#define GPIO_P_SCR_03_0_SECURE                  0x0
#define GPIO_P_SCR_03_0_SCR                     0
#define GPIO_P_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR7_SHIFT)
#define GPIO_P_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR6_SHIFT)
#define GPIO_P_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR5_SHIFT)
#define GPIO_P_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR4_SHIFT)
#define GPIO_P_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR3_SHIFT)
#define GPIO_P_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR2_SHIFT)
#define GPIO_P_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR1_SHIFT)
#define GPIO_P_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR0_SHIFT)
#define GPIO_P_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7W_SHIFT)
#define GPIO_P_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6W_SHIFT)
#define GPIO_P_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5W_SHIFT)
#define GPIO_P_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4W_SHIFT)
#define GPIO_P_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3W_SHIFT)
#define GPIO_P_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2W_SHIFT)
#define GPIO_P_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1W_SHIFT)
#define GPIO_P_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0W_SHIFT)
#define GPIO_P_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7R_SHIFT)
#define GPIO_P_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6R_SHIFT)
#define GPIO_P_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5R_SHIFT)
#define GPIO_P_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4R_SHIFT)
#define GPIO_P_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3R_SHIFT)
#define GPIO_P_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2R_SHIFT)
#define GPIO_P_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1R_SHIFT)
#define GPIO_P_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0R_SHIFT)
#define GPIO_P_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_04_0
#define GPIO_P_VM_04_0                  _MK_ADDR_CONST(0x4020)
#define GPIO_P_VM_04_0_SECURE                   0x0
#define GPIO_P_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_04_0_WORD_COUNT                       0x1
#define GPIO_P_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM1_SHIFT)
#define GPIO_P_VM_04_0_VM1_RANGE                        1:0
#define GPIO_P_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM2_SHIFT)
#define GPIO_P_VM_04_0_VM2_RANGE                        3:2
#define GPIO_P_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM3_SHIFT)
#define GPIO_P_VM_04_0_VM3_RANGE                        5:4
#define GPIO_P_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM4_SHIFT)
#define GPIO_P_VM_04_0_VM4_RANGE                        7:6
#define GPIO_P_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM5_SHIFT)
#define GPIO_P_VM_04_0_VM5_RANGE                        9:8
#define GPIO_P_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM6_SHIFT)
#define GPIO_P_VM_04_0_VM6_RANGE                        11:10
#define GPIO_P_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM7_SHIFT)
#define GPIO_P_VM_04_0_VM7_RANGE                        13:12
#define GPIO_P_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM8_SHIFT)
#define GPIO_P_VM_04_0_VM8_RANGE                        15:14
#define GPIO_P_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_04_0
#define GPIO_P_SCR_04_0                 _MK_ADDR_CONST(0x4024)
#define GPIO_P_SCR_04_0_SECURE                  0x0
#define GPIO_P_SCR_04_0_SCR                     0
#define GPIO_P_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR7_SHIFT)
#define GPIO_P_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR6_SHIFT)
#define GPIO_P_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR5_SHIFT)
#define GPIO_P_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR4_SHIFT)
#define GPIO_P_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR3_SHIFT)
#define GPIO_P_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR2_SHIFT)
#define GPIO_P_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR1_SHIFT)
#define GPIO_P_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR0_SHIFT)
#define GPIO_P_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7W_SHIFT)
#define GPIO_P_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6W_SHIFT)
#define GPIO_P_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5W_SHIFT)
#define GPIO_P_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4W_SHIFT)
#define GPIO_P_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3W_SHIFT)
#define GPIO_P_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2W_SHIFT)
#define GPIO_P_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1W_SHIFT)
#define GPIO_P_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0W_SHIFT)
#define GPIO_P_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7R_SHIFT)
#define GPIO_P_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6R_SHIFT)
#define GPIO_P_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5R_SHIFT)
#define GPIO_P_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4R_SHIFT)
#define GPIO_P_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3R_SHIFT)
#define GPIO_P_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2R_SHIFT)
#define GPIO_P_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1R_SHIFT)
#define GPIO_P_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0R_SHIFT)
#define GPIO_P_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_05_0
#define GPIO_P_VM_05_0                  _MK_ADDR_CONST(0x4028)
#define GPIO_P_VM_05_0_SECURE                   0x0
#define GPIO_P_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_05_0_WORD_COUNT                       0x1
#define GPIO_P_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM1_SHIFT)
#define GPIO_P_VM_05_0_VM1_RANGE                        1:0
#define GPIO_P_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM2_SHIFT)
#define GPIO_P_VM_05_0_VM2_RANGE                        3:2
#define GPIO_P_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM3_SHIFT)
#define GPIO_P_VM_05_0_VM3_RANGE                        5:4
#define GPIO_P_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM4_SHIFT)
#define GPIO_P_VM_05_0_VM4_RANGE                        7:6
#define GPIO_P_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM5_SHIFT)
#define GPIO_P_VM_05_0_VM5_RANGE                        9:8
#define GPIO_P_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM6_SHIFT)
#define GPIO_P_VM_05_0_VM6_RANGE                        11:10
#define GPIO_P_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM7_SHIFT)
#define GPIO_P_VM_05_0_VM7_RANGE                        13:12
#define GPIO_P_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM8_SHIFT)
#define GPIO_P_VM_05_0_VM8_RANGE                        15:14
#define GPIO_P_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_05_0
#define GPIO_P_SCR_05_0                 _MK_ADDR_CONST(0x402c)
#define GPIO_P_SCR_05_0_SECURE                  0x0
#define GPIO_P_SCR_05_0_SCR                     0
#define GPIO_P_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR7_SHIFT)
#define GPIO_P_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR6_SHIFT)
#define GPIO_P_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR5_SHIFT)
#define GPIO_P_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR4_SHIFT)
#define GPIO_P_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR3_SHIFT)
#define GPIO_P_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR2_SHIFT)
#define GPIO_P_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR1_SHIFT)
#define GPIO_P_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR0_SHIFT)
#define GPIO_P_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7W_SHIFT)
#define GPIO_P_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6W_SHIFT)
#define GPIO_P_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5W_SHIFT)
#define GPIO_P_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4W_SHIFT)
#define GPIO_P_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3W_SHIFT)
#define GPIO_P_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2W_SHIFT)
#define GPIO_P_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1W_SHIFT)
#define GPIO_P_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0W_SHIFT)
#define GPIO_P_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7R_SHIFT)
#define GPIO_P_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6R_SHIFT)
#define GPIO_P_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5R_SHIFT)
#define GPIO_P_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4R_SHIFT)
#define GPIO_P_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3R_SHIFT)
#define GPIO_P_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2R_SHIFT)
#define GPIO_P_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1R_SHIFT)
#define GPIO_P_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0R_SHIFT)
#define GPIO_P_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_P_VM_06_0
#define GPIO_P_VM_06_0                  _MK_ADDR_CONST(0x4030)
#define GPIO_P_VM_06_0_SECURE                   0x0
#define GPIO_P_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_P_VM_06_0_WORD_COUNT                       0x1
#define GPIO_P_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM1_SHIFT)
#define GPIO_P_VM_06_0_VM1_RANGE                        1:0
#define GPIO_P_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM2_SHIFT)
#define GPIO_P_VM_06_0_VM2_RANGE                        3:2
#define GPIO_P_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM3_SHIFT)
#define GPIO_P_VM_06_0_VM3_RANGE                        5:4
#define GPIO_P_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM4_SHIFT)
#define GPIO_P_VM_06_0_VM4_RANGE                        7:6
#define GPIO_P_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM5_SHIFT)
#define GPIO_P_VM_06_0_VM5_RANGE                        9:8
#define GPIO_P_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM6_SHIFT)
#define GPIO_P_VM_06_0_VM6_RANGE                        11:10
#define GPIO_P_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM7_SHIFT)
#define GPIO_P_VM_06_0_VM7_RANGE                        13:12
#define GPIO_P_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_P_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM8_SHIFT)
#define GPIO_P_VM_06_0_VM8_RANGE                        15:14
#define GPIO_P_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_SCR_06_0
#define GPIO_P_SCR_06_0                 _MK_ADDR_CONST(0x4034)
#define GPIO_P_SCR_06_0_SECURE                  0x0
#define GPIO_P_SCR_06_0_SCR                     0
#define GPIO_P_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR7_SHIFT)
#define GPIO_P_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR6_SHIFT)
#define GPIO_P_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR5_SHIFT)
#define GPIO_P_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR4_SHIFT)
#define GPIO_P_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR3_SHIFT)
#define GPIO_P_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR2_SHIFT)
#define GPIO_P_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR1_SHIFT)
#define GPIO_P_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR0_SHIFT)
#define GPIO_P_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7W_SHIFT)
#define GPIO_P_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6W_SHIFT)
#define GPIO_P_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5W_SHIFT)
#define GPIO_P_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4W_SHIFT)
#define GPIO_P_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3W_SHIFT)
#define GPIO_P_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2W_SHIFT)
#define GPIO_P_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1W_SHIFT)
#define GPIO_P_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0W_SHIFT)
#define GPIO_P_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7R_SHIFT)
#define GPIO_P_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6R_SHIFT)
#define GPIO_P_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5R_SHIFT)
#define GPIO_P_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4R_SHIFT)
#define GPIO_P_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3R_SHIFT)
#define GPIO_P_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2R_SHIFT)
#define GPIO_P_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1R_SHIFT)
#define GPIO_P_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_P_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0R_SHIFT)
#define GPIO_P_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 16440 [0x4038]

// Reserved address 16444 [0x403c]

// Register GPIO_G_VM_00_0
#define GPIO_G_VM_00_0                  _MK_ADDR_CONST(0x4040)
#define GPIO_G_VM_00_0_SECURE                   0x0
#define GPIO_G_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_00_0_WORD_COUNT                       0x1
#define GPIO_G_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM1_SHIFT)
#define GPIO_G_VM_00_0_VM1_RANGE                        1:0
#define GPIO_G_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM2_SHIFT)
#define GPIO_G_VM_00_0_VM2_RANGE                        3:2
#define GPIO_G_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM3_SHIFT)
#define GPIO_G_VM_00_0_VM3_RANGE                        5:4
#define GPIO_G_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM4_SHIFT)
#define GPIO_G_VM_00_0_VM4_RANGE                        7:6
#define GPIO_G_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM5_SHIFT)
#define GPIO_G_VM_00_0_VM5_RANGE                        9:8
#define GPIO_G_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM6_SHIFT)
#define GPIO_G_VM_00_0_VM6_RANGE                        11:10
#define GPIO_G_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM7_SHIFT)
#define GPIO_G_VM_00_0_VM7_RANGE                        13:12
#define GPIO_G_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM8_SHIFT)
#define GPIO_G_VM_00_0_VM8_RANGE                        15:14
#define GPIO_G_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_00_0
#define GPIO_G_SCR_00_0                 _MK_ADDR_CONST(0x4044)
#define GPIO_G_SCR_00_0_SECURE                  0x0
#define GPIO_G_SCR_00_0_SCR                     0
#define GPIO_G_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR7_SHIFT)
#define GPIO_G_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR6_SHIFT)
#define GPIO_G_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR5_SHIFT)
#define GPIO_G_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR4_SHIFT)
#define GPIO_G_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR3_SHIFT)
#define GPIO_G_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR2_SHIFT)
#define GPIO_G_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR1_SHIFT)
#define GPIO_G_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR0_SHIFT)
#define GPIO_G_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7W_SHIFT)
#define GPIO_G_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6W_SHIFT)
#define GPIO_G_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5W_SHIFT)
#define GPIO_G_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4W_SHIFT)
#define GPIO_G_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3W_SHIFT)
#define GPIO_G_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2W_SHIFT)
#define GPIO_G_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1W_SHIFT)
#define GPIO_G_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0W_SHIFT)
#define GPIO_G_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7R_SHIFT)
#define GPIO_G_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6R_SHIFT)
#define GPIO_G_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5R_SHIFT)
#define GPIO_G_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4R_SHIFT)
#define GPIO_G_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3R_SHIFT)
#define GPIO_G_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2R_SHIFT)
#define GPIO_G_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1R_SHIFT)
#define GPIO_G_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0R_SHIFT)
#define GPIO_G_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_G_VM_01_0
#define GPIO_G_VM_01_0                  _MK_ADDR_CONST(0x4048)
#define GPIO_G_VM_01_0_SECURE                   0x0
#define GPIO_G_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_01_0_WORD_COUNT                       0x1
#define GPIO_G_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM1_SHIFT)
#define GPIO_G_VM_01_0_VM1_RANGE                        1:0
#define GPIO_G_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM2_SHIFT)
#define GPIO_G_VM_01_0_VM2_RANGE                        3:2
#define GPIO_G_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM3_SHIFT)
#define GPIO_G_VM_01_0_VM3_RANGE                        5:4
#define GPIO_G_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM4_SHIFT)
#define GPIO_G_VM_01_0_VM4_RANGE                        7:6
#define GPIO_G_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM5_SHIFT)
#define GPIO_G_VM_01_0_VM5_RANGE                        9:8
#define GPIO_G_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM6_SHIFT)
#define GPIO_G_VM_01_0_VM6_RANGE                        11:10
#define GPIO_G_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM7_SHIFT)
#define GPIO_G_VM_01_0_VM7_RANGE                        13:12
#define GPIO_G_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM8_SHIFT)
#define GPIO_G_VM_01_0_VM8_RANGE                        15:14
#define GPIO_G_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_01_0
#define GPIO_G_SCR_01_0                 _MK_ADDR_CONST(0x404c)
#define GPIO_G_SCR_01_0_SECURE                  0x0
#define GPIO_G_SCR_01_0_SCR                     0
#define GPIO_G_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR7_SHIFT)
#define GPIO_G_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR6_SHIFT)
#define GPIO_G_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR5_SHIFT)
#define GPIO_G_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR4_SHIFT)
#define GPIO_G_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR3_SHIFT)
#define GPIO_G_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR2_SHIFT)
#define GPIO_G_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR1_SHIFT)
#define GPIO_G_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR0_SHIFT)
#define GPIO_G_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7W_SHIFT)
#define GPIO_G_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6W_SHIFT)
#define GPIO_G_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5W_SHIFT)
#define GPIO_G_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4W_SHIFT)
#define GPIO_G_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3W_SHIFT)
#define GPIO_G_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2W_SHIFT)
#define GPIO_G_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1W_SHIFT)
#define GPIO_G_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0W_SHIFT)
#define GPIO_G_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7R_SHIFT)
#define GPIO_G_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6R_SHIFT)
#define GPIO_G_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5R_SHIFT)
#define GPIO_G_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4R_SHIFT)
#define GPIO_G_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3R_SHIFT)
#define GPIO_G_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2R_SHIFT)
#define GPIO_G_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1R_SHIFT)
#define GPIO_G_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0R_SHIFT)
#define GPIO_G_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_G_VM_02_0
#define GPIO_G_VM_02_0                  _MK_ADDR_CONST(0x4050)
#define GPIO_G_VM_02_0_SECURE                   0x0
#define GPIO_G_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_02_0_WORD_COUNT                       0x1
#define GPIO_G_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM1_SHIFT)
#define GPIO_G_VM_02_0_VM1_RANGE                        1:0
#define GPIO_G_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM2_SHIFT)
#define GPIO_G_VM_02_0_VM2_RANGE                        3:2
#define GPIO_G_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM3_SHIFT)
#define GPIO_G_VM_02_0_VM3_RANGE                        5:4
#define GPIO_G_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM4_SHIFT)
#define GPIO_G_VM_02_0_VM4_RANGE                        7:6
#define GPIO_G_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM5_SHIFT)
#define GPIO_G_VM_02_0_VM5_RANGE                        9:8
#define GPIO_G_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM6_SHIFT)
#define GPIO_G_VM_02_0_VM6_RANGE                        11:10
#define GPIO_G_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM7_SHIFT)
#define GPIO_G_VM_02_0_VM7_RANGE                        13:12
#define GPIO_G_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM8_SHIFT)
#define GPIO_G_VM_02_0_VM8_RANGE                        15:14
#define GPIO_G_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_02_0
#define GPIO_G_SCR_02_0                 _MK_ADDR_CONST(0x4054)
#define GPIO_G_SCR_02_0_SECURE                  0x0
#define GPIO_G_SCR_02_0_SCR                     0
#define GPIO_G_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR7_SHIFT)
#define GPIO_G_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR6_SHIFT)
#define GPIO_G_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR5_SHIFT)
#define GPIO_G_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR4_SHIFT)
#define GPIO_G_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR3_SHIFT)
#define GPIO_G_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR2_SHIFT)
#define GPIO_G_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR1_SHIFT)
#define GPIO_G_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR0_SHIFT)
#define GPIO_G_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7W_SHIFT)
#define GPIO_G_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6W_SHIFT)
#define GPIO_G_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5W_SHIFT)
#define GPIO_G_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4W_SHIFT)
#define GPIO_G_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3W_SHIFT)
#define GPIO_G_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2W_SHIFT)
#define GPIO_G_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1W_SHIFT)
#define GPIO_G_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0W_SHIFT)
#define GPIO_G_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7R_SHIFT)
#define GPIO_G_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6R_SHIFT)
#define GPIO_G_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5R_SHIFT)
#define GPIO_G_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4R_SHIFT)
#define GPIO_G_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3R_SHIFT)
#define GPIO_G_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2R_SHIFT)
#define GPIO_G_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1R_SHIFT)
#define GPIO_G_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0R_SHIFT)
#define GPIO_G_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_G_VM_03_0
#define GPIO_G_VM_03_0                  _MK_ADDR_CONST(0x4058)
#define GPIO_G_VM_03_0_SECURE                   0x0
#define GPIO_G_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_03_0_WORD_COUNT                       0x1
#define GPIO_G_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM1_SHIFT)
#define GPIO_G_VM_03_0_VM1_RANGE                        1:0
#define GPIO_G_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM2_SHIFT)
#define GPIO_G_VM_03_0_VM2_RANGE                        3:2
#define GPIO_G_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM3_SHIFT)
#define GPIO_G_VM_03_0_VM3_RANGE                        5:4
#define GPIO_G_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM4_SHIFT)
#define GPIO_G_VM_03_0_VM4_RANGE                        7:6
#define GPIO_G_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM5_SHIFT)
#define GPIO_G_VM_03_0_VM5_RANGE                        9:8
#define GPIO_G_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM6_SHIFT)
#define GPIO_G_VM_03_0_VM6_RANGE                        11:10
#define GPIO_G_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM7_SHIFT)
#define GPIO_G_VM_03_0_VM7_RANGE                        13:12
#define GPIO_G_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM8_SHIFT)
#define GPIO_G_VM_03_0_VM8_RANGE                        15:14
#define GPIO_G_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_03_0
#define GPIO_G_SCR_03_0                 _MK_ADDR_CONST(0x405c)
#define GPIO_G_SCR_03_0_SECURE                  0x0
#define GPIO_G_SCR_03_0_SCR                     0
#define GPIO_G_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR7_SHIFT)
#define GPIO_G_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR6_SHIFT)
#define GPIO_G_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR5_SHIFT)
#define GPIO_G_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR4_SHIFT)
#define GPIO_G_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR3_SHIFT)
#define GPIO_G_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR2_SHIFT)
#define GPIO_G_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR1_SHIFT)
#define GPIO_G_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR0_SHIFT)
#define GPIO_G_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7W_SHIFT)
#define GPIO_G_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6W_SHIFT)
#define GPIO_G_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5W_SHIFT)
#define GPIO_G_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4W_SHIFT)
#define GPIO_G_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3W_SHIFT)
#define GPIO_G_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2W_SHIFT)
#define GPIO_G_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1W_SHIFT)
#define GPIO_G_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0W_SHIFT)
#define GPIO_G_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7R_SHIFT)
#define GPIO_G_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6R_SHIFT)
#define GPIO_G_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5R_SHIFT)
#define GPIO_G_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4R_SHIFT)
#define GPIO_G_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3R_SHIFT)
#define GPIO_G_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2R_SHIFT)
#define GPIO_G_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1R_SHIFT)
#define GPIO_G_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0R_SHIFT)
#define GPIO_G_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_G_VM_04_0
#define GPIO_G_VM_04_0                  _MK_ADDR_CONST(0x4060)
#define GPIO_G_VM_04_0_SECURE                   0x0
#define GPIO_G_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_04_0_WORD_COUNT                       0x1
#define GPIO_G_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM1_SHIFT)
#define GPIO_G_VM_04_0_VM1_RANGE                        1:0
#define GPIO_G_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM2_SHIFT)
#define GPIO_G_VM_04_0_VM2_RANGE                        3:2
#define GPIO_G_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM3_SHIFT)
#define GPIO_G_VM_04_0_VM3_RANGE                        5:4
#define GPIO_G_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM4_SHIFT)
#define GPIO_G_VM_04_0_VM4_RANGE                        7:6
#define GPIO_G_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM5_SHIFT)
#define GPIO_G_VM_04_0_VM5_RANGE                        9:8
#define GPIO_G_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM6_SHIFT)
#define GPIO_G_VM_04_0_VM6_RANGE                        11:10
#define GPIO_G_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM7_SHIFT)
#define GPIO_G_VM_04_0_VM7_RANGE                        13:12
#define GPIO_G_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM8_SHIFT)
#define GPIO_G_VM_04_0_VM8_RANGE                        15:14
#define GPIO_G_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_04_0
#define GPIO_G_SCR_04_0                 _MK_ADDR_CONST(0x4064)
#define GPIO_G_SCR_04_0_SECURE                  0x0
#define GPIO_G_SCR_04_0_SCR                     0
#define GPIO_G_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR7_SHIFT)
#define GPIO_G_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR6_SHIFT)
#define GPIO_G_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR5_SHIFT)
#define GPIO_G_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR4_SHIFT)
#define GPIO_G_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR3_SHIFT)
#define GPIO_G_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR2_SHIFT)
#define GPIO_G_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR1_SHIFT)
#define GPIO_G_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR0_SHIFT)
#define GPIO_G_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7W_SHIFT)
#define GPIO_G_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6W_SHIFT)
#define GPIO_G_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5W_SHIFT)
#define GPIO_G_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4W_SHIFT)
#define GPIO_G_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3W_SHIFT)
#define GPIO_G_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2W_SHIFT)
#define GPIO_G_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1W_SHIFT)
#define GPIO_G_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0W_SHIFT)
#define GPIO_G_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7R_SHIFT)
#define GPIO_G_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6R_SHIFT)
#define GPIO_G_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5R_SHIFT)
#define GPIO_G_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4R_SHIFT)
#define GPIO_G_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3R_SHIFT)
#define GPIO_G_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2R_SHIFT)
#define GPIO_G_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1R_SHIFT)
#define GPIO_G_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0R_SHIFT)
#define GPIO_G_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_G_VM_05_0
#define GPIO_G_VM_05_0                  _MK_ADDR_CONST(0x4068)
#define GPIO_G_VM_05_0_SECURE                   0x0
#define GPIO_G_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_05_0_WORD_COUNT                       0x1
#define GPIO_G_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM1_SHIFT)
#define GPIO_G_VM_05_0_VM1_RANGE                        1:0
#define GPIO_G_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM2_SHIFT)
#define GPIO_G_VM_05_0_VM2_RANGE                        3:2
#define GPIO_G_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM3_SHIFT)
#define GPIO_G_VM_05_0_VM3_RANGE                        5:4
#define GPIO_G_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM4_SHIFT)
#define GPIO_G_VM_05_0_VM4_RANGE                        7:6
#define GPIO_G_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM5_SHIFT)
#define GPIO_G_VM_05_0_VM5_RANGE                        9:8
#define GPIO_G_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM6_SHIFT)
#define GPIO_G_VM_05_0_VM6_RANGE                        11:10
#define GPIO_G_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM7_SHIFT)
#define GPIO_G_VM_05_0_VM7_RANGE                        13:12
#define GPIO_G_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_G_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM8_SHIFT)
#define GPIO_G_VM_05_0_VM8_RANGE                        15:14
#define GPIO_G_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_SCR_05_0
#define GPIO_G_SCR_05_0                 _MK_ADDR_CONST(0x406c)
#define GPIO_G_SCR_05_0_SECURE                  0x0
#define GPIO_G_SCR_05_0_SCR                     0
#define GPIO_G_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR7_SHIFT)
#define GPIO_G_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR6_SHIFT)
#define GPIO_G_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR5_SHIFT)
#define GPIO_G_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR4_SHIFT)
#define GPIO_G_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR3_SHIFT)
#define GPIO_G_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR2_SHIFT)
#define GPIO_G_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR1_SHIFT)
#define GPIO_G_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR0_SHIFT)
#define GPIO_G_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7W_SHIFT)
#define GPIO_G_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6W_SHIFT)
#define GPIO_G_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5W_SHIFT)
#define GPIO_G_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4W_SHIFT)
#define GPIO_G_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3W_SHIFT)
#define GPIO_G_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2W_SHIFT)
#define GPIO_G_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1W_SHIFT)
#define GPIO_G_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0W_SHIFT)
#define GPIO_G_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7R_SHIFT)
#define GPIO_G_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6R_SHIFT)
#define GPIO_G_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5R_SHIFT)
#define GPIO_G_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4R_SHIFT)
#define GPIO_G_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3R_SHIFT)
#define GPIO_G_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2R_SHIFT)
#define GPIO_G_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1R_SHIFT)
#define GPIO_G_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_G_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0R_SHIFT)
#define GPIO_G_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 16496 [0x4070]

// Reserved address 16500 [0x4074]

// Reserved address 16504 [0x4078]

// Reserved address 16508 [0x407c]

// Register GPIO_CTL4_VM_SCR_0
#define GPIO_CTL4_VM_SCR_0                      _MK_ADDR_CONST(0x4800)
#define GPIO_CTL4_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL4_VM_SCR_0_SCR                  0
#define GPIO_CTL4_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL4_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL4_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL4_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL4_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL4_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL4_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL4_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL4_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL4_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL4_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL4_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL4_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL4_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL4_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL4_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL4_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL4_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL4_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL4_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL4_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL4_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL4_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL4_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL4_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL4_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL4_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL4_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL4_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL4_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL4_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL4_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL4_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL4_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL4_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL4_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL4_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL4_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL4_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL4_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL4_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL4_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL4_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL4_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL4_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL4_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL4_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL4_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL4_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL4_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL4_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL4_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x4804)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x4808)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL4_SCR_0
#define GPIO_CTL4_SCR_0                 _MK_ADDR_CONST(0x480c)
#define GPIO_CTL4_SCR_0_SECURE                  0x0
#define GPIO_CTL4_SCR_0_SCR                     0
#define GPIO_CTL4_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL4_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL4_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL4_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL4_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL4_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL4_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL4_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL4_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL4_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL4_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL4_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL4_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL4_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL4_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL4_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL4_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL4_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL4_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL4_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL4_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL4_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL4_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL4_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL4_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL4_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL4_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL4_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL4_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL4_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL4_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL4_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL4_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL4_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL4_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL4_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL4_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL4_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL4_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL4_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL4_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL4_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL4_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL4_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL4_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL4_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL4_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL4_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL4_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL4_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL4_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL4_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL4_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL4_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL4_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL4_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL4_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL4_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL4_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL4_ICG_EN_OVERRIDE_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x4810)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL4_SPARE_0
#define GPIO_CTL4_SPARE_0                       _MK_ADDR_CONST(0x4814)
#define GPIO_CTL4_SPARE_0_SECURE                        0x0
#define GPIO_CTL4_SPARE_0_SCR                   0
#define GPIO_CTL4_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL4_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL4_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL4_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL4_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL4_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_00_0
#define GPIO_J_VM_00_0                  _MK_ADDR_CONST(0x5000)
#define GPIO_J_VM_00_0_SECURE                   0x0
#define GPIO_J_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_00_0_WORD_COUNT                       0x1
#define GPIO_J_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM1_SHIFT)
#define GPIO_J_VM_00_0_VM1_RANGE                        1:0
#define GPIO_J_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM2_SHIFT)
#define GPIO_J_VM_00_0_VM2_RANGE                        3:2
#define GPIO_J_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM3_SHIFT)
#define GPIO_J_VM_00_0_VM3_RANGE                        5:4
#define GPIO_J_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM4_SHIFT)
#define GPIO_J_VM_00_0_VM4_RANGE                        7:6
#define GPIO_J_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM5_SHIFT)
#define GPIO_J_VM_00_0_VM5_RANGE                        9:8
#define GPIO_J_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM6_SHIFT)
#define GPIO_J_VM_00_0_VM6_RANGE                        11:10
#define GPIO_J_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM7_SHIFT)
#define GPIO_J_VM_00_0_VM7_RANGE                        13:12
#define GPIO_J_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM8_SHIFT)
#define GPIO_J_VM_00_0_VM8_RANGE                        15:14
#define GPIO_J_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_00_0
#define GPIO_J_SCR_00_0                 _MK_ADDR_CONST(0x5004)
#define GPIO_J_SCR_00_0_SECURE                  0x0
#define GPIO_J_SCR_00_0_SCR                     0
#define GPIO_J_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR7_SHIFT)
#define GPIO_J_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR6_SHIFT)
#define GPIO_J_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR5_SHIFT)
#define GPIO_J_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR4_SHIFT)
#define GPIO_J_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR3_SHIFT)
#define GPIO_J_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR2_SHIFT)
#define GPIO_J_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR1_SHIFT)
#define GPIO_J_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR0_SHIFT)
#define GPIO_J_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7W_SHIFT)
#define GPIO_J_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6W_SHIFT)
#define GPIO_J_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5W_SHIFT)
#define GPIO_J_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4W_SHIFT)
#define GPIO_J_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3W_SHIFT)
#define GPIO_J_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2W_SHIFT)
#define GPIO_J_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1W_SHIFT)
#define GPIO_J_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0W_SHIFT)
#define GPIO_J_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7R_SHIFT)
#define GPIO_J_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6R_SHIFT)
#define GPIO_J_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5R_SHIFT)
#define GPIO_J_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4R_SHIFT)
#define GPIO_J_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3R_SHIFT)
#define GPIO_J_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2R_SHIFT)
#define GPIO_J_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1R_SHIFT)
#define GPIO_J_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0R_SHIFT)
#define GPIO_J_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_01_0
#define GPIO_J_VM_01_0                  _MK_ADDR_CONST(0x5008)
#define GPIO_J_VM_01_0_SECURE                   0x0
#define GPIO_J_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_01_0_WORD_COUNT                       0x1
#define GPIO_J_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM1_SHIFT)
#define GPIO_J_VM_01_0_VM1_RANGE                        1:0
#define GPIO_J_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM2_SHIFT)
#define GPIO_J_VM_01_0_VM2_RANGE                        3:2
#define GPIO_J_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM3_SHIFT)
#define GPIO_J_VM_01_0_VM3_RANGE                        5:4
#define GPIO_J_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM4_SHIFT)
#define GPIO_J_VM_01_0_VM4_RANGE                        7:6
#define GPIO_J_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM5_SHIFT)
#define GPIO_J_VM_01_0_VM5_RANGE                        9:8
#define GPIO_J_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM6_SHIFT)
#define GPIO_J_VM_01_0_VM6_RANGE                        11:10
#define GPIO_J_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM7_SHIFT)
#define GPIO_J_VM_01_0_VM7_RANGE                        13:12
#define GPIO_J_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM8_SHIFT)
#define GPIO_J_VM_01_0_VM8_RANGE                        15:14
#define GPIO_J_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_01_0
#define GPIO_J_SCR_01_0                 _MK_ADDR_CONST(0x500c)
#define GPIO_J_SCR_01_0_SECURE                  0x0
#define GPIO_J_SCR_01_0_SCR                     0
#define GPIO_J_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR7_SHIFT)
#define GPIO_J_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR6_SHIFT)
#define GPIO_J_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR5_SHIFT)
#define GPIO_J_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR4_SHIFT)
#define GPIO_J_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR3_SHIFT)
#define GPIO_J_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR2_SHIFT)
#define GPIO_J_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR1_SHIFT)
#define GPIO_J_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR0_SHIFT)
#define GPIO_J_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7W_SHIFT)
#define GPIO_J_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6W_SHIFT)
#define GPIO_J_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5W_SHIFT)
#define GPIO_J_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4W_SHIFT)
#define GPIO_J_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3W_SHIFT)
#define GPIO_J_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2W_SHIFT)
#define GPIO_J_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1W_SHIFT)
#define GPIO_J_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0W_SHIFT)
#define GPIO_J_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7R_SHIFT)
#define GPIO_J_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6R_SHIFT)
#define GPIO_J_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5R_SHIFT)
#define GPIO_J_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4R_SHIFT)
#define GPIO_J_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3R_SHIFT)
#define GPIO_J_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2R_SHIFT)
#define GPIO_J_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1R_SHIFT)
#define GPIO_J_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0R_SHIFT)
#define GPIO_J_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_02_0
#define GPIO_J_VM_02_0                  _MK_ADDR_CONST(0x5010)
#define GPIO_J_VM_02_0_SECURE                   0x0
#define GPIO_J_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_02_0_WORD_COUNT                       0x1
#define GPIO_J_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM1_SHIFT)
#define GPIO_J_VM_02_0_VM1_RANGE                        1:0
#define GPIO_J_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM2_SHIFT)
#define GPIO_J_VM_02_0_VM2_RANGE                        3:2
#define GPIO_J_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM3_SHIFT)
#define GPIO_J_VM_02_0_VM3_RANGE                        5:4
#define GPIO_J_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM4_SHIFT)
#define GPIO_J_VM_02_0_VM4_RANGE                        7:6
#define GPIO_J_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM5_SHIFT)
#define GPIO_J_VM_02_0_VM5_RANGE                        9:8
#define GPIO_J_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM6_SHIFT)
#define GPIO_J_VM_02_0_VM6_RANGE                        11:10
#define GPIO_J_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM7_SHIFT)
#define GPIO_J_VM_02_0_VM7_RANGE                        13:12
#define GPIO_J_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM8_SHIFT)
#define GPIO_J_VM_02_0_VM8_RANGE                        15:14
#define GPIO_J_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_02_0
#define GPIO_J_SCR_02_0                 _MK_ADDR_CONST(0x5014)
#define GPIO_J_SCR_02_0_SECURE                  0x0
#define GPIO_J_SCR_02_0_SCR                     0
#define GPIO_J_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR7_SHIFT)
#define GPIO_J_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR6_SHIFT)
#define GPIO_J_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR5_SHIFT)
#define GPIO_J_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR4_SHIFT)
#define GPIO_J_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR3_SHIFT)
#define GPIO_J_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR2_SHIFT)
#define GPIO_J_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR1_SHIFT)
#define GPIO_J_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR0_SHIFT)
#define GPIO_J_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7W_SHIFT)
#define GPIO_J_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6W_SHIFT)
#define GPIO_J_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5W_SHIFT)
#define GPIO_J_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4W_SHIFT)
#define GPIO_J_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3W_SHIFT)
#define GPIO_J_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2W_SHIFT)
#define GPIO_J_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1W_SHIFT)
#define GPIO_J_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0W_SHIFT)
#define GPIO_J_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7R_SHIFT)
#define GPIO_J_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6R_SHIFT)
#define GPIO_J_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5R_SHIFT)
#define GPIO_J_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4R_SHIFT)
#define GPIO_J_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3R_SHIFT)
#define GPIO_J_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2R_SHIFT)
#define GPIO_J_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1R_SHIFT)
#define GPIO_J_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0R_SHIFT)
#define GPIO_J_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_03_0
#define GPIO_J_VM_03_0                  _MK_ADDR_CONST(0x5018)
#define GPIO_J_VM_03_0_SECURE                   0x0
#define GPIO_J_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_03_0_WORD_COUNT                       0x1
#define GPIO_J_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM1_SHIFT)
#define GPIO_J_VM_03_0_VM1_RANGE                        1:0
#define GPIO_J_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM2_SHIFT)
#define GPIO_J_VM_03_0_VM2_RANGE                        3:2
#define GPIO_J_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM3_SHIFT)
#define GPIO_J_VM_03_0_VM3_RANGE                        5:4
#define GPIO_J_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM4_SHIFT)
#define GPIO_J_VM_03_0_VM4_RANGE                        7:6
#define GPIO_J_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM5_SHIFT)
#define GPIO_J_VM_03_0_VM5_RANGE                        9:8
#define GPIO_J_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM6_SHIFT)
#define GPIO_J_VM_03_0_VM6_RANGE                        11:10
#define GPIO_J_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM7_SHIFT)
#define GPIO_J_VM_03_0_VM7_RANGE                        13:12
#define GPIO_J_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM8_SHIFT)
#define GPIO_J_VM_03_0_VM8_RANGE                        15:14
#define GPIO_J_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_03_0
#define GPIO_J_SCR_03_0                 _MK_ADDR_CONST(0x501c)
#define GPIO_J_SCR_03_0_SECURE                  0x0
#define GPIO_J_SCR_03_0_SCR                     0
#define GPIO_J_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR7_SHIFT)
#define GPIO_J_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR6_SHIFT)
#define GPIO_J_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR5_SHIFT)
#define GPIO_J_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR4_SHIFT)
#define GPIO_J_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR3_SHIFT)
#define GPIO_J_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR2_SHIFT)
#define GPIO_J_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR1_SHIFT)
#define GPIO_J_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR0_SHIFT)
#define GPIO_J_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7W_SHIFT)
#define GPIO_J_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6W_SHIFT)
#define GPIO_J_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5W_SHIFT)
#define GPIO_J_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4W_SHIFT)
#define GPIO_J_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3W_SHIFT)
#define GPIO_J_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2W_SHIFT)
#define GPIO_J_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1W_SHIFT)
#define GPIO_J_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0W_SHIFT)
#define GPIO_J_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7R_SHIFT)
#define GPIO_J_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6R_SHIFT)
#define GPIO_J_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5R_SHIFT)
#define GPIO_J_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4R_SHIFT)
#define GPIO_J_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3R_SHIFT)
#define GPIO_J_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2R_SHIFT)
#define GPIO_J_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1R_SHIFT)
#define GPIO_J_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0R_SHIFT)
#define GPIO_J_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_04_0
#define GPIO_J_VM_04_0                  _MK_ADDR_CONST(0x5020)
#define GPIO_J_VM_04_0_SECURE                   0x0
#define GPIO_J_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_04_0_WORD_COUNT                       0x1
#define GPIO_J_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM1_SHIFT)
#define GPIO_J_VM_04_0_VM1_RANGE                        1:0
#define GPIO_J_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM2_SHIFT)
#define GPIO_J_VM_04_0_VM2_RANGE                        3:2
#define GPIO_J_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM3_SHIFT)
#define GPIO_J_VM_04_0_VM3_RANGE                        5:4
#define GPIO_J_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM4_SHIFT)
#define GPIO_J_VM_04_0_VM4_RANGE                        7:6
#define GPIO_J_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM5_SHIFT)
#define GPIO_J_VM_04_0_VM5_RANGE                        9:8
#define GPIO_J_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM6_SHIFT)
#define GPIO_J_VM_04_0_VM6_RANGE                        11:10
#define GPIO_J_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM7_SHIFT)
#define GPIO_J_VM_04_0_VM7_RANGE                        13:12
#define GPIO_J_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM8_SHIFT)
#define GPIO_J_VM_04_0_VM8_RANGE                        15:14
#define GPIO_J_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_04_0
#define GPIO_J_SCR_04_0                 _MK_ADDR_CONST(0x5024)
#define GPIO_J_SCR_04_0_SECURE                  0x0
#define GPIO_J_SCR_04_0_SCR                     0
#define GPIO_J_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR7_SHIFT)
#define GPIO_J_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR6_SHIFT)
#define GPIO_J_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR5_SHIFT)
#define GPIO_J_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR4_SHIFT)
#define GPIO_J_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR3_SHIFT)
#define GPIO_J_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR2_SHIFT)
#define GPIO_J_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR1_SHIFT)
#define GPIO_J_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR0_SHIFT)
#define GPIO_J_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7W_SHIFT)
#define GPIO_J_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6W_SHIFT)
#define GPIO_J_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5W_SHIFT)
#define GPIO_J_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4W_SHIFT)
#define GPIO_J_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3W_SHIFT)
#define GPIO_J_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2W_SHIFT)
#define GPIO_J_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1W_SHIFT)
#define GPIO_J_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0W_SHIFT)
#define GPIO_J_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7R_SHIFT)
#define GPIO_J_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6R_SHIFT)
#define GPIO_J_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5R_SHIFT)
#define GPIO_J_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4R_SHIFT)
#define GPIO_J_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3R_SHIFT)
#define GPIO_J_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2R_SHIFT)
#define GPIO_J_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1R_SHIFT)
#define GPIO_J_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0R_SHIFT)
#define GPIO_J_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_05_0
#define GPIO_J_VM_05_0                  _MK_ADDR_CONST(0x5028)
#define GPIO_J_VM_05_0_SECURE                   0x0
#define GPIO_J_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_05_0_WORD_COUNT                       0x1
#define GPIO_J_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM1_SHIFT)
#define GPIO_J_VM_05_0_VM1_RANGE                        1:0
#define GPIO_J_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM2_SHIFT)
#define GPIO_J_VM_05_0_VM2_RANGE                        3:2
#define GPIO_J_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM3_SHIFT)
#define GPIO_J_VM_05_0_VM3_RANGE                        5:4
#define GPIO_J_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM4_SHIFT)
#define GPIO_J_VM_05_0_VM4_RANGE                        7:6
#define GPIO_J_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM5_SHIFT)
#define GPIO_J_VM_05_0_VM5_RANGE                        9:8
#define GPIO_J_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM6_SHIFT)
#define GPIO_J_VM_05_0_VM6_RANGE                        11:10
#define GPIO_J_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM7_SHIFT)
#define GPIO_J_VM_05_0_VM7_RANGE                        13:12
#define GPIO_J_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM8_SHIFT)
#define GPIO_J_VM_05_0_VM8_RANGE                        15:14
#define GPIO_J_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_05_0
#define GPIO_J_SCR_05_0                 _MK_ADDR_CONST(0x502c)
#define GPIO_J_SCR_05_0_SECURE                  0x0
#define GPIO_J_SCR_05_0_SCR                     0
#define GPIO_J_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR7_SHIFT)
#define GPIO_J_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR6_SHIFT)
#define GPIO_J_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR5_SHIFT)
#define GPIO_J_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR4_SHIFT)
#define GPIO_J_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR3_SHIFT)
#define GPIO_J_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR2_SHIFT)
#define GPIO_J_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR1_SHIFT)
#define GPIO_J_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR0_SHIFT)
#define GPIO_J_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7W_SHIFT)
#define GPIO_J_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6W_SHIFT)
#define GPIO_J_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5W_SHIFT)
#define GPIO_J_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4W_SHIFT)
#define GPIO_J_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3W_SHIFT)
#define GPIO_J_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2W_SHIFT)
#define GPIO_J_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1W_SHIFT)
#define GPIO_J_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0W_SHIFT)
#define GPIO_J_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7R_SHIFT)
#define GPIO_J_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6R_SHIFT)
#define GPIO_J_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5R_SHIFT)
#define GPIO_J_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4R_SHIFT)
#define GPIO_J_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3R_SHIFT)
#define GPIO_J_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2R_SHIFT)
#define GPIO_J_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1R_SHIFT)
#define GPIO_J_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0R_SHIFT)
#define GPIO_J_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_06_0
#define GPIO_J_VM_06_0                  _MK_ADDR_CONST(0x5030)
#define GPIO_J_VM_06_0_SECURE                   0x0
#define GPIO_J_VM_06_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_06_0_WORD_COUNT                       0x1
#define GPIO_J_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM1_SHIFT)
#define GPIO_J_VM_06_0_VM1_RANGE                        1:0
#define GPIO_J_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM2_SHIFT)
#define GPIO_J_VM_06_0_VM2_RANGE                        3:2
#define GPIO_J_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM3_SHIFT)
#define GPIO_J_VM_06_0_VM3_RANGE                        5:4
#define GPIO_J_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM4_SHIFT)
#define GPIO_J_VM_06_0_VM4_RANGE                        7:6
#define GPIO_J_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM5_SHIFT)
#define GPIO_J_VM_06_0_VM5_RANGE                        9:8
#define GPIO_J_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM6_SHIFT)
#define GPIO_J_VM_06_0_VM6_RANGE                        11:10
#define GPIO_J_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM7_SHIFT)
#define GPIO_J_VM_06_0_VM7_RANGE                        13:12
#define GPIO_J_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_06_0_VM8_SHIFT)
#define GPIO_J_VM_06_0_VM8_RANGE                        15:14
#define GPIO_J_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_06_0
#define GPIO_J_SCR_06_0                 _MK_ADDR_CONST(0x5034)
#define GPIO_J_SCR_06_0_SECURE                  0x0
#define GPIO_J_SCR_06_0_SCR                     0
#define GPIO_J_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR7_SHIFT)
#define GPIO_J_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR6_SHIFT)
#define GPIO_J_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR5_SHIFT)
#define GPIO_J_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR4_SHIFT)
#define GPIO_J_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR3_SHIFT)
#define GPIO_J_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR2_SHIFT)
#define GPIO_J_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR1_SHIFT)
#define GPIO_J_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_PR0_SHIFT)
#define GPIO_J_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G7W_SHIFT)
#define GPIO_J_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G6W_SHIFT)
#define GPIO_J_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G5W_SHIFT)
#define GPIO_J_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G4W_SHIFT)
#define GPIO_J_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G3W_SHIFT)
#define GPIO_J_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G2W_SHIFT)
#define GPIO_J_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G1W_SHIFT)
#define GPIO_J_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G0W_SHIFT)
#define GPIO_J_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G7R_SHIFT)
#define GPIO_J_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G6R_SHIFT)
#define GPIO_J_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G5R_SHIFT)
#define GPIO_J_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G4R_SHIFT)
#define GPIO_J_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G3R_SHIFT)
#define GPIO_J_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G2R_SHIFT)
#define GPIO_J_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G1R_SHIFT)
#define GPIO_J_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_06_0_G0R_SHIFT)
#define GPIO_J_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_J_VM_07_0
#define GPIO_J_VM_07_0                  _MK_ADDR_CONST(0x5038)
#define GPIO_J_VM_07_0_SECURE                   0x0
#define GPIO_J_VM_07_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_07_0_WORD_COUNT                       0x1
#define GPIO_J_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM1_SHIFT)
#define GPIO_J_VM_07_0_VM1_RANGE                        1:0
#define GPIO_J_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM2_SHIFT)
#define GPIO_J_VM_07_0_VM2_RANGE                        3:2
#define GPIO_J_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM3_SHIFT)
#define GPIO_J_VM_07_0_VM3_RANGE                        5:4
#define GPIO_J_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM4_SHIFT)
#define GPIO_J_VM_07_0_VM4_RANGE                        7:6
#define GPIO_J_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM5_SHIFT)
#define GPIO_J_VM_07_0_VM5_RANGE                        9:8
#define GPIO_J_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM6_SHIFT)
#define GPIO_J_VM_07_0_VM6_RANGE                        11:10
#define GPIO_J_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM7_SHIFT)
#define GPIO_J_VM_07_0_VM7_RANGE                        13:12
#define GPIO_J_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_J_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_07_0_VM8_SHIFT)
#define GPIO_J_VM_07_0_VM8_RANGE                        15:14
#define GPIO_J_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_SCR_07_0
#define GPIO_J_SCR_07_0                 _MK_ADDR_CONST(0x503c)
#define GPIO_J_SCR_07_0_SECURE                  0x0
#define GPIO_J_SCR_07_0_SCR                     0
#define GPIO_J_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR7_SHIFT)
#define GPIO_J_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR6_SHIFT)
#define GPIO_J_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR5_SHIFT)
#define GPIO_J_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR4_SHIFT)
#define GPIO_J_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR3_SHIFT)
#define GPIO_J_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR2_SHIFT)
#define GPIO_J_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR1_SHIFT)
#define GPIO_J_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_PR0_SHIFT)
#define GPIO_J_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G7W_SHIFT)
#define GPIO_J_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G6W_SHIFT)
#define GPIO_J_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G5W_SHIFT)
#define GPIO_J_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G4W_SHIFT)
#define GPIO_J_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G3W_SHIFT)
#define GPIO_J_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G2W_SHIFT)
#define GPIO_J_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G1W_SHIFT)
#define GPIO_J_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G0W_SHIFT)
#define GPIO_J_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G7R_SHIFT)
#define GPIO_J_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G6R_SHIFT)
#define GPIO_J_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G5R_SHIFT)
#define GPIO_J_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G4R_SHIFT)
#define GPIO_J_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G3R_SHIFT)
#define GPIO_J_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G2R_SHIFT)
#define GPIO_J_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G1R_SHIFT)
#define GPIO_J_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_J_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_07_0_G0R_SHIFT)
#define GPIO_J_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_K_VM_00_0
#define GPIO_K_VM_00_0                  _MK_ADDR_CONST(0x5040)
#define GPIO_K_VM_00_0_SECURE                   0x0
#define GPIO_K_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_K_VM_00_0_WORD_COUNT                       0x1
#define GPIO_K_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM1_SHIFT)
#define GPIO_K_VM_00_0_VM1_RANGE                        1:0
#define GPIO_K_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM2_SHIFT)
#define GPIO_K_VM_00_0_VM2_RANGE                        3:2
#define GPIO_K_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM3_SHIFT)
#define GPIO_K_VM_00_0_VM3_RANGE                        5:4
#define GPIO_K_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM4_SHIFT)
#define GPIO_K_VM_00_0_VM4_RANGE                        7:6
#define GPIO_K_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM5_SHIFT)
#define GPIO_K_VM_00_0_VM5_RANGE                        9:8
#define GPIO_K_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM6_SHIFT)
#define GPIO_K_VM_00_0_VM6_RANGE                        11:10
#define GPIO_K_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM7_SHIFT)
#define GPIO_K_VM_00_0_VM7_RANGE                        13:12
#define GPIO_K_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_K_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM8_SHIFT)
#define GPIO_K_VM_00_0_VM8_RANGE                        15:14
#define GPIO_K_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_SCR_00_0
#define GPIO_K_SCR_00_0                 _MK_ADDR_CONST(0x5044)
#define GPIO_K_SCR_00_0_SECURE                  0x0
#define GPIO_K_SCR_00_0_SCR                     0
#define GPIO_K_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR7_SHIFT)
#define GPIO_K_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR6_SHIFT)
#define GPIO_K_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR5_SHIFT)
#define GPIO_K_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR4_SHIFT)
#define GPIO_K_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR3_SHIFT)
#define GPIO_K_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR2_SHIFT)
#define GPIO_K_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR1_SHIFT)
#define GPIO_K_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR0_SHIFT)
#define GPIO_K_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7W_SHIFT)
#define GPIO_K_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6W_SHIFT)
#define GPIO_K_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5W_SHIFT)
#define GPIO_K_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4W_SHIFT)
#define GPIO_K_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3W_SHIFT)
#define GPIO_K_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2W_SHIFT)
#define GPIO_K_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1W_SHIFT)
#define GPIO_K_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0W_SHIFT)
#define GPIO_K_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7R_SHIFT)
#define GPIO_K_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6R_SHIFT)
#define GPIO_K_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5R_SHIFT)
#define GPIO_K_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4R_SHIFT)
#define GPIO_K_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3R_SHIFT)
#define GPIO_K_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2R_SHIFT)
#define GPIO_K_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1R_SHIFT)
#define GPIO_K_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_K_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0R_SHIFT)
#define GPIO_K_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 20552 [0x5048]

// Reserved address 20556 [0x504c]

// Reserved address 20560 [0x5050]

// Reserved address 20564 [0x5054]

// Reserved address 20568 [0x5058]

// Reserved address 20572 [0x505c]

// Reserved address 20576 [0x5060]

// Reserved address 20580 [0x5064]

// Reserved address 20584 [0x5068]

// Reserved address 20588 [0x506c]

// Reserved address 20592 [0x5070]

// Reserved address 20596 [0x5074]

// Reserved address 20600 [0x5078]

// Reserved address 20604 [0x507c]

// Register GPIO_CC_VM_00_0
#define GPIO_CC_VM_00_0                 _MK_ADDR_CONST(0x5080)
#define GPIO_CC_VM_00_0_SECURE                  0x0
#define GPIO_CC_VM_00_0_SCR                     GPIO_CTL5_VM_SCR_0
#define GPIO_CC_VM_00_0_WORD_COUNT                      0x1
#define GPIO_CC_VM_00_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_00_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_00_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_00_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_VM_00_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM1_SHIFT)
#define GPIO_CC_VM_00_0_VM1_RANGE                       1:0
#define GPIO_CC_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CC_VM_00_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM2_SHIFT)
#define GPIO_CC_VM_00_0_VM2_RANGE                       3:2
#define GPIO_CC_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CC_VM_00_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM3_SHIFT)
#define GPIO_CC_VM_00_0_VM3_RANGE                       5:4
#define GPIO_CC_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CC_VM_00_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM4_SHIFT)
#define GPIO_CC_VM_00_0_VM4_RANGE                       7:6
#define GPIO_CC_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CC_VM_00_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM5_SHIFT)
#define GPIO_CC_VM_00_0_VM5_RANGE                       9:8
#define GPIO_CC_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CC_VM_00_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM6_SHIFT)
#define GPIO_CC_VM_00_0_VM6_RANGE                       11:10
#define GPIO_CC_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CC_VM_00_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM7_SHIFT)
#define GPIO_CC_VM_00_0_VM7_RANGE                       13:12
#define GPIO_CC_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_00_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CC_VM_00_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_00_0_VM8_SHIFT)
#define GPIO_CC_VM_00_0_VM8_RANGE                       15:14
#define GPIO_CC_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_CC_VM_00_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_00_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_00_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_SCR_00_0
#define GPIO_CC_SCR_00_0                        _MK_ADDR_CONST(0x5084)
#define GPIO_CC_SCR_00_0_SECURE                         0x0
#define GPIO_CC_SCR_00_0_SCR                    0
#define GPIO_CC_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_CC_SCR_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_00_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_00_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_CC_SCR_00_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_CC_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_CC_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_CC_SCR_00_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_CC_SCR_00_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_CC_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_CC_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_CC_SCR_00_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_CC_SCR_00_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_CC_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_CC_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_CC_SCR_00_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_CC_SCR_00_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_CC_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_CC_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_CC_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_CC_SCR_00_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_CC_SCR_00_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_CC_SCR_00_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR7_SHIFT)
#define GPIO_CC_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_CC_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_CC_SCR_00_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR6_SHIFT)
#define GPIO_CC_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_CC_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_CC_SCR_00_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR5_SHIFT)
#define GPIO_CC_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_CC_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_CC_SCR_00_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR4_SHIFT)
#define GPIO_CC_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_CC_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_CC_SCR_00_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR3_SHIFT)
#define GPIO_CC_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_CC_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_CC_SCR_00_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR2_SHIFT)
#define GPIO_CC_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_CC_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_CC_SCR_00_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR1_SHIFT)
#define GPIO_CC_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_CC_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_CC_SCR_00_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_PR0_SHIFT)
#define GPIO_CC_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_CC_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_CC_SCR_00_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G7W_SHIFT)
#define GPIO_CC_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_CC_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_CC_SCR_00_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G6W_SHIFT)
#define GPIO_CC_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_CC_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_CC_SCR_00_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G5W_SHIFT)
#define GPIO_CC_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_CC_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_CC_SCR_00_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G4W_SHIFT)
#define GPIO_CC_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_CC_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_CC_SCR_00_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G3W_SHIFT)
#define GPIO_CC_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_CC_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_CC_SCR_00_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G2W_SHIFT)
#define GPIO_CC_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_CC_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_CC_SCR_00_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G1W_SHIFT)
#define GPIO_CC_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_CC_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_CC_SCR_00_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G0W_SHIFT)
#define GPIO_CC_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_CC_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_CC_SCR_00_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G7R_SHIFT)
#define GPIO_CC_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_CC_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_CC_SCR_00_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G6R_SHIFT)
#define GPIO_CC_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_CC_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_SCR_00_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G5R_SHIFT)
#define GPIO_CC_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_CC_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_CC_SCR_00_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G4R_SHIFT)
#define GPIO_CC_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_CC_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_CC_SCR_00_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G3R_SHIFT)
#define GPIO_CC_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_CC_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_CC_SCR_00_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G2R_SHIFT)
#define GPIO_CC_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_CC_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_CC_SCR_00_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G1R_SHIFT)
#define GPIO_CC_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_CC_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_00_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_SCR_00_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_00_0_G0R_SHIFT)
#define GPIO_CC_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_CC_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_CC_SCR_00_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_00_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_00_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register GPIO_CC_VM_01_0
#define GPIO_CC_VM_01_0                 _MK_ADDR_CONST(0x5088)
#define GPIO_CC_VM_01_0_SECURE                  0x0
#define GPIO_CC_VM_01_0_SCR                     GPIO_CTL5_VM_SCR_0
#define GPIO_CC_VM_01_0_WORD_COUNT                      0x1
#define GPIO_CC_VM_01_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_01_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_01_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_01_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_VM_01_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM1_SHIFT)
#define GPIO_CC_VM_01_0_VM1_RANGE                       1:0
#define GPIO_CC_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CC_VM_01_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM2_SHIFT)
#define GPIO_CC_VM_01_0_VM2_RANGE                       3:2
#define GPIO_CC_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CC_VM_01_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM3_SHIFT)
#define GPIO_CC_VM_01_0_VM3_RANGE                       5:4
#define GPIO_CC_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CC_VM_01_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM4_SHIFT)
#define GPIO_CC_VM_01_0_VM4_RANGE                       7:6
#define GPIO_CC_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CC_VM_01_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM5_SHIFT)
#define GPIO_CC_VM_01_0_VM5_RANGE                       9:8
#define GPIO_CC_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CC_VM_01_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM6_SHIFT)
#define GPIO_CC_VM_01_0_VM6_RANGE                       11:10
#define GPIO_CC_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CC_VM_01_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM7_SHIFT)
#define GPIO_CC_VM_01_0_VM7_RANGE                       13:12
#define GPIO_CC_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_01_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CC_VM_01_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_01_0_VM8_SHIFT)
#define GPIO_CC_VM_01_0_VM8_RANGE                       15:14
#define GPIO_CC_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_CC_VM_01_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_01_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_01_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_SCR_01_0
#define GPIO_CC_SCR_01_0                        _MK_ADDR_CONST(0x508c)
#define GPIO_CC_SCR_01_0_SECURE                         0x0
#define GPIO_CC_SCR_01_0_SCR                    0
#define GPIO_CC_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_CC_SCR_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_01_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_01_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_CC_SCR_01_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_CC_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_CC_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_CC_SCR_01_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_CC_SCR_01_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_CC_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_CC_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_CC_SCR_01_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_CC_SCR_01_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_CC_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_CC_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_CC_SCR_01_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_CC_SCR_01_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_CC_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_CC_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_CC_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_CC_SCR_01_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_CC_SCR_01_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_CC_SCR_01_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR7_SHIFT)
#define GPIO_CC_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_CC_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_CC_SCR_01_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR6_SHIFT)
#define GPIO_CC_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_CC_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_CC_SCR_01_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR5_SHIFT)
#define GPIO_CC_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_CC_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_CC_SCR_01_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR4_SHIFT)
#define GPIO_CC_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_CC_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_CC_SCR_01_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR3_SHIFT)
#define GPIO_CC_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_CC_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_CC_SCR_01_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR2_SHIFT)
#define GPIO_CC_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_CC_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_CC_SCR_01_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR1_SHIFT)
#define GPIO_CC_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_CC_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_CC_SCR_01_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_PR0_SHIFT)
#define GPIO_CC_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_CC_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_CC_SCR_01_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G7W_SHIFT)
#define GPIO_CC_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_CC_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_CC_SCR_01_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G6W_SHIFT)
#define GPIO_CC_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_CC_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_CC_SCR_01_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G5W_SHIFT)
#define GPIO_CC_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_CC_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_CC_SCR_01_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G4W_SHIFT)
#define GPIO_CC_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_CC_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_CC_SCR_01_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G3W_SHIFT)
#define GPIO_CC_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_CC_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_CC_SCR_01_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G2W_SHIFT)
#define GPIO_CC_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_CC_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_CC_SCR_01_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G1W_SHIFT)
#define GPIO_CC_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_CC_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_CC_SCR_01_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G0W_SHIFT)
#define GPIO_CC_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_CC_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_CC_SCR_01_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G7R_SHIFT)
#define GPIO_CC_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_CC_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_CC_SCR_01_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G6R_SHIFT)
#define GPIO_CC_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_CC_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_SCR_01_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G5R_SHIFT)
#define GPIO_CC_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_CC_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_CC_SCR_01_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G4R_SHIFT)
#define GPIO_CC_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_CC_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_CC_SCR_01_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G3R_SHIFT)
#define GPIO_CC_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_CC_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_CC_SCR_01_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G2R_SHIFT)
#define GPIO_CC_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_CC_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_CC_SCR_01_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G1R_SHIFT)
#define GPIO_CC_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_CC_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_01_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_SCR_01_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_01_0_G0R_SHIFT)
#define GPIO_CC_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_CC_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_CC_SCR_01_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_01_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_01_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register GPIO_CC_VM_02_0
#define GPIO_CC_VM_02_0                 _MK_ADDR_CONST(0x5090)
#define GPIO_CC_VM_02_0_SECURE                  0x0
#define GPIO_CC_VM_02_0_SCR                     GPIO_CTL5_VM_SCR_0
#define GPIO_CC_VM_02_0_WORD_COUNT                      0x1
#define GPIO_CC_VM_02_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_02_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_02_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_02_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_VM_02_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM1_SHIFT)
#define GPIO_CC_VM_02_0_VM1_RANGE                       1:0
#define GPIO_CC_VM_02_0_VM1_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CC_VM_02_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM2_SHIFT)
#define GPIO_CC_VM_02_0_VM2_RANGE                       3:2
#define GPIO_CC_VM_02_0_VM2_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CC_VM_02_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM3_SHIFT)
#define GPIO_CC_VM_02_0_VM3_RANGE                       5:4
#define GPIO_CC_VM_02_0_VM3_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CC_VM_02_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM4_SHIFT)
#define GPIO_CC_VM_02_0_VM4_RANGE                       7:6
#define GPIO_CC_VM_02_0_VM4_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CC_VM_02_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM5_SHIFT)
#define GPIO_CC_VM_02_0_VM5_RANGE                       9:8
#define GPIO_CC_VM_02_0_VM5_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CC_VM_02_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM6_SHIFT)
#define GPIO_CC_VM_02_0_VM6_RANGE                       11:10
#define GPIO_CC_VM_02_0_VM6_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CC_VM_02_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM7_SHIFT)
#define GPIO_CC_VM_02_0_VM7_RANGE                       13:12
#define GPIO_CC_VM_02_0_VM7_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_02_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CC_VM_02_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_02_0_VM8_SHIFT)
#define GPIO_CC_VM_02_0_VM8_RANGE                       15:14
#define GPIO_CC_VM_02_0_VM8_WOFFSET                     0x0
#define GPIO_CC_VM_02_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_02_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_02_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_SCR_02_0
#define GPIO_CC_SCR_02_0                        _MK_ADDR_CONST(0x5094)
#define GPIO_CC_SCR_02_0_SECURE                         0x0
#define GPIO_CC_SCR_02_0_SCR                    0
#define GPIO_CC_SCR_02_0_WORD_COUNT                     0x1
#define GPIO_CC_SCR_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_02_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_02_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_CC_SCR_02_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_CC_SCR_02_0_SEC_LCK_RANGE                  29:29
#define GPIO_CC_SCR_02_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_CC_SCR_02_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_CC_SCR_02_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_CC_SCR_02_0_SEC_WEN_RANGE                  28:28
#define GPIO_CC_SCR_02_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_CC_SCR_02_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_CC_SCR_02_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_CC_SCR_02_0_SEC_REN_RANGE                  27:27
#define GPIO_CC_SCR_02_0_SEC_REN_WOFFSET                        0x0
#define GPIO_CC_SCR_02_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_CC_SCR_02_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_CC_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_CC_SCR_02_0_SEC_OWNER_RANGE                        26:24
#define GPIO_CC_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_CC_SCR_02_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_CC_SCR_02_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_CC_SCR_02_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR7_SHIFT)
#define GPIO_CC_SCR_02_0_PR7_RANGE                      23:23
#define GPIO_CC_SCR_02_0_PR7_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_CC_SCR_02_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR6_SHIFT)
#define GPIO_CC_SCR_02_0_PR6_RANGE                      22:22
#define GPIO_CC_SCR_02_0_PR6_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_CC_SCR_02_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR5_SHIFT)
#define GPIO_CC_SCR_02_0_PR5_RANGE                      21:21
#define GPIO_CC_SCR_02_0_PR5_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_CC_SCR_02_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR4_SHIFT)
#define GPIO_CC_SCR_02_0_PR4_RANGE                      20:20
#define GPIO_CC_SCR_02_0_PR4_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_CC_SCR_02_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR3_SHIFT)
#define GPIO_CC_SCR_02_0_PR3_RANGE                      19:19
#define GPIO_CC_SCR_02_0_PR3_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_CC_SCR_02_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR2_SHIFT)
#define GPIO_CC_SCR_02_0_PR2_RANGE                      18:18
#define GPIO_CC_SCR_02_0_PR2_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_CC_SCR_02_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR1_SHIFT)
#define GPIO_CC_SCR_02_0_PR1_RANGE                      17:17
#define GPIO_CC_SCR_02_0_PR1_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_CC_SCR_02_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_PR0_SHIFT)
#define GPIO_CC_SCR_02_0_PR0_RANGE                      16:16
#define GPIO_CC_SCR_02_0_PR0_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_CC_SCR_02_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G7W_SHIFT)
#define GPIO_CC_SCR_02_0_G7W_RANGE                      15:15
#define GPIO_CC_SCR_02_0_G7W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_CC_SCR_02_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G6W_SHIFT)
#define GPIO_CC_SCR_02_0_G6W_RANGE                      14:14
#define GPIO_CC_SCR_02_0_G6W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_CC_SCR_02_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G5W_SHIFT)
#define GPIO_CC_SCR_02_0_G5W_RANGE                      13:13
#define GPIO_CC_SCR_02_0_G5W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_CC_SCR_02_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G4W_SHIFT)
#define GPIO_CC_SCR_02_0_G4W_RANGE                      12:12
#define GPIO_CC_SCR_02_0_G4W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_CC_SCR_02_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G3W_SHIFT)
#define GPIO_CC_SCR_02_0_G3W_RANGE                      11:11
#define GPIO_CC_SCR_02_0_G3W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_CC_SCR_02_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G2W_SHIFT)
#define GPIO_CC_SCR_02_0_G2W_RANGE                      10:10
#define GPIO_CC_SCR_02_0_G2W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_CC_SCR_02_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G1W_SHIFT)
#define GPIO_CC_SCR_02_0_G1W_RANGE                      9:9
#define GPIO_CC_SCR_02_0_G1W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_CC_SCR_02_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G0W_SHIFT)
#define GPIO_CC_SCR_02_0_G0W_RANGE                      8:8
#define GPIO_CC_SCR_02_0_G0W_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_CC_SCR_02_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G7R_SHIFT)
#define GPIO_CC_SCR_02_0_G7R_RANGE                      7:7
#define GPIO_CC_SCR_02_0_G7R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_CC_SCR_02_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G6R_SHIFT)
#define GPIO_CC_SCR_02_0_G6R_RANGE                      6:6
#define GPIO_CC_SCR_02_0_G6R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_SCR_02_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G5R_SHIFT)
#define GPIO_CC_SCR_02_0_G5R_RANGE                      5:5
#define GPIO_CC_SCR_02_0_G5R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_CC_SCR_02_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G4R_SHIFT)
#define GPIO_CC_SCR_02_0_G4R_RANGE                      4:4
#define GPIO_CC_SCR_02_0_G4R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_CC_SCR_02_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G3R_SHIFT)
#define GPIO_CC_SCR_02_0_G3R_RANGE                      3:3
#define GPIO_CC_SCR_02_0_G3R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_CC_SCR_02_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G2R_SHIFT)
#define GPIO_CC_SCR_02_0_G2R_RANGE                      2:2
#define GPIO_CC_SCR_02_0_G2R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_CC_SCR_02_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G1R_SHIFT)
#define GPIO_CC_SCR_02_0_G1R_RANGE                      1:1
#define GPIO_CC_SCR_02_0_G1R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_02_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_SCR_02_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_02_0_G0R_SHIFT)
#define GPIO_CC_SCR_02_0_G0R_RANGE                      0:0
#define GPIO_CC_SCR_02_0_G0R_WOFFSET                    0x0
#define GPIO_CC_SCR_02_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_02_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_02_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register GPIO_CC_VM_03_0
#define GPIO_CC_VM_03_0                 _MK_ADDR_CONST(0x5098)
#define GPIO_CC_VM_03_0_SECURE                  0x0
#define GPIO_CC_VM_03_0_SCR                     GPIO_CTL5_VM_SCR_0
#define GPIO_CC_VM_03_0_WORD_COUNT                      0x1
#define GPIO_CC_VM_03_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_03_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_03_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_CC_VM_03_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_VM_03_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM1_SHIFT)
#define GPIO_CC_VM_03_0_VM1_RANGE                       1:0
#define GPIO_CC_VM_03_0_VM1_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CC_VM_03_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM2_SHIFT)
#define GPIO_CC_VM_03_0_VM2_RANGE                       3:2
#define GPIO_CC_VM_03_0_VM2_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CC_VM_03_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM3_SHIFT)
#define GPIO_CC_VM_03_0_VM3_RANGE                       5:4
#define GPIO_CC_VM_03_0_VM3_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CC_VM_03_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM4_SHIFT)
#define GPIO_CC_VM_03_0_VM4_RANGE                       7:6
#define GPIO_CC_VM_03_0_VM4_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CC_VM_03_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM5_SHIFT)
#define GPIO_CC_VM_03_0_VM5_RANGE                       9:8
#define GPIO_CC_VM_03_0_VM5_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CC_VM_03_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM6_SHIFT)
#define GPIO_CC_VM_03_0_VM6_RANGE                       11:10
#define GPIO_CC_VM_03_0_VM6_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CC_VM_03_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM7_SHIFT)
#define GPIO_CC_VM_03_0_VM7_RANGE                       13:12
#define GPIO_CC_VM_03_0_VM7_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CC_VM_03_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CC_VM_03_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_CC_VM_03_0_VM8_SHIFT)
#define GPIO_CC_VM_03_0_VM8_RANGE                       15:14
#define GPIO_CC_VM_03_0_VM8_WOFFSET                     0x0
#define GPIO_CC_VM_03_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_CC_VM_03_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_VM_03_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_SCR_03_0
#define GPIO_CC_SCR_03_0                        _MK_ADDR_CONST(0x509c)
#define GPIO_CC_SCR_03_0_SECURE                         0x0
#define GPIO_CC_SCR_03_0_SCR                    0
#define GPIO_CC_SCR_03_0_WORD_COUNT                     0x1
#define GPIO_CC_SCR_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_03_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_CC_SCR_03_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_CC_SCR_03_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_CC_SCR_03_0_SEC_LCK_RANGE                  29:29
#define GPIO_CC_SCR_03_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_CC_SCR_03_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_CC_SCR_03_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_CC_SCR_03_0_SEC_WEN_RANGE                  28:28
#define GPIO_CC_SCR_03_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_CC_SCR_03_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_CC_SCR_03_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_CC_SCR_03_0_SEC_REN_RANGE                  27:27
#define GPIO_CC_SCR_03_0_SEC_REN_WOFFSET                        0x0
#define GPIO_CC_SCR_03_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_CC_SCR_03_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_CC_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_CC_SCR_03_0_SEC_OWNER_RANGE                        26:24
#define GPIO_CC_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_CC_SCR_03_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_CC_SCR_03_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_CC_SCR_03_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR7_SHIFT)
#define GPIO_CC_SCR_03_0_PR7_RANGE                      23:23
#define GPIO_CC_SCR_03_0_PR7_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_CC_SCR_03_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR6_SHIFT)
#define GPIO_CC_SCR_03_0_PR6_RANGE                      22:22
#define GPIO_CC_SCR_03_0_PR6_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_CC_SCR_03_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR5_SHIFT)
#define GPIO_CC_SCR_03_0_PR5_RANGE                      21:21
#define GPIO_CC_SCR_03_0_PR5_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_CC_SCR_03_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR4_SHIFT)
#define GPIO_CC_SCR_03_0_PR4_RANGE                      20:20
#define GPIO_CC_SCR_03_0_PR4_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_CC_SCR_03_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR3_SHIFT)
#define GPIO_CC_SCR_03_0_PR3_RANGE                      19:19
#define GPIO_CC_SCR_03_0_PR3_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_CC_SCR_03_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR2_SHIFT)
#define GPIO_CC_SCR_03_0_PR2_RANGE                      18:18
#define GPIO_CC_SCR_03_0_PR2_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_CC_SCR_03_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR1_SHIFT)
#define GPIO_CC_SCR_03_0_PR1_RANGE                      17:17
#define GPIO_CC_SCR_03_0_PR1_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_CC_SCR_03_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_PR0_SHIFT)
#define GPIO_CC_SCR_03_0_PR0_RANGE                      16:16
#define GPIO_CC_SCR_03_0_PR0_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_CC_SCR_03_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G7W_SHIFT)
#define GPIO_CC_SCR_03_0_G7W_RANGE                      15:15
#define GPIO_CC_SCR_03_0_G7W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_CC_SCR_03_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G6W_SHIFT)
#define GPIO_CC_SCR_03_0_G6W_RANGE                      14:14
#define GPIO_CC_SCR_03_0_G6W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_CC_SCR_03_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G5W_SHIFT)
#define GPIO_CC_SCR_03_0_G5W_RANGE                      13:13
#define GPIO_CC_SCR_03_0_G5W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_CC_SCR_03_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G4W_SHIFT)
#define GPIO_CC_SCR_03_0_G4W_RANGE                      12:12
#define GPIO_CC_SCR_03_0_G4W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_CC_SCR_03_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G3W_SHIFT)
#define GPIO_CC_SCR_03_0_G3W_RANGE                      11:11
#define GPIO_CC_SCR_03_0_G3W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_CC_SCR_03_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G2W_SHIFT)
#define GPIO_CC_SCR_03_0_G2W_RANGE                      10:10
#define GPIO_CC_SCR_03_0_G2W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_CC_SCR_03_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G1W_SHIFT)
#define GPIO_CC_SCR_03_0_G1W_RANGE                      9:9
#define GPIO_CC_SCR_03_0_G1W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_CC_SCR_03_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G0W_SHIFT)
#define GPIO_CC_SCR_03_0_G0W_RANGE                      8:8
#define GPIO_CC_SCR_03_0_G0W_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_CC_SCR_03_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G7R_SHIFT)
#define GPIO_CC_SCR_03_0_G7R_RANGE                      7:7
#define GPIO_CC_SCR_03_0_G7R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_CC_SCR_03_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G6R_SHIFT)
#define GPIO_CC_SCR_03_0_G6R_RANGE                      6:6
#define GPIO_CC_SCR_03_0_G6R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_SCR_03_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G5R_SHIFT)
#define GPIO_CC_SCR_03_0_G5R_RANGE                      5:5
#define GPIO_CC_SCR_03_0_G5R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_CC_SCR_03_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G4R_SHIFT)
#define GPIO_CC_SCR_03_0_G4R_RANGE                      4:4
#define GPIO_CC_SCR_03_0_G4R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_CC_SCR_03_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G3R_SHIFT)
#define GPIO_CC_SCR_03_0_G3R_RANGE                      3:3
#define GPIO_CC_SCR_03_0_G3R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_CC_SCR_03_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G2R_SHIFT)
#define GPIO_CC_SCR_03_0_G2R_RANGE                      2:2
#define GPIO_CC_SCR_03_0_G2R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_CC_SCR_03_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G1R_SHIFT)
#define GPIO_CC_SCR_03_0_G1R_RANGE                      1:1
#define GPIO_CC_SCR_03_0_G1R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CC_SCR_03_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_SCR_03_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_SCR_03_0_G0R_SHIFT)
#define GPIO_CC_SCR_03_0_G0R_RANGE                      0:0
#define GPIO_CC_SCR_03_0_G0R_WOFFSET                    0x0
#define GPIO_CC_SCR_03_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_SCR_03_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_SCR_03_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 20640 [0x50a0]

// Reserved address 20644 [0x50a4]

// Reserved address 20648 [0x50a8]

// Reserved address 20652 [0x50ac]

// Reserved address 20656 [0x50b0]

// Reserved address 20660 [0x50b4]

// Reserved address 20664 [0x50b8]

// Reserved address 20668 [0x50bc]

// Register GPIO_M_VM_00_0
#define GPIO_M_VM_00_0                  _MK_ADDR_CONST(0x50c0)
#define GPIO_M_VM_00_0_SECURE                   0x0
#define GPIO_M_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_00_0_WORD_COUNT                       0x1
#define GPIO_M_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM1_SHIFT)
#define GPIO_M_VM_00_0_VM1_RANGE                        1:0
#define GPIO_M_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM2_SHIFT)
#define GPIO_M_VM_00_0_VM2_RANGE                        3:2
#define GPIO_M_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM3_SHIFT)
#define GPIO_M_VM_00_0_VM3_RANGE                        5:4
#define GPIO_M_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM4_SHIFT)
#define GPIO_M_VM_00_0_VM4_RANGE                        7:6
#define GPIO_M_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM5_SHIFT)
#define GPIO_M_VM_00_0_VM5_RANGE                        9:8
#define GPIO_M_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM6_SHIFT)
#define GPIO_M_VM_00_0_VM6_RANGE                        11:10
#define GPIO_M_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM7_SHIFT)
#define GPIO_M_VM_00_0_VM7_RANGE                        13:12
#define GPIO_M_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM8_SHIFT)
#define GPIO_M_VM_00_0_VM8_RANGE                        15:14
#define GPIO_M_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_00_0
#define GPIO_M_SCR_00_0                 _MK_ADDR_CONST(0x50c4)
#define GPIO_M_SCR_00_0_SECURE                  0x0
#define GPIO_M_SCR_00_0_SCR                     0
#define GPIO_M_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR7_SHIFT)
#define GPIO_M_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR6_SHIFT)
#define GPIO_M_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR5_SHIFT)
#define GPIO_M_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR4_SHIFT)
#define GPIO_M_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR3_SHIFT)
#define GPIO_M_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR2_SHIFT)
#define GPIO_M_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR1_SHIFT)
#define GPIO_M_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR0_SHIFT)
#define GPIO_M_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7W_SHIFT)
#define GPIO_M_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6W_SHIFT)
#define GPIO_M_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5W_SHIFT)
#define GPIO_M_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4W_SHIFT)
#define GPIO_M_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3W_SHIFT)
#define GPIO_M_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2W_SHIFT)
#define GPIO_M_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1W_SHIFT)
#define GPIO_M_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0W_SHIFT)
#define GPIO_M_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7R_SHIFT)
#define GPIO_M_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6R_SHIFT)
#define GPIO_M_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5R_SHIFT)
#define GPIO_M_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4R_SHIFT)
#define GPIO_M_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3R_SHIFT)
#define GPIO_M_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2R_SHIFT)
#define GPIO_M_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1R_SHIFT)
#define GPIO_M_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0R_SHIFT)
#define GPIO_M_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_M_VM_01_0
#define GPIO_M_VM_01_0                  _MK_ADDR_CONST(0x50c8)
#define GPIO_M_VM_01_0_SECURE                   0x0
#define GPIO_M_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_01_0_WORD_COUNT                       0x1
#define GPIO_M_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM1_SHIFT)
#define GPIO_M_VM_01_0_VM1_RANGE                        1:0
#define GPIO_M_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM2_SHIFT)
#define GPIO_M_VM_01_0_VM2_RANGE                        3:2
#define GPIO_M_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM3_SHIFT)
#define GPIO_M_VM_01_0_VM3_RANGE                        5:4
#define GPIO_M_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM4_SHIFT)
#define GPIO_M_VM_01_0_VM4_RANGE                        7:6
#define GPIO_M_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM5_SHIFT)
#define GPIO_M_VM_01_0_VM5_RANGE                        9:8
#define GPIO_M_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM6_SHIFT)
#define GPIO_M_VM_01_0_VM6_RANGE                        11:10
#define GPIO_M_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM7_SHIFT)
#define GPIO_M_VM_01_0_VM7_RANGE                        13:12
#define GPIO_M_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM8_SHIFT)
#define GPIO_M_VM_01_0_VM8_RANGE                        15:14
#define GPIO_M_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_01_0
#define GPIO_M_SCR_01_0                 _MK_ADDR_CONST(0x50cc)
#define GPIO_M_SCR_01_0_SECURE                  0x0
#define GPIO_M_SCR_01_0_SCR                     0
#define GPIO_M_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR7_SHIFT)
#define GPIO_M_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR6_SHIFT)
#define GPIO_M_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR5_SHIFT)
#define GPIO_M_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR4_SHIFT)
#define GPIO_M_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR3_SHIFT)
#define GPIO_M_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR2_SHIFT)
#define GPIO_M_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR1_SHIFT)
#define GPIO_M_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR0_SHIFT)
#define GPIO_M_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7W_SHIFT)
#define GPIO_M_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6W_SHIFT)
#define GPIO_M_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5W_SHIFT)
#define GPIO_M_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4W_SHIFT)
#define GPIO_M_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3W_SHIFT)
#define GPIO_M_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2W_SHIFT)
#define GPIO_M_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1W_SHIFT)
#define GPIO_M_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0W_SHIFT)
#define GPIO_M_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7R_SHIFT)
#define GPIO_M_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6R_SHIFT)
#define GPIO_M_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5R_SHIFT)
#define GPIO_M_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4R_SHIFT)
#define GPIO_M_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3R_SHIFT)
#define GPIO_M_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2R_SHIFT)
#define GPIO_M_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1R_SHIFT)
#define GPIO_M_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0R_SHIFT)
#define GPIO_M_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_M_VM_02_0
#define GPIO_M_VM_02_0                  _MK_ADDR_CONST(0x50d0)
#define GPIO_M_VM_02_0_SECURE                   0x0
#define GPIO_M_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_02_0_WORD_COUNT                       0x1
#define GPIO_M_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM1_SHIFT)
#define GPIO_M_VM_02_0_VM1_RANGE                        1:0
#define GPIO_M_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM2_SHIFT)
#define GPIO_M_VM_02_0_VM2_RANGE                        3:2
#define GPIO_M_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM3_SHIFT)
#define GPIO_M_VM_02_0_VM3_RANGE                        5:4
#define GPIO_M_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM4_SHIFT)
#define GPIO_M_VM_02_0_VM4_RANGE                        7:6
#define GPIO_M_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM5_SHIFT)
#define GPIO_M_VM_02_0_VM5_RANGE                        9:8
#define GPIO_M_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM6_SHIFT)
#define GPIO_M_VM_02_0_VM6_RANGE                        11:10
#define GPIO_M_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM7_SHIFT)
#define GPIO_M_VM_02_0_VM7_RANGE                        13:12
#define GPIO_M_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM8_SHIFT)
#define GPIO_M_VM_02_0_VM8_RANGE                        15:14
#define GPIO_M_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_02_0
#define GPIO_M_SCR_02_0                 _MK_ADDR_CONST(0x50d4)
#define GPIO_M_SCR_02_0_SECURE                  0x0
#define GPIO_M_SCR_02_0_SCR                     0
#define GPIO_M_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR7_SHIFT)
#define GPIO_M_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR6_SHIFT)
#define GPIO_M_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR5_SHIFT)
#define GPIO_M_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR4_SHIFT)
#define GPIO_M_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR3_SHIFT)
#define GPIO_M_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR2_SHIFT)
#define GPIO_M_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR1_SHIFT)
#define GPIO_M_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR0_SHIFT)
#define GPIO_M_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7W_SHIFT)
#define GPIO_M_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6W_SHIFT)
#define GPIO_M_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5W_SHIFT)
#define GPIO_M_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4W_SHIFT)
#define GPIO_M_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3W_SHIFT)
#define GPIO_M_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2W_SHIFT)
#define GPIO_M_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1W_SHIFT)
#define GPIO_M_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0W_SHIFT)
#define GPIO_M_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7R_SHIFT)
#define GPIO_M_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6R_SHIFT)
#define GPIO_M_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5R_SHIFT)
#define GPIO_M_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4R_SHIFT)
#define GPIO_M_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3R_SHIFT)
#define GPIO_M_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2R_SHIFT)
#define GPIO_M_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1R_SHIFT)
#define GPIO_M_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0R_SHIFT)
#define GPIO_M_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_M_VM_03_0
#define GPIO_M_VM_03_0                  _MK_ADDR_CONST(0x50d8)
#define GPIO_M_VM_03_0_SECURE                   0x0
#define GPIO_M_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_03_0_WORD_COUNT                       0x1
#define GPIO_M_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM1_SHIFT)
#define GPIO_M_VM_03_0_VM1_RANGE                        1:0
#define GPIO_M_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM2_SHIFT)
#define GPIO_M_VM_03_0_VM2_RANGE                        3:2
#define GPIO_M_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM3_SHIFT)
#define GPIO_M_VM_03_0_VM3_RANGE                        5:4
#define GPIO_M_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM4_SHIFT)
#define GPIO_M_VM_03_0_VM4_RANGE                        7:6
#define GPIO_M_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM5_SHIFT)
#define GPIO_M_VM_03_0_VM5_RANGE                        9:8
#define GPIO_M_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM6_SHIFT)
#define GPIO_M_VM_03_0_VM6_RANGE                        11:10
#define GPIO_M_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM7_SHIFT)
#define GPIO_M_VM_03_0_VM7_RANGE                        13:12
#define GPIO_M_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM8_SHIFT)
#define GPIO_M_VM_03_0_VM8_RANGE                        15:14
#define GPIO_M_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_03_0
#define GPIO_M_SCR_03_0                 _MK_ADDR_CONST(0x50dc)
#define GPIO_M_SCR_03_0_SECURE                  0x0
#define GPIO_M_SCR_03_0_SCR                     0
#define GPIO_M_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR7_SHIFT)
#define GPIO_M_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR6_SHIFT)
#define GPIO_M_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR5_SHIFT)
#define GPIO_M_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR4_SHIFT)
#define GPIO_M_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR3_SHIFT)
#define GPIO_M_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR2_SHIFT)
#define GPIO_M_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR1_SHIFT)
#define GPIO_M_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR0_SHIFT)
#define GPIO_M_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7W_SHIFT)
#define GPIO_M_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6W_SHIFT)
#define GPIO_M_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5W_SHIFT)
#define GPIO_M_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4W_SHIFT)
#define GPIO_M_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3W_SHIFT)
#define GPIO_M_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2W_SHIFT)
#define GPIO_M_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1W_SHIFT)
#define GPIO_M_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0W_SHIFT)
#define GPIO_M_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7R_SHIFT)
#define GPIO_M_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6R_SHIFT)
#define GPIO_M_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5R_SHIFT)
#define GPIO_M_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4R_SHIFT)
#define GPIO_M_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3R_SHIFT)
#define GPIO_M_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2R_SHIFT)
#define GPIO_M_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1R_SHIFT)
#define GPIO_M_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0R_SHIFT)
#define GPIO_M_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_M_VM_04_0
#define GPIO_M_VM_04_0                  _MK_ADDR_CONST(0x50e0)
#define GPIO_M_VM_04_0_SECURE                   0x0
#define GPIO_M_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_04_0_WORD_COUNT                       0x1
#define GPIO_M_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM1_SHIFT)
#define GPIO_M_VM_04_0_VM1_RANGE                        1:0
#define GPIO_M_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM2_SHIFT)
#define GPIO_M_VM_04_0_VM2_RANGE                        3:2
#define GPIO_M_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM3_SHIFT)
#define GPIO_M_VM_04_0_VM3_RANGE                        5:4
#define GPIO_M_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM4_SHIFT)
#define GPIO_M_VM_04_0_VM4_RANGE                        7:6
#define GPIO_M_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM5_SHIFT)
#define GPIO_M_VM_04_0_VM5_RANGE                        9:8
#define GPIO_M_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM6_SHIFT)
#define GPIO_M_VM_04_0_VM6_RANGE                        11:10
#define GPIO_M_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM7_SHIFT)
#define GPIO_M_VM_04_0_VM7_RANGE                        13:12
#define GPIO_M_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM8_SHIFT)
#define GPIO_M_VM_04_0_VM8_RANGE                        15:14
#define GPIO_M_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_04_0
#define GPIO_M_SCR_04_0                 _MK_ADDR_CONST(0x50e4)
#define GPIO_M_SCR_04_0_SECURE                  0x0
#define GPIO_M_SCR_04_0_SCR                     0
#define GPIO_M_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR7_SHIFT)
#define GPIO_M_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR6_SHIFT)
#define GPIO_M_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR5_SHIFT)
#define GPIO_M_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR4_SHIFT)
#define GPIO_M_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR3_SHIFT)
#define GPIO_M_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR2_SHIFT)
#define GPIO_M_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR1_SHIFT)
#define GPIO_M_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR0_SHIFT)
#define GPIO_M_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7W_SHIFT)
#define GPIO_M_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6W_SHIFT)
#define GPIO_M_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5W_SHIFT)
#define GPIO_M_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4W_SHIFT)
#define GPIO_M_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3W_SHIFT)
#define GPIO_M_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2W_SHIFT)
#define GPIO_M_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1W_SHIFT)
#define GPIO_M_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0W_SHIFT)
#define GPIO_M_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7R_SHIFT)
#define GPIO_M_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6R_SHIFT)
#define GPIO_M_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5R_SHIFT)
#define GPIO_M_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4R_SHIFT)
#define GPIO_M_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3R_SHIFT)
#define GPIO_M_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2R_SHIFT)
#define GPIO_M_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1R_SHIFT)
#define GPIO_M_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0R_SHIFT)
#define GPIO_M_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_M_VM_05_0
#define GPIO_M_VM_05_0                  _MK_ADDR_CONST(0x50e8)
#define GPIO_M_VM_05_0_SECURE                   0x0
#define GPIO_M_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_M_VM_05_0_WORD_COUNT                       0x1
#define GPIO_M_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM1_SHIFT)
#define GPIO_M_VM_05_0_VM1_RANGE                        1:0
#define GPIO_M_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM2_SHIFT)
#define GPIO_M_VM_05_0_VM2_RANGE                        3:2
#define GPIO_M_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM3_SHIFT)
#define GPIO_M_VM_05_0_VM3_RANGE                        5:4
#define GPIO_M_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM4_SHIFT)
#define GPIO_M_VM_05_0_VM4_RANGE                        7:6
#define GPIO_M_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM5_SHIFT)
#define GPIO_M_VM_05_0_VM5_RANGE                        9:8
#define GPIO_M_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM6_SHIFT)
#define GPIO_M_VM_05_0_VM6_RANGE                        11:10
#define GPIO_M_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM7_SHIFT)
#define GPIO_M_VM_05_0_VM7_RANGE                        13:12
#define GPIO_M_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_M_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM8_SHIFT)
#define GPIO_M_VM_05_0_VM8_RANGE                        15:14
#define GPIO_M_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_SCR_05_0
#define GPIO_M_SCR_05_0                 _MK_ADDR_CONST(0x50ec)
#define GPIO_M_SCR_05_0_SECURE                  0x0
#define GPIO_M_SCR_05_0_SCR                     0
#define GPIO_M_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR7_SHIFT)
#define GPIO_M_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR6_SHIFT)
#define GPIO_M_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR5_SHIFT)
#define GPIO_M_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR4_SHIFT)
#define GPIO_M_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR3_SHIFT)
#define GPIO_M_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR2_SHIFT)
#define GPIO_M_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR1_SHIFT)
#define GPIO_M_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR0_SHIFT)
#define GPIO_M_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7W_SHIFT)
#define GPIO_M_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6W_SHIFT)
#define GPIO_M_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5W_SHIFT)
#define GPIO_M_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4W_SHIFT)
#define GPIO_M_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3W_SHIFT)
#define GPIO_M_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2W_SHIFT)
#define GPIO_M_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1W_SHIFT)
#define GPIO_M_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0W_SHIFT)
#define GPIO_M_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7R_SHIFT)
#define GPIO_M_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6R_SHIFT)
#define GPIO_M_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5R_SHIFT)
#define GPIO_M_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4R_SHIFT)
#define GPIO_M_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3R_SHIFT)
#define GPIO_M_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2R_SHIFT)
#define GPIO_M_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1R_SHIFT)
#define GPIO_M_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_M_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0R_SHIFT)
#define GPIO_M_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 20720 [0x50f0]

// Reserved address 20724 [0x50f4]

// Reserved address 20728 [0x50f8]

// Reserved address 20732 [0x50fc]

// Register GPIO_CTL5_VM_SCR_0
#define GPIO_CTL5_VM_SCR_0                      _MK_ADDR_CONST(0x5800)
#define GPIO_CTL5_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL5_VM_SCR_0_SCR                  0
#define GPIO_CTL5_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL5_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL5_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL5_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL5_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL5_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL5_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL5_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL5_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL5_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL5_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL5_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL5_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL5_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL5_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL5_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL5_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL5_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL5_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL5_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL5_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL5_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL5_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL5_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL5_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL5_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL5_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL5_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL5_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL5_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL5_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL5_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL5_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL5_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL5_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL5_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL5_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL5_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL5_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL5_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL5_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL5_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL5_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL5_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL5_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL5_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL5_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL5_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL5_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define GPIO_CTL5_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL5_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL5_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x5804)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x5808)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL5_SCR_0
#define GPIO_CTL5_SCR_0                 _MK_ADDR_CONST(0x580c)
#define GPIO_CTL5_SCR_0_SECURE                  0x0
#define GPIO_CTL5_SCR_0_SCR                     0
#define GPIO_CTL5_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL5_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL5_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL5_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL5_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL5_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL5_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL5_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL5_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL5_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL5_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL5_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL5_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL5_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL5_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL5_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL5_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL5_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL5_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL5_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL5_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL5_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL5_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL5_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL5_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL5_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL5_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL5_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL5_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL5_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL5_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL5_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL5_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL5_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL5_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL5_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL5_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL5_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL5_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL5_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL5_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL5_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL5_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL5_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL5_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL5_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL5_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL5_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL5_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL5_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL5_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL5_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL5_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL5_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL5_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL5_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define GPIO_CTL5_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL5_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL5_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CTL5_ICG_EN_OVERRIDE_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x5810)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register GPIO_CTL5_SPARE_0
#define GPIO_CTL5_SPARE_0                       _MK_ADDR_CONST(0x5814)
#define GPIO_CTL5_SPARE_0_SECURE                        0x0
#define GPIO_CTL5_SPARE_0_SCR                   0
#define GPIO_CTL5_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL5_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL5_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL5_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL5_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL5_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register GPIO_N_ENABLE_CONFIG_00_0
#define GPIO_N_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10000)
#define GPIO_N_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10004)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_N_SCR_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_00_0
#define GPIO_N_INPUT_00_0                       _MK_ADDR_CONST(0x10008)
#define GPIO_N_INPUT_00_0_SECURE                        0x0
#define GPIO_N_INPUT_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1000c)
#define GPIO_N_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_SCR                  GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_00_0
#define GPIO_N_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10010)
#define GPIO_N_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_00_0_SCR                    GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10014)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_SCR                         GPIO_N_SCR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65560 [0x10018]

// Reserved address 65564 [0x1001c]

// Register GPIO_N_ENABLE_CONFIG_01_0
#define GPIO_N_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10020)
#define GPIO_N_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10024)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_N_SCR_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_01_0
#define GPIO_N_INPUT_01_0                       _MK_ADDR_CONST(0x10028)
#define GPIO_N_INPUT_01_0_SECURE                        0x0
#define GPIO_N_INPUT_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1002c)
#define GPIO_N_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_SCR                  GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_01_0
#define GPIO_N_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10030)
#define GPIO_N_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_01_0_SCR                    GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10034)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_SCR                         GPIO_N_SCR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65592 [0x10038]

// Reserved address 65596 [0x1003c]

// Register GPIO_N_ENABLE_CONFIG_02_0
#define GPIO_N_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10040)
#define GPIO_N_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10044)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_N_SCR_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_02_0
#define GPIO_N_INPUT_02_0                       _MK_ADDR_CONST(0x10048)
#define GPIO_N_INPUT_02_0_SECURE                        0x0
#define GPIO_N_INPUT_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1004c)
#define GPIO_N_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_SCR                  GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_02_0
#define GPIO_N_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10050)
#define GPIO_N_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_02_0_SCR                    GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10054)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_SCR                         GPIO_N_SCR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65624 [0x10058]

// Reserved address 65628 [0x1005c]

// Register GPIO_N_ENABLE_CONFIG_03_0
#define GPIO_N_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10060)
#define GPIO_N_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_03_0_SCR                   GPIO_N_SCR_03_0
#define GPIO_N_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_03_0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10064)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_N_SCR_03_0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_03_0
#define GPIO_N_INPUT_03_0                       _MK_ADDR_CONST(0x10068)
#define GPIO_N_INPUT_03_0_SECURE                        0x0
#define GPIO_N_INPUT_03_0_SCR                   GPIO_N_SCR_03_0
#define GPIO_N_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_03_0
#define GPIO_N_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1006c)
#define GPIO_N_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_03_0_SCR                  GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_03_0
#define GPIO_N_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10070)
#define GPIO_N_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_03_0_SCR                    GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_03_0
#define GPIO_N_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10074)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_03_0_SCR                         GPIO_N_SCR_03_0
#define GPIO_N_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65656 [0x10078]

// Reserved address 65660 [0x1007c]

// Register GPIO_N_ENABLE_CONFIG_04_0
#define GPIO_N_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x10080)
#define GPIO_N_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_04_0_SCR                   GPIO_N_SCR_04_0
#define GPIO_N_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_04_0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x10084)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_N_SCR_04_0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_04_0
#define GPIO_N_INPUT_04_0                       _MK_ADDR_CONST(0x10088)
#define GPIO_N_INPUT_04_0_SECURE                        0x0
#define GPIO_N_INPUT_04_0_SCR                   GPIO_N_SCR_04_0
#define GPIO_N_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_04_0
#define GPIO_N_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1008c)
#define GPIO_N_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_04_0_SCR                  GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_04_0
#define GPIO_N_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x10090)
#define GPIO_N_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_04_0_SCR                    GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_04_0
#define GPIO_N_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x10094)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_04_0_SCR                         GPIO_N_SCR_04_0
#define GPIO_N_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65688 [0x10098]

// Reserved address 65692 [0x1009c]

// Register GPIO_N_ENABLE_CONFIG_05_0
#define GPIO_N_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x100a0)
#define GPIO_N_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_05_0_SCR                   GPIO_N_SCR_05_0
#define GPIO_N_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_05_0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x100a4)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_N_SCR_05_0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_05_0
#define GPIO_N_INPUT_05_0                       _MK_ADDR_CONST(0x100a8)
#define GPIO_N_INPUT_05_0_SECURE                        0x0
#define GPIO_N_INPUT_05_0_SCR                   GPIO_N_SCR_05_0
#define GPIO_N_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_05_0
#define GPIO_N_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x100ac)
#define GPIO_N_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_05_0_SCR                  GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_05_0
#define GPIO_N_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x100b0)
#define GPIO_N_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_05_0_SCR                    GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_05_0
#define GPIO_N_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x100b4)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_05_0_SCR                         GPIO_N_SCR_05_0
#define GPIO_N_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65720 [0x100b8]

// Reserved address 65724 [0x100bc]

// Register GPIO_N_ENABLE_CONFIG_06_0
#define GPIO_N_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x100c0)
#define GPIO_N_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_06_0_SCR                   GPIO_N_SCR_06_0
#define GPIO_N_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_06_0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x100c4)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_N_SCR_06_0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_INPUT_06_0
#define GPIO_N_INPUT_06_0                       _MK_ADDR_CONST(0x100c8)
#define GPIO_N_INPUT_06_0_SECURE                        0x0
#define GPIO_N_INPUT_06_0_SCR                   GPIO_N_SCR_06_0
#define GPIO_N_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_N_OUTPUT_CONTROL_06_0
#define GPIO_N_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x100cc)
#define GPIO_N_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_06_0_SCR                  GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_06_0
#define GPIO_N_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x100d0)
#define GPIO_N_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_06_0_SCR                    GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_CLEAR_06_0
#define GPIO_N_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x100d4)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_06_0_SCR                         GPIO_N_SCR_06_0
#define GPIO_N_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 65752 [0x100d8]

// Reserved address 65756 [0x100dc]

// Reserved address 65760 [0x100e0]

// Reserved address 65764 [0x100e4]

// Reserved address 65768 [0x100e8]

// Reserved address 65772 [0x100ec]

// Reserved address 65776 [0x100f0]

// Reserved address 65780 [0x100f4]

// Reserved address 65784 [0x100f8]

// Reserved address 65788 [0x100fc]

// Register GPIO_N_INTERRUPT_STATUS_G0_0
#define GPIO_N_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10100)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G1_0
#define GPIO_N_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10104)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G2_0
#define GPIO_N_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10108)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G3_0
#define GPIO_N_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1010c)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G4_0
#define GPIO_N_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10110)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G5_0
#define GPIO_N_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10114)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G6_0
#define GPIO_N_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10118)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_N_INTERRUPT_STATUS_G7_0
#define GPIO_N_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1011c)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 65824 [0x10120]

// Reserved address 65828 [0x10124]

// Reserved address 65832 [0x10128]

// Reserved address 65836 [0x1012c]

// Reserved address 65840 [0x10130]

// Reserved address 65844 [0x10134]

// Reserved address 65848 [0x10138]

// Reserved address 65852 [0x1013c]

// Reserved address 65856 [0x10140]

// Reserved address 65860 [0x10144]

// Reserved address 65864 [0x10148]

// Reserved address 65868 [0x1014c]

// Reserved address 65872 [0x10150]

// Reserved address 65876 [0x10154]

// Reserved address 65880 [0x10158]

// Reserved address 65884 [0x1015c]

// Reserved address 65888 [0x10160]

// Reserved address 65892 [0x10164]

// Reserved address 65896 [0x10168]

// Reserved address 65900 [0x1016c]

// Reserved address 65904 [0x10170]

// Reserved address 65908 [0x10174]

// Reserved address 65912 [0x10178]

// Reserved address 65916 [0x1017c]

// Reserved address 65920 [0x10180]

// Reserved address 65924 [0x10184]

// Reserved address 65928 [0x10188]

// Reserved address 65932 [0x1018c]

// Reserved address 65936 [0x10190]

// Reserved address 65940 [0x10194]

// Reserved address 65944 [0x10198]

// Reserved address 65948 [0x1019c]

// Reserved address 65952 [0x101a0]

// Reserved address 65956 [0x101a4]

// Reserved address 65960 [0x101a8]

// Reserved address 65964 [0x101ac]

// Reserved address 65968 [0x101b0]

// Reserved address 65972 [0x101b4]

// Reserved address 65976 [0x101b8]

// Reserved address 65980 [0x101bc]

// Reserved address 65984 [0x101c0]

// Reserved address 65988 [0x101c4]

// Reserved address 65992 [0x101c8]

// Reserved address 65996 [0x101cc]

// Reserved address 66000 [0x101d0]

// Reserved address 66004 [0x101d4]

// Reserved address 66008 [0x101d8]

// Reserved address 66012 [0x101dc]

// Reserved address 66016 [0x101e0]

// Reserved address 66020 [0x101e4]

// Reserved address 66024 [0x101e8]

// Reserved address 66028 [0x101ec]

// Reserved address 66032 [0x101f0]

// Reserved address 66036 [0x101f4]

// Reserved address 66040 [0x101f8]

// Reserved address 66044 [0x101fc]

// Register GPIO_O_ENABLE_CONFIG_00_0
#define GPIO_O_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10200)
#define GPIO_O_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_00_0_SCR                   GPIO_O_SCR_00_0
#define GPIO_O_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_00_0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10204)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_O_SCR_00_0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_INPUT_00_0
#define GPIO_O_INPUT_00_0                       _MK_ADDR_CONST(0x10208)
#define GPIO_O_INPUT_00_0_SECURE                        0x0
#define GPIO_O_INPUT_00_0_SCR                   GPIO_O_SCR_00_0
#define GPIO_O_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_OUTPUT_CONTROL_00_0
#define GPIO_O_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1020c)
#define GPIO_O_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_00_0_SCR                  GPIO_O_SCR_00_0
#define GPIO_O_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_00_0
#define GPIO_O_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10210)
#define GPIO_O_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_00_0_SCR                    GPIO_O_SCR_00_0
#define GPIO_O_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_CLEAR_00_0
#define GPIO_O_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10214)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_00_0_SCR                         GPIO_O_SCR_00_0
#define GPIO_O_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66072 [0x10218]

// Reserved address 66076 [0x1021c]

// Register GPIO_O_ENABLE_CONFIG_01_0
#define GPIO_O_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10220)
#define GPIO_O_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_01_0_SCR                   GPIO_O_SCR_01_0
#define GPIO_O_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_01_0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10224)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_O_SCR_01_0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_INPUT_01_0
#define GPIO_O_INPUT_01_0                       _MK_ADDR_CONST(0x10228)
#define GPIO_O_INPUT_01_0_SECURE                        0x0
#define GPIO_O_INPUT_01_0_SCR                   GPIO_O_SCR_01_0
#define GPIO_O_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_OUTPUT_CONTROL_01_0
#define GPIO_O_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1022c)
#define GPIO_O_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_01_0_SCR                  GPIO_O_SCR_01_0
#define GPIO_O_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_01_0
#define GPIO_O_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10230)
#define GPIO_O_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_01_0_SCR                    GPIO_O_SCR_01_0
#define GPIO_O_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_CLEAR_01_0
#define GPIO_O_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10234)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_01_0_SCR                         GPIO_O_SCR_01_0
#define GPIO_O_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66104 [0x10238]

// Reserved address 66108 [0x1023c]

// Register GPIO_O_ENABLE_CONFIG_02_0
#define GPIO_O_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10240)
#define GPIO_O_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_02_0_SCR                   GPIO_O_SCR_02_0
#define GPIO_O_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_02_0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10244)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_O_SCR_02_0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_INPUT_02_0
#define GPIO_O_INPUT_02_0                       _MK_ADDR_CONST(0x10248)
#define GPIO_O_INPUT_02_0_SECURE                        0x0
#define GPIO_O_INPUT_02_0_SCR                   GPIO_O_SCR_02_0
#define GPIO_O_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_OUTPUT_CONTROL_02_0
#define GPIO_O_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1024c)
#define GPIO_O_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_02_0_SCR                  GPIO_O_SCR_02_0
#define GPIO_O_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_02_0
#define GPIO_O_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10250)
#define GPIO_O_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_02_0_SCR                    GPIO_O_SCR_02_0
#define GPIO_O_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_CLEAR_02_0
#define GPIO_O_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10254)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_02_0_SCR                         GPIO_O_SCR_02_0
#define GPIO_O_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66136 [0x10258]

// Reserved address 66140 [0x1025c]

// Register GPIO_O_ENABLE_CONFIG_03_0
#define GPIO_O_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10260)
#define GPIO_O_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_03_0_SCR                   GPIO_O_SCR_03_0
#define GPIO_O_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_03_0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10264)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_O_SCR_03_0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_INPUT_03_0
#define GPIO_O_INPUT_03_0                       _MK_ADDR_CONST(0x10268)
#define GPIO_O_INPUT_03_0_SECURE                        0x0
#define GPIO_O_INPUT_03_0_SCR                   GPIO_O_SCR_03_0
#define GPIO_O_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_O_OUTPUT_CONTROL_03_0
#define GPIO_O_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1026c)
#define GPIO_O_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_03_0_SCR                  GPIO_O_SCR_03_0
#define GPIO_O_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_03_0
#define GPIO_O_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10270)
#define GPIO_O_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_03_0_SCR                    GPIO_O_SCR_03_0
#define GPIO_O_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_CLEAR_03_0
#define GPIO_O_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10274)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_03_0_SCR                         GPIO_O_SCR_03_0
#define GPIO_O_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66168 [0x10278]

// Reserved address 66172 [0x1027c]

// Reserved address 66176 [0x10280]

// Reserved address 66180 [0x10284]

// Reserved address 66184 [0x10288]

// Reserved address 66188 [0x1028c]

// Reserved address 66192 [0x10290]

// Reserved address 66196 [0x10294]

// Reserved address 66200 [0x10298]

// Reserved address 66204 [0x1029c]

// Reserved address 66208 [0x102a0]

// Reserved address 66212 [0x102a4]

// Reserved address 66216 [0x102a8]

// Reserved address 66220 [0x102ac]

// Reserved address 66224 [0x102b0]

// Reserved address 66228 [0x102b4]

// Reserved address 66232 [0x102b8]

// Reserved address 66236 [0x102bc]

// Reserved address 66240 [0x102c0]

// Reserved address 66244 [0x102c4]

// Reserved address 66248 [0x102c8]

// Reserved address 66252 [0x102cc]

// Reserved address 66256 [0x102d0]

// Reserved address 66260 [0x102d4]

// Reserved address 66264 [0x102d8]

// Reserved address 66268 [0x102dc]

// Reserved address 66272 [0x102e0]

// Reserved address 66276 [0x102e4]

// Reserved address 66280 [0x102e8]

// Reserved address 66284 [0x102ec]

// Reserved address 66288 [0x102f0]

// Reserved address 66292 [0x102f4]

// Reserved address 66296 [0x102f8]

// Reserved address 66300 [0x102fc]

// Register GPIO_O_INTERRUPT_STATUS_G0_0
#define GPIO_O_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10300)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G1_0
#define GPIO_O_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10304)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G2_0
#define GPIO_O_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10308)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G3_0
#define GPIO_O_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1030c)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G4_0
#define GPIO_O_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10310)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G5_0
#define GPIO_O_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10314)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G6_0
#define GPIO_O_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10318)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_O_INTERRUPT_STATUS_G7_0
#define GPIO_O_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1031c)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 66336 [0x10320]

// Reserved address 66340 [0x10324]

// Reserved address 66344 [0x10328]

// Reserved address 66348 [0x1032c]

// Reserved address 66352 [0x10330]

// Reserved address 66356 [0x10334]

// Reserved address 66360 [0x10338]

// Reserved address 66364 [0x1033c]

// Reserved address 66368 [0x10340]

// Reserved address 66372 [0x10344]

// Reserved address 66376 [0x10348]

// Reserved address 66380 [0x1034c]

// Reserved address 66384 [0x10350]

// Reserved address 66388 [0x10354]

// Reserved address 66392 [0x10358]

// Reserved address 66396 [0x1035c]

// Reserved address 66400 [0x10360]

// Reserved address 66404 [0x10364]

// Reserved address 66408 [0x10368]

// Reserved address 66412 [0x1036c]

// Reserved address 66416 [0x10370]

// Reserved address 66420 [0x10374]

// Reserved address 66424 [0x10378]

// Reserved address 66428 [0x1037c]

// Reserved address 66432 [0x10380]

// Reserved address 66436 [0x10384]

// Reserved address 66440 [0x10388]

// Reserved address 66444 [0x1038c]

// Reserved address 66448 [0x10390]

// Reserved address 66452 [0x10394]

// Reserved address 66456 [0x10398]

// Reserved address 66460 [0x1039c]

// Reserved address 66464 [0x103a0]

// Reserved address 66468 [0x103a4]

// Reserved address 66472 [0x103a8]

// Reserved address 66476 [0x103ac]

// Reserved address 66480 [0x103b0]

// Reserved address 66484 [0x103b4]

// Reserved address 66488 [0x103b8]

// Reserved address 66492 [0x103bc]

// Reserved address 66496 [0x103c0]

// Reserved address 66500 [0x103c4]

// Reserved address 66504 [0x103c8]

// Reserved address 66508 [0x103cc]

// Reserved address 66512 [0x103d0]

// Reserved address 66516 [0x103d4]

// Reserved address 66520 [0x103d8]

// Reserved address 66524 [0x103dc]

// Reserved address 66528 [0x103e0]

// Reserved address 66532 [0x103e4]

// Reserved address 66536 [0x103e8]

// Reserved address 66540 [0x103ec]

// Reserved address 66544 [0x103f0]

// Reserved address 66548 [0x103f4]

// Reserved address 66552 [0x103f8]

// Reserved address 66556 [0x103fc]

// Register GPIO_Q_ENABLE_CONFIG_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10400)
#define GPIO_Q_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10404)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Q_SCR_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_00_0
#define GPIO_Q_INPUT_00_0                       _MK_ADDR_CONST(0x10408)
#define GPIO_Q_INPUT_00_0_SECURE                        0x0
#define GPIO_Q_INPUT_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1040c)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_SCR                  GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10410)
#define GPIO_Q_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_SCR                    GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10414)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Q_SCR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66584 [0x10418]

// Reserved address 66588 [0x1041c]

// Register GPIO_Q_ENABLE_CONFIG_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10420)
#define GPIO_Q_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10424)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Q_SCR_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_01_0
#define GPIO_Q_INPUT_01_0                       _MK_ADDR_CONST(0x10428)
#define GPIO_Q_INPUT_01_0_SECURE                        0x0
#define GPIO_Q_INPUT_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1042c)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_SCR                  GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10430)
#define GPIO_Q_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_SCR                    GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10434)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Q_SCR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66616 [0x10438]

// Reserved address 66620 [0x1043c]

// Register GPIO_Q_ENABLE_CONFIG_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10440)
#define GPIO_Q_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10444)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Q_SCR_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_02_0
#define GPIO_Q_INPUT_02_0                       _MK_ADDR_CONST(0x10448)
#define GPIO_Q_INPUT_02_0_SECURE                        0x0
#define GPIO_Q_INPUT_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1044c)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_SCR                  GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10450)
#define GPIO_Q_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_SCR                    GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10454)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Q_SCR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66648 [0x10458]

// Reserved address 66652 [0x1045c]

// Register GPIO_Q_ENABLE_CONFIG_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10460)
#define GPIO_Q_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10464)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Q_SCR_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_03_0
#define GPIO_Q_INPUT_03_0                       _MK_ADDR_CONST(0x10468)
#define GPIO_Q_INPUT_03_0_SECURE                        0x0
#define GPIO_Q_INPUT_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1046c)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_SCR                  GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10470)
#define GPIO_Q_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_SCR                    GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10474)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Q_SCR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66680 [0x10478]

// Reserved address 66684 [0x1047c]

// Register GPIO_Q_ENABLE_CONFIG_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x10480)
#define GPIO_Q_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x10484)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Q_SCR_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_04_0
#define GPIO_Q_INPUT_04_0                       _MK_ADDR_CONST(0x10488)
#define GPIO_Q_INPUT_04_0_SECURE                        0x0
#define GPIO_Q_INPUT_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1048c)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_SCR                  GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x10490)
#define GPIO_Q_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_SCR                    GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x10494)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Q_SCR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66712 [0x10498]

// Reserved address 66716 [0x1049c]

// Register GPIO_Q_ENABLE_CONFIG_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x104a0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x104a4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Q_SCR_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_INPUT_05_0
#define GPIO_Q_INPUT_05_0                       _MK_ADDR_CONST(0x104a8)
#define GPIO_Q_INPUT_05_0_SECURE                        0x0
#define GPIO_Q_INPUT_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Q_OUTPUT_CONTROL_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x104ac)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_SCR                  GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x104b0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_SCR                    GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_CLEAR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x104b4)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Q_SCR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 66744 [0x104b8]

// Reserved address 66748 [0x104bc]

// Reserved address 66752 [0x104c0]

// Reserved address 66756 [0x104c4]

// Reserved address 66760 [0x104c8]

// Reserved address 66764 [0x104cc]

// Reserved address 66768 [0x104d0]

// Reserved address 66772 [0x104d4]

// Reserved address 66776 [0x104d8]

// Reserved address 66780 [0x104dc]

// Reserved address 66784 [0x104e0]

// Reserved address 66788 [0x104e4]

// Reserved address 66792 [0x104e8]

// Reserved address 66796 [0x104ec]

// Reserved address 66800 [0x104f0]

// Reserved address 66804 [0x104f4]

// Reserved address 66808 [0x104f8]

// Reserved address 66812 [0x104fc]

// Register GPIO_Q_INTERRUPT_STATUS_G0_0
#define GPIO_Q_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10500)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G1_0
#define GPIO_Q_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10504)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G2_0
#define GPIO_Q_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10508)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G3_0
#define GPIO_Q_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1050c)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G4_0
#define GPIO_Q_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10510)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G5_0
#define GPIO_Q_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10514)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G6_0
#define GPIO_Q_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10518)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Q_INTERRUPT_STATUS_G7_0
#define GPIO_Q_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1051c)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 66848 [0x10520]

// Reserved address 66852 [0x10524]

// Reserved address 66856 [0x10528]

// Reserved address 66860 [0x1052c]

// Reserved address 66864 [0x10530]

// Reserved address 66868 [0x10534]

// Reserved address 66872 [0x10538]

// Reserved address 66876 [0x1053c]

// Reserved address 66880 [0x10540]

// Reserved address 66884 [0x10544]

// Reserved address 66888 [0x10548]

// Reserved address 66892 [0x1054c]

// Reserved address 66896 [0x10550]

// Reserved address 66900 [0x10554]

// Reserved address 66904 [0x10558]

// Reserved address 66908 [0x1055c]

// Reserved address 66912 [0x10560]

// Reserved address 66916 [0x10564]

// Reserved address 66920 [0x10568]

// Reserved address 66924 [0x1056c]

// Reserved address 66928 [0x10570]

// Reserved address 66932 [0x10574]

// Reserved address 66936 [0x10578]

// Reserved address 66940 [0x1057c]

// Reserved address 66944 [0x10580]

// Reserved address 66948 [0x10584]

// Reserved address 66952 [0x10588]

// Reserved address 66956 [0x1058c]

// Reserved address 66960 [0x10590]

// Reserved address 66964 [0x10594]

// Reserved address 66968 [0x10598]

// Reserved address 66972 [0x1059c]

// Reserved address 66976 [0x105a0]

// Reserved address 66980 [0x105a4]

// Reserved address 66984 [0x105a8]

// Reserved address 66988 [0x105ac]

// Reserved address 66992 [0x105b0]

// Reserved address 66996 [0x105b4]

// Reserved address 67000 [0x105b8]

// Reserved address 67004 [0x105bc]

// Reserved address 67008 [0x105c0]

// Reserved address 67012 [0x105c4]

// Reserved address 67016 [0x105c8]

// Reserved address 67020 [0x105cc]

// Reserved address 67024 [0x105d0]

// Reserved address 67028 [0x105d4]

// Reserved address 67032 [0x105d8]

// Reserved address 67036 [0x105dc]

// Reserved address 67040 [0x105e0]

// Reserved address 67044 [0x105e4]

// Reserved address 67048 [0x105e8]

// Reserved address 67052 [0x105ec]

// Reserved address 67056 [0x105f0]

// Reserved address 67060 [0x105f4]

// Reserved address 67064 [0x105f8]

// Reserved address 67068 [0x105fc]

// Register GPIO_T_ENABLE_CONFIG_00_0
#define GPIO_T_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10600)
#define GPIO_T_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_00_0_SCR                   GPIO_T_SCR_00_0
#define GPIO_T_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_00_0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10604)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_T_SCR_00_0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_INPUT_00_0
#define GPIO_T_INPUT_00_0                       _MK_ADDR_CONST(0x10608)
#define GPIO_T_INPUT_00_0_SECURE                        0x0
#define GPIO_T_INPUT_00_0_SCR                   GPIO_T_SCR_00_0
#define GPIO_T_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_OUTPUT_CONTROL_00_0
#define GPIO_T_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1060c)
#define GPIO_T_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_00_0_SCR                  GPIO_T_SCR_00_0
#define GPIO_T_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_00_0
#define GPIO_T_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10610)
#define GPIO_T_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_00_0_SCR                    GPIO_T_SCR_00_0
#define GPIO_T_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_CLEAR_00_0
#define GPIO_T_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10614)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_00_0_SCR                         GPIO_T_SCR_00_0
#define GPIO_T_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67096 [0x10618]

// Reserved address 67100 [0x1061c]

// Register GPIO_T_ENABLE_CONFIG_01_0
#define GPIO_T_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10620)
#define GPIO_T_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_01_0_SCR                   GPIO_T_SCR_01_0
#define GPIO_T_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_01_0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10624)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_T_SCR_01_0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_INPUT_01_0
#define GPIO_T_INPUT_01_0                       _MK_ADDR_CONST(0x10628)
#define GPIO_T_INPUT_01_0_SECURE                        0x0
#define GPIO_T_INPUT_01_0_SCR                   GPIO_T_SCR_01_0
#define GPIO_T_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_OUTPUT_CONTROL_01_0
#define GPIO_T_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1062c)
#define GPIO_T_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_01_0_SCR                  GPIO_T_SCR_01_0
#define GPIO_T_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_01_0
#define GPIO_T_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10630)
#define GPIO_T_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_01_0_SCR                    GPIO_T_SCR_01_0
#define GPIO_T_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_CLEAR_01_0
#define GPIO_T_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10634)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_01_0_SCR                         GPIO_T_SCR_01_0
#define GPIO_T_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67128 [0x10638]

// Reserved address 67132 [0x1063c]

// Register GPIO_T_ENABLE_CONFIG_02_0
#define GPIO_T_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10640)
#define GPIO_T_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_02_0_SCR                   GPIO_T_SCR_02_0
#define GPIO_T_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_02_0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10644)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_T_SCR_02_0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_INPUT_02_0
#define GPIO_T_INPUT_02_0                       _MK_ADDR_CONST(0x10648)
#define GPIO_T_INPUT_02_0_SECURE                        0x0
#define GPIO_T_INPUT_02_0_SCR                   GPIO_T_SCR_02_0
#define GPIO_T_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_OUTPUT_CONTROL_02_0
#define GPIO_T_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1064c)
#define GPIO_T_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_02_0_SCR                  GPIO_T_SCR_02_0
#define GPIO_T_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_02_0
#define GPIO_T_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10650)
#define GPIO_T_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_02_0_SCR                    GPIO_T_SCR_02_0
#define GPIO_T_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_CLEAR_02_0
#define GPIO_T_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10654)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_02_0_SCR                         GPIO_T_SCR_02_0
#define GPIO_T_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67160 [0x10658]

// Reserved address 67164 [0x1065c]

// Register GPIO_T_ENABLE_CONFIG_03_0
#define GPIO_T_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10660)
#define GPIO_T_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_03_0_SCR                   GPIO_T_SCR_03_0
#define GPIO_T_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_03_0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10664)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_T_SCR_03_0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_INPUT_03_0
#define GPIO_T_INPUT_03_0                       _MK_ADDR_CONST(0x10668)
#define GPIO_T_INPUT_03_0_SECURE                        0x0
#define GPIO_T_INPUT_03_0_SCR                   GPIO_T_SCR_03_0
#define GPIO_T_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_T_OUTPUT_CONTROL_03_0
#define GPIO_T_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1066c)
#define GPIO_T_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_03_0_SCR                  GPIO_T_SCR_03_0
#define GPIO_T_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_03_0
#define GPIO_T_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10670)
#define GPIO_T_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_03_0_SCR                    GPIO_T_SCR_03_0
#define GPIO_T_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_CLEAR_03_0
#define GPIO_T_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10674)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_03_0_SCR                         GPIO_T_SCR_03_0
#define GPIO_T_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67192 [0x10678]

// Reserved address 67196 [0x1067c]

// Reserved address 67200 [0x10680]

// Reserved address 67204 [0x10684]

// Reserved address 67208 [0x10688]

// Reserved address 67212 [0x1068c]

// Reserved address 67216 [0x10690]

// Reserved address 67220 [0x10694]

// Reserved address 67224 [0x10698]

// Reserved address 67228 [0x1069c]

// Reserved address 67232 [0x106a0]

// Reserved address 67236 [0x106a4]

// Reserved address 67240 [0x106a8]

// Reserved address 67244 [0x106ac]

// Reserved address 67248 [0x106b0]

// Reserved address 67252 [0x106b4]

// Reserved address 67256 [0x106b8]

// Reserved address 67260 [0x106bc]

// Reserved address 67264 [0x106c0]

// Reserved address 67268 [0x106c4]

// Reserved address 67272 [0x106c8]

// Reserved address 67276 [0x106cc]

// Reserved address 67280 [0x106d0]

// Reserved address 67284 [0x106d4]

// Reserved address 67288 [0x106d8]

// Reserved address 67292 [0x106dc]

// Reserved address 67296 [0x106e0]

// Reserved address 67300 [0x106e4]

// Reserved address 67304 [0x106e8]

// Reserved address 67308 [0x106ec]

// Reserved address 67312 [0x106f0]

// Reserved address 67316 [0x106f4]

// Reserved address 67320 [0x106f8]

// Reserved address 67324 [0x106fc]

// Register GPIO_T_INTERRUPT_STATUS_G0_0
#define GPIO_T_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10700)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G1_0
#define GPIO_T_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10704)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G2_0
#define GPIO_T_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10708)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G3_0
#define GPIO_T_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1070c)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G4_0
#define GPIO_T_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10710)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G5_0
#define GPIO_T_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10714)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G6_0
#define GPIO_T_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10718)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_T_INTERRUPT_STATUS_G7_0
#define GPIO_T_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1071c)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 67360 [0x10720]

// Reserved address 67364 [0x10724]

// Reserved address 67368 [0x10728]

// Reserved address 67372 [0x1072c]

// Reserved address 67376 [0x10730]

// Reserved address 67380 [0x10734]

// Reserved address 67384 [0x10738]

// Reserved address 67388 [0x1073c]

// Reserved address 67392 [0x10740]

// Reserved address 67396 [0x10744]

// Reserved address 67400 [0x10748]

// Reserved address 67404 [0x1074c]

// Reserved address 67408 [0x10750]

// Reserved address 67412 [0x10754]

// Reserved address 67416 [0x10758]

// Reserved address 67420 [0x1075c]

// Reserved address 67424 [0x10760]

// Reserved address 67428 [0x10764]

// Reserved address 67432 [0x10768]

// Reserved address 67436 [0x1076c]

// Reserved address 67440 [0x10770]

// Reserved address 67444 [0x10774]

// Reserved address 67448 [0x10778]

// Reserved address 67452 [0x1077c]

// Reserved address 67456 [0x10780]

// Reserved address 67460 [0x10784]

// Reserved address 67464 [0x10788]

// Reserved address 67468 [0x1078c]

// Reserved address 67472 [0x10790]

// Reserved address 67476 [0x10794]

// Reserved address 67480 [0x10798]

// Reserved address 67484 [0x1079c]

// Reserved address 67488 [0x107a0]

// Reserved address 67492 [0x107a4]

// Reserved address 67496 [0x107a8]

// Reserved address 67500 [0x107ac]

// Reserved address 67504 [0x107b0]

// Reserved address 67508 [0x107b4]

// Reserved address 67512 [0x107b8]

// Reserved address 67516 [0x107bc]

// Reserved address 67520 [0x107c0]

// Reserved address 67524 [0x107c4]

// Reserved address 67528 [0x107c8]

// Reserved address 67532 [0x107cc]

// Reserved address 67536 [0x107d0]

// Reserved address 67540 [0x107d4]

// Reserved address 67544 [0x107d8]

// Reserved address 67548 [0x107dc]

// Reserved address 67552 [0x107e0]

// Reserved address 67556 [0x107e4]

// Reserved address 67560 [0x107e8]

// Reserved address 67564 [0x107ec]

// Reserved address 67568 [0x107f0]

// Reserved address 67572 [0x107f4]

// Reserved address 67576 [0x107f8]

// Reserved address 67580 [0x107fc]

// Register GPIO_I_ENABLE_CONFIG_00_0
#define GPIO_I_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10800)
#define GPIO_I_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10804)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_I_SCR_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_00_0
#define GPIO_I_INPUT_00_0                       _MK_ADDR_CONST(0x10808)
#define GPIO_I_INPUT_00_0_SECURE                        0x0
#define GPIO_I_INPUT_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1080c)
#define GPIO_I_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_SCR                  GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_00_0
#define GPIO_I_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10810)
#define GPIO_I_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_00_0_SCR                    GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10814)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_SCR                         GPIO_I_SCR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67608 [0x10818]

// Reserved address 67612 [0x1081c]

// Register GPIO_I_ENABLE_CONFIG_01_0
#define GPIO_I_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10820)
#define GPIO_I_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10824)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_I_SCR_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_01_0
#define GPIO_I_INPUT_01_0                       _MK_ADDR_CONST(0x10828)
#define GPIO_I_INPUT_01_0_SECURE                        0x0
#define GPIO_I_INPUT_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1082c)
#define GPIO_I_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_SCR                  GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_01_0
#define GPIO_I_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10830)
#define GPIO_I_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_01_0_SCR                    GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10834)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_SCR                         GPIO_I_SCR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67640 [0x10838]

// Reserved address 67644 [0x1083c]

// Register GPIO_I_ENABLE_CONFIG_02_0
#define GPIO_I_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10840)
#define GPIO_I_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10844)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_I_SCR_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_02_0
#define GPIO_I_INPUT_02_0                       _MK_ADDR_CONST(0x10848)
#define GPIO_I_INPUT_02_0_SECURE                        0x0
#define GPIO_I_INPUT_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1084c)
#define GPIO_I_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_SCR                  GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_02_0
#define GPIO_I_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10850)
#define GPIO_I_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_02_0_SCR                    GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10854)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_SCR                         GPIO_I_SCR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67672 [0x10858]

// Reserved address 67676 [0x1085c]

// Register GPIO_I_ENABLE_CONFIG_03_0
#define GPIO_I_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10860)
#define GPIO_I_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10864)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_I_SCR_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_03_0
#define GPIO_I_INPUT_03_0                       _MK_ADDR_CONST(0x10868)
#define GPIO_I_INPUT_03_0_SECURE                        0x0
#define GPIO_I_INPUT_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1086c)
#define GPIO_I_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_SCR                  GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_03_0
#define GPIO_I_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10870)
#define GPIO_I_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_03_0_SCR                    GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10874)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_SCR                         GPIO_I_SCR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67704 [0x10878]

// Reserved address 67708 [0x1087c]

// Register GPIO_I_ENABLE_CONFIG_04_0
#define GPIO_I_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x10880)
#define GPIO_I_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x10884)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_I_SCR_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_04_0
#define GPIO_I_INPUT_04_0                       _MK_ADDR_CONST(0x10888)
#define GPIO_I_INPUT_04_0_SECURE                        0x0
#define GPIO_I_INPUT_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1088c)
#define GPIO_I_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_SCR                  GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_04_0
#define GPIO_I_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x10890)
#define GPIO_I_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_04_0_SCR                    GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x10894)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_SCR                         GPIO_I_SCR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67736 [0x10898]

// Reserved address 67740 [0x1089c]

// Register GPIO_I_ENABLE_CONFIG_05_0
#define GPIO_I_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x108a0)
#define GPIO_I_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_05_0_SCR                   GPIO_I_SCR_05_0
#define GPIO_I_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_05_0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x108a4)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_I_SCR_05_0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_05_0
#define GPIO_I_INPUT_05_0                       _MK_ADDR_CONST(0x108a8)
#define GPIO_I_INPUT_05_0_SECURE                        0x0
#define GPIO_I_INPUT_05_0_SCR                   GPIO_I_SCR_05_0
#define GPIO_I_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_05_0
#define GPIO_I_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x108ac)
#define GPIO_I_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_05_0_SCR                  GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_05_0
#define GPIO_I_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x108b0)
#define GPIO_I_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_05_0_SCR                    GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_05_0
#define GPIO_I_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x108b4)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_05_0_SCR                         GPIO_I_SCR_05_0
#define GPIO_I_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67768 [0x108b8]

// Reserved address 67772 [0x108bc]

// Register GPIO_I_ENABLE_CONFIG_06_0
#define GPIO_I_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x108c0)
#define GPIO_I_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_06_0_SCR                   GPIO_I_SCR_06_0
#define GPIO_I_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_06_0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x108c4)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_I_SCR_06_0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_06_0
#define GPIO_I_INPUT_06_0                       _MK_ADDR_CONST(0x108c8)
#define GPIO_I_INPUT_06_0_SECURE                        0x0
#define GPIO_I_INPUT_06_0_SCR                   GPIO_I_SCR_06_0
#define GPIO_I_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_06_0
#define GPIO_I_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x108cc)
#define GPIO_I_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_06_0_SCR                  GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_06_0
#define GPIO_I_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x108d0)
#define GPIO_I_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_06_0_SCR                    GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_06_0
#define GPIO_I_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x108d4)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_06_0_SCR                         GPIO_I_SCR_06_0
#define GPIO_I_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67800 [0x108d8]

// Reserved address 67804 [0x108dc]

// Register GPIO_I_ENABLE_CONFIG_07_0
#define GPIO_I_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x108e0)
#define GPIO_I_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_07_0_SCR                   GPIO_I_SCR_07_0
#define GPIO_I_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_07_0
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x108e4)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_I_SCR_07_0
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_INPUT_07_0
#define GPIO_I_INPUT_07_0                       _MK_ADDR_CONST(0x108e8)
#define GPIO_I_INPUT_07_0_SECURE                        0x0
#define GPIO_I_INPUT_07_0_SCR                   GPIO_I_SCR_07_0
#define GPIO_I_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_I_OUTPUT_CONTROL_07_0
#define GPIO_I_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x108ec)
#define GPIO_I_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_07_0_SCR                  GPIO_I_SCR_07_0
#define GPIO_I_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_07_0
#define GPIO_I_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x108f0)
#define GPIO_I_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_07_0_SCR                    GPIO_I_SCR_07_0
#define GPIO_I_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_CLEAR_07_0
#define GPIO_I_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x108f4)
#define GPIO_I_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_07_0_SCR                         GPIO_I_SCR_07_0
#define GPIO_I_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 67832 [0x108f8]

// Reserved address 67836 [0x108fc]

// Register GPIO_I_INTERRUPT_STATUS_G0_0
#define GPIO_I_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10900)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G1_0
#define GPIO_I_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10904)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G2_0
#define GPIO_I_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10908)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G3_0
#define GPIO_I_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1090c)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G4_0
#define GPIO_I_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10910)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G5_0
#define GPIO_I_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10914)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G6_0
#define GPIO_I_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10918)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_I_INTERRUPT_STATUS_G7_0
#define GPIO_I_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1091c)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 67872 [0x10920]

// Reserved address 67876 [0x10924]

// Reserved address 67880 [0x10928]

// Reserved address 67884 [0x1092c]

// Reserved address 67888 [0x10930]

// Reserved address 67892 [0x10934]

// Reserved address 67896 [0x10938]

// Reserved address 67900 [0x1093c]

// Reserved address 67904 [0x10940]

// Reserved address 67908 [0x10944]

// Reserved address 67912 [0x10948]

// Reserved address 67916 [0x1094c]

// Reserved address 67920 [0x10950]

// Reserved address 67924 [0x10954]

// Reserved address 67928 [0x10958]

// Reserved address 67932 [0x1095c]

// Reserved address 67936 [0x10960]

// Reserved address 67940 [0x10964]

// Reserved address 67944 [0x10968]

// Reserved address 67948 [0x1096c]

// Reserved address 67952 [0x10970]

// Reserved address 67956 [0x10974]

// Reserved address 67960 [0x10978]

// Reserved address 67964 [0x1097c]

// Reserved address 67968 [0x10980]

// Reserved address 67972 [0x10984]

// Reserved address 67976 [0x10988]

// Reserved address 67980 [0x1098c]

// Reserved address 67984 [0x10990]

// Reserved address 67988 [0x10994]

// Reserved address 67992 [0x10998]

// Reserved address 67996 [0x1099c]

// Reserved address 68000 [0x109a0]

// Reserved address 68004 [0x109a4]

// Reserved address 68008 [0x109a8]

// Reserved address 68012 [0x109ac]

// Reserved address 68016 [0x109b0]

// Reserved address 68020 [0x109b4]

// Reserved address 68024 [0x109b8]

// Reserved address 68028 [0x109bc]

// Reserved address 68032 [0x109c0]

// Reserved address 68036 [0x109c4]

// Reserved address 68040 [0x109c8]

// Reserved address 68044 [0x109cc]

// Reserved address 68048 [0x109d0]

// Reserved address 68052 [0x109d4]

// Reserved address 68056 [0x109d8]

// Reserved address 68060 [0x109dc]

// Reserved address 68064 [0x109e0]

// Reserved address 68068 [0x109e4]

// Reserved address 68072 [0x109e8]

// Reserved address 68076 [0x109ec]

// Reserved address 68080 [0x109f0]

// Reserved address 68084 [0x109f4]

// Reserved address 68088 [0x109f8]

// Reserved address 68092 [0x109fc]

// Register GPIO_R_ENABLE_CONFIG_00_0
#define GPIO_R_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x10a00)
#define GPIO_R_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x10a04)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_R_SCR_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_00_0
#define GPIO_R_INPUT_00_0                       _MK_ADDR_CONST(0x10a08)
#define GPIO_R_INPUT_00_0_SECURE                        0x0
#define GPIO_R_INPUT_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x10a0c)
#define GPIO_R_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_SCR                  GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_00_0
#define GPIO_R_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x10a10)
#define GPIO_R_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_00_0_SCR                    GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x10a14)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_SCR                         GPIO_R_SCR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68120 [0x10a18]

// Reserved address 68124 [0x10a1c]

// Register GPIO_R_ENABLE_CONFIG_01_0
#define GPIO_R_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x10a20)
#define GPIO_R_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x10a24)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_R_SCR_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_01_0
#define GPIO_R_INPUT_01_0                       _MK_ADDR_CONST(0x10a28)
#define GPIO_R_INPUT_01_0_SECURE                        0x0
#define GPIO_R_INPUT_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x10a2c)
#define GPIO_R_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_SCR                  GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_01_0
#define GPIO_R_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x10a30)
#define GPIO_R_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_01_0_SCR                    GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x10a34)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_SCR                         GPIO_R_SCR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68152 [0x10a38]

// Reserved address 68156 [0x10a3c]

// Register GPIO_R_ENABLE_CONFIG_02_0
#define GPIO_R_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x10a40)
#define GPIO_R_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x10a44)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_R_SCR_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_02_0
#define GPIO_R_INPUT_02_0                       _MK_ADDR_CONST(0x10a48)
#define GPIO_R_INPUT_02_0_SECURE                        0x0
#define GPIO_R_INPUT_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x10a4c)
#define GPIO_R_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_SCR                  GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_02_0
#define GPIO_R_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x10a50)
#define GPIO_R_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_02_0_SCR                    GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x10a54)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_SCR                         GPIO_R_SCR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68184 [0x10a58]

// Reserved address 68188 [0x10a5c]

// Register GPIO_R_ENABLE_CONFIG_03_0
#define GPIO_R_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x10a60)
#define GPIO_R_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x10a64)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_R_SCR_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_03_0
#define GPIO_R_INPUT_03_0                       _MK_ADDR_CONST(0x10a68)
#define GPIO_R_INPUT_03_0_SECURE                        0x0
#define GPIO_R_INPUT_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x10a6c)
#define GPIO_R_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_SCR                  GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_03_0
#define GPIO_R_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x10a70)
#define GPIO_R_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_03_0_SCR                    GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x10a74)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_SCR                         GPIO_R_SCR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68216 [0x10a78]

// Reserved address 68220 [0x10a7c]

// Register GPIO_R_ENABLE_CONFIG_04_0
#define GPIO_R_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x10a80)
#define GPIO_R_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x10a84)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_R_SCR_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_04_0
#define GPIO_R_INPUT_04_0                       _MK_ADDR_CONST(0x10a88)
#define GPIO_R_INPUT_04_0_SECURE                        0x0
#define GPIO_R_INPUT_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x10a8c)
#define GPIO_R_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_SCR                  GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_04_0
#define GPIO_R_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x10a90)
#define GPIO_R_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_04_0_SCR                    GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x10a94)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_SCR                         GPIO_R_SCR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68248 [0x10a98]

// Reserved address 68252 [0x10a9c]

// Register GPIO_R_ENABLE_CONFIG_05_0
#define GPIO_R_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x10aa0)
#define GPIO_R_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x10aa4)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_R_SCR_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_INPUT_05_0
#define GPIO_R_INPUT_05_0                       _MK_ADDR_CONST(0x10aa8)
#define GPIO_R_INPUT_05_0_SECURE                        0x0
#define GPIO_R_INPUT_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_R_OUTPUT_CONTROL_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x10aac)
#define GPIO_R_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_SCR                  GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_05_0
#define GPIO_R_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x10ab0)
#define GPIO_R_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_05_0_SCR                    GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_CLEAR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x10ab4)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_SCR                         GPIO_R_SCR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 68280 [0x10ab8]

// Reserved address 68284 [0x10abc]

// Reserved address 68288 [0x10ac0]

// Reserved address 68292 [0x10ac4]

// Reserved address 68296 [0x10ac8]

// Reserved address 68300 [0x10acc]

// Reserved address 68304 [0x10ad0]

// Reserved address 68308 [0x10ad4]

// Reserved address 68312 [0x10ad8]

// Reserved address 68316 [0x10adc]

// Reserved address 68320 [0x10ae0]

// Reserved address 68324 [0x10ae4]

// Reserved address 68328 [0x10ae8]

// Reserved address 68332 [0x10aec]

// Reserved address 68336 [0x10af0]

// Reserved address 68340 [0x10af4]

// Reserved address 68344 [0x10af8]

// Reserved address 68348 [0x10afc]

// Register GPIO_R_INTERRUPT_STATUS_G0_0
#define GPIO_R_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x10b00)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G1_0
#define GPIO_R_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x10b04)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G2_0
#define GPIO_R_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x10b08)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G3_0
#define GPIO_R_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x10b0c)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G4_0
#define GPIO_R_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x10b10)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G5_0
#define GPIO_R_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x10b14)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G6_0
#define GPIO_R_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x10b18)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_R_INTERRUPT_STATUS_G7_0
#define GPIO_R_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x10b1c)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 68384 [0x10b20]

// Reserved address 68388 [0x10b24]

// Reserved address 68392 [0x10b28]

// Reserved address 68396 [0x10b2c]

// Reserved address 68400 [0x10b30]

// Reserved address 68404 [0x10b34]

// Reserved address 68408 [0x10b38]

// Reserved address 68412 [0x10b3c]

// Reserved address 68416 [0x10b40]

// Reserved address 68420 [0x10b44]

// Reserved address 68424 [0x10b48]

// Reserved address 68428 [0x10b4c]

// Reserved address 68432 [0x10b50]

// Reserved address 68436 [0x10b54]

// Reserved address 68440 [0x10b58]

// Reserved address 68444 [0x10b5c]

// Reserved address 68448 [0x10b60]

// Reserved address 68452 [0x10b64]

// Reserved address 68456 [0x10b68]

// Reserved address 68460 [0x10b6c]

// Reserved address 68464 [0x10b70]

// Reserved address 68468 [0x10b74]

// Reserved address 68472 [0x10b78]

// Reserved address 68476 [0x10b7c]

// Reserved address 68480 [0x10b80]

// Reserved address 68484 [0x10b84]

// Reserved address 68488 [0x10b88]

// Reserved address 68492 [0x10b8c]

// Reserved address 68496 [0x10b90]

// Reserved address 68500 [0x10b94]

// Reserved address 68504 [0x10b98]

// Reserved address 68508 [0x10b9c]

// Reserved address 68512 [0x10ba0]

// Reserved address 68516 [0x10ba4]

// Reserved address 68520 [0x10ba8]

// Reserved address 68524 [0x10bac]

// Reserved address 68528 [0x10bb0]

// Reserved address 68532 [0x10bb4]

// Reserved address 68536 [0x10bb8]

// Reserved address 68540 [0x10bbc]

// Reserved address 68544 [0x10bc0]

// Reserved address 68548 [0x10bc4]

// Reserved address 68552 [0x10bc8]

// Reserved address 68556 [0x10bcc]

// Reserved address 68560 [0x10bd0]

// Reserved address 68564 [0x10bd4]

// Reserved address 68568 [0x10bd8]

// Reserved address 68572 [0x10bdc]

// Reserved address 68576 [0x10be0]

// Reserved address 68580 [0x10be4]

// Reserved address 68584 [0x10be8]

// Reserved address 68588 [0x10bec]

// Reserved address 68592 [0x10bf0]

// Reserved address 68596 [0x10bf4]

// Reserved address 68600 [0x10bf8]

// Reserved address 68604 [0x10bfc]

// Register GPIO_H_ENABLE_CONFIG_00_0
#define GPIO_H_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11000)
#define GPIO_H_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11004)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_H_SCR_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_00_0
#define GPIO_H_INPUT_00_0                       _MK_ADDR_CONST(0x11008)
#define GPIO_H_INPUT_00_0_SECURE                        0x0
#define GPIO_H_INPUT_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1100c)
#define GPIO_H_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_SCR                  GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_00_0
#define GPIO_H_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11010)
#define GPIO_H_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_00_0_SCR                    GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11014)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_SCR                         GPIO_H_SCR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69656 [0x11018]

// Reserved address 69660 [0x1101c]

// Register GPIO_H_ENABLE_CONFIG_01_0
#define GPIO_H_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11020)
#define GPIO_H_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11024)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_H_SCR_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_01_0
#define GPIO_H_INPUT_01_0                       _MK_ADDR_CONST(0x11028)
#define GPIO_H_INPUT_01_0_SECURE                        0x0
#define GPIO_H_INPUT_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1102c)
#define GPIO_H_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_SCR                  GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_01_0
#define GPIO_H_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11030)
#define GPIO_H_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_01_0_SCR                    GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11034)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_SCR                         GPIO_H_SCR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69688 [0x11038]

// Reserved address 69692 [0x1103c]

// Register GPIO_H_ENABLE_CONFIG_02_0
#define GPIO_H_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11040)
#define GPIO_H_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11044)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_H_SCR_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_02_0
#define GPIO_H_INPUT_02_0                       _MK_ADDR_CONST(0x11048)
#define GPIO_H_INPUT_02_0_SECURE                        0x0
#define GPIO_H_INPUT_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1104c)
#define GPIO_H_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_SCR                  GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_02_0
#define GPIO_H_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11050)
#define GPIO_H_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_02_0_SCR                    GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11054)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_SCR                         GPIO_H_SCR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69720 [0x11058]

// Reserved address 69724 [0x1105c]

// Register GPIO_H_ENABLE_CONFIG_03_0
#define GPIO_H_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11060)
#define GPIO_H_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11064)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_H_SCR_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_03_0
#define GPIO_H_INPUT_03_0                       _MK_ADDR_CONST(0x11068)
#define GPIO_H_INPUT_03_0_SECURE                        0x0
#define GPIO_H_INPUT_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1106c)
#define GPIO_H_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_SCR                  GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_03_0
#define GPIO_H_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11070)
#define GPIO_H_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_03_0_SCR                    GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11074)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_SCR                         GPIO_H_SCR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69752 [0x11078]

// Reserved address 69756 [0x1107c]

// Register GPIO_H_ENABLE_CONFIG_04_0
#define GPIO_H_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11080)
#define GPIO_H_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11084)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_H_SCR_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_04_0
#define GPIO_H_INPUT_04_0                       _MK_ADDR_CONST(0x11088)
#define GPIO_H_INPUT_04_0_SECURE                        0x0
#define GPIO_H_INPUT_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1108c)
#define GPIO_H_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_SCR                  GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_04_0
#define GPIO_H_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11090)
#define GPIO_H_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_04_0_SCR                    GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11094)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_SCR                         GPIO_H_SCR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69784 [0x11098]

// Reserved address 69788 [0x1109c]

// Register GPIO_H_ENABLE_CONFIG_05_0
#define GPIO_H_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x110a0)
#define GPIO_H_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x110a4)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_H_SCR_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_05_0
#define GPIO_H_INPUT_05_0                       _MK_ADDR_CONST(0x110a8)
#define GPIO_H_INPUT_05_0_SECURE                        0x0
#define GPIO_H_INPUT_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x110ac)
#define GPIO_H_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_SCR                  GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_05_0
#define GPIO_H_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x110b0)
#define GPIO_H_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_05_0_SCR                    GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x110b4)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_SCR                         GPIO_H_SCR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69816 [0x110b8]

// Reserved address 69820 [0x110bc]

// Register GPIO_H_ENABLE_CONFIG_06_0
#define GPIO_H_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x110c0)
#define GPIO_H_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x110c4)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_H_SCR_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_INPUT_06_0
#define GPIO_H_INPUT_06_0                       _MK_ADDR_CONST(0x110c8)
#define GPIO_H_INPUT_06_0_SECURE                        0x0
#define GPIO_H_INPUT_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_H_OUTPUT_CONTROL_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x110cc)
#define GPIO_H_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_SCR                  GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_06_0
#define GPIO_H_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x110d0)
#define GPIO_H_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_06_0_SCR                    GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_CLEAR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x110d4)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_SCR                         GPIO_H_SCR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 69848 [0x110d8]

// Reserved address 69852 [0x110dc]

// Reserved address 69856 [0x110e0]

// Reserved address 69860 [0x110e4]

// Reserved address 69864 [0x110e8]

// Reserved address 69868 [0x110ec]

// Reserved address 69872 [0x110f0]

// Reserved address 69876 [0x110f4]

// Reserved address 69880 [0x110f8]

// Reserved address 69884 [0x110fc]

// Register GPIO_H_INTERRUPT_STATUS_G0_0
#define GPIO_H_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11100)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G1_0
#define GPIO_H_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11104)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G2_0
#define GPIO_H_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11108)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G3_0
#define GPIO_H_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1110c)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G4_0
#define GPIO_H_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11110)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G5_0
#define GPIO_H_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11114)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G6_0
#define GPIO_H_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11118)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_H_INTERRUPT_STATUS_G7_0
#define GPIO_H_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1111c)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 69920 [0x11120]

// Reserved address 69924 [0x11124]

// Reserved address 69928 [0x11128]

// Reserved address 69932 [0x1112c]

// Reserved address 69936 [0x11130]

// Reserved address 69940 [0x11134]

// Reserved address 69944 [0x11138]

// Reserved address 69948 [0x1113c]

// Reserved address 69952 [0x11140]

// Reserved address 69956 [0x11144]

// Reserved address 69960 [0x11148]

// Reserved address 69964 [0x1114c]

// Reserved address 69968 [0x11150]

// Reserved address 69972 [0x11154]

// Reserved address 69976 [0x11158]

// Reserved address 69980 [0x1115c]

// Reserved address 69984 [0x11160]

// Reserved address 69988 [0x11164]

// Reserved address 69992 [0x11168]

// Reserved address 69996 [0x1116c]

// Reserved address 70000 [0x11170]

// Reserved address 70004 [0x11174]

// Reserved address 70008 [0x11178]

// Reserved address 70012 [0x1117c]

// Reserved address 70016 [0x11180]

// Reserved address 70020 [0x11184]

// Reserved address 70024 [0x11188]

// Reserved address 70028 [0x1118c]

// Reserved address 70032 [0x11190]

// Reserved address 70036 [0x11194]

// Reserved address 70040 [0x11198]

// Reserved address 70044 [0x1119c]

// Reserved address 70048 [0x111a0]

// Reserved address 70052 [0x111a4]

// Reserved address 70056 [0x111a8]

// Reserved address 70060 [0x111ac]

// Reserved address 70064 [0x111b0]

// Reserved address 70068 [0x111b4]

// Reserved address 70072 [0x111b8]

// Reserved address 70076 [0x111bc]

// Reserved address 70080 [0x111c0]

// Reserved address 70084 [0x111c4]

// Reserved address 70088 [0x111c8]

// Reserved address 70092 [0x111cc]

// Reserved address 70096 [0x111d0]

// Reserved address 70100 [0x111d4]

// Reserved address 70104 [0x111d8]

// Reserved address 70108 [0x111dc]

// Reserved address 70112 [0x111e0]

// Reserved address 70116 [0x111e4]

// Reserved address 70120 [0x111e8]

// Reserved address 70124 [0x111ec]

// Reserved address 70128 [0x111f0]

// Reserved address 70132 [0x111f4]

// Reserved address 70136 [0x111f8]

// Reserved address 70140 [0x111fc]

// Register GPIO_L_ENABLE_CONFIG_00_0
#define GPIO_L_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11200)
#define GPIO_L_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11204)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_L_SCR_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_00_0
#define GPIO_L_INPUT_00_0                       _MK_ADDR_CONST(0x11208)
#define GPIO_L_INPUT_00_0_SECURE                        0x0
#define GPIO_L_INPUT_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1120c)
#define GPIO_L_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_SCR                  GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_00_0
#define GPIO_L_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11210)
#define GPIO_L_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_00_0_SCR                    GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11214)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_SCR                         GPIO_L_SCR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70168 [0x11218]

// Reserved address 70172 [0x1121c]

// Register GPIO_L_ENABLE_CONFIG_01_0
#define GPIO_L_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11220)
#define GPIO_L_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11224)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_L_SCR_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_01_0
#define GPIO_L_INPUT_01_0                       _MK_ADDR_CONST(0x11228)
#define GPIO_L_INPUT_01_0_SECURE                        0x0
#define GPIO_L_INPUT_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1122c)
#define GPIO_L_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_SCR                  GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_01_0
#define GPIO_L_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11230)
#define GPIO_L_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_01_0_SCR                    GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11234)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_SCR                         GPIO_L_SCR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70200 [0x11238]

// Reserved address 70204 [0x1123c]

// Register GPIO_L_ENABLE_CONFIG_02_0
#define GPIO_L_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11240)
#define GPIO_L_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11244)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_L_SCR_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_02_0
#define GPIO_L_INPUT_02_0                       _MK_ADDR_CONST(0x11248)
#define GPIO_L_INPUT_02_0_SECURE                        0x0
#define GPIO_L_INPUT_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1124c)
#define GPIO_L_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_SCR                  GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_02_0
#define GPIO_L_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11250)
#define GPIO_L_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_02_0_SCR                    GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11254)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_SCR                         GPIO_L_SCR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70232 [0x11258]

// Reserved address 70236 [0x1125c]

// Register GPIO_L_ENABLE_CONFIG_03_0
#define GPIO_L_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11260)
#define GPIO_L_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11264)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_L_SCR_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_03_0
#define GPIO_L_INPUT_03_0                       _MK_ADDR_CONST(0x11268)
#define GPIO_L_INPUT_03_0_SECURE                        0x0
#define GPIO_L_INPUT_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1126c)
#define GPIO_L_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_SCR                  GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_03_0
#define GPIO_L_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11270)
#define GPIO_L_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_03_0_SCR                    GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11274)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_SCR                         GPIO_L_SCR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70264 [0x11278]

// Reserved address 70268 [0x1127c]

// Register GPIO_L_ENABLE_CONFIG_04_0
#define GPIO_L_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11280)
#define GPIO_L_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_04_0_SCR                   GPIO_L_SCR_04_0
#define GPIO_L_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_04_0
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11284)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_L_SCR_04_0
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_04_0
#define GPIO_L_INPUT_04_0                       _MK_ADDR_CONST(0x11288)
#define GPIO_L_INPUT_04_0_SECURE                        0x0
#define GPIO_L_INPUT_04_0_SCR                   GPIO_L_SCR_04_0
#define GPIO_L_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_04_0
#define GPIO_L_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1128c)
#define GPIO_L_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_04_0_SCR                  GPIO_L_SCR_04_0
#define GPIO_L_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_04_0
#define GPIO_L_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11290)
#define GPIO_L_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_04_0_SCR                    GPIO_L_SCR_04_0
#define GPIO_L_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_04_0
#define GPIO_L_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11294)
#define GPIO_L_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_04_0_SCR                         GPIO_L_SCR_04_0
#define GPIO_L_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70296 [0x11298]

// Reserved address 70300 [0x1129c]

// Register GPIO_L_ENABLE_CONFIG_05_0
#define GPIO_L_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x112a0)
#define GPIO_L_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_05_0_SCR                   GPIO_L_SCR_05_0
#define GPIO_L_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_05_0
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x112a4)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_L_SCR_05_0
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_05_0
#define GPIO_L_INPUT_05_0                       _MK_ADDR_CONST(0x112a8)
#define GPIO_L_INPUT_05_0_SECURE                        0x0
#define GPIO_L_INPUT_05_0_SCR                   GPIO_L_SCR_05_0
#define GPIO_L_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_05_0
#define GPIO_L_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x112ac)
#define GPIO_L_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_05_0_SCR                  GPIO_L_SCR_05_0
#define GPIO_L_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_05_0
#define GPIO_L_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x112b0)
#define GPIO_L_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_05_0_SCR                    GPIO_L_SCR_05_0
#define GPIO_L_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_05_0
#define GPIO_L_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x112b4)
#define GPIO_L_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_05_0_SCR                         GPIO_L_SCR_05_0
#define GPIO_L_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70328 [0x112b8]

// Reserved address 70332 [0x112bc]

// Register GPIO_L_ENABLE_CONFIG_06_0
#define GPIO_L_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x112c0)
#define GPIO_L_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_06_0_SCR                   GPIO_L_SCR_06_0
#define GPIO_L_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_06_0
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x112c4)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_L_SCR_06_0
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_06_0
#define GPIO_L_INPUT_06_0                       _MK_ADDR_CONST(0x112c8)
#define GPIO_L_INPUT_06_0_SECURE                        0x0
#define GPIO_L_INPUT_06_0_SCR                   GPIO_L_SCR_06_0
#define GPIO_L_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_06_0
#define GPIO_L_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x112cc)
#define GPIO_L_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_06_0_SCR                  GPIO_L_SCR_06_0
#define GPIO_L_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_06_0
#define GPIO_L_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x112d0)
#define GPIO_L_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_06_0_SCR                    GPIO_L_SCR_06_0
#define GPIO_L_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_06_0
#define GPIO_L_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x112d4)
#define GPIO_L_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_06_0_SCR                         GPIO_L_SCR_06_0
#define GPIO_L_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70360 [0x112d8]

// Reserved address 70364 [0x112dc]

// Register GPIO_L_ENABLE_CONFIG_07_0
#define GPIO_L_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x112e0)
#define GPIO_L_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_07_0_SCR                   GPIO_L_SCR_07_0
#define GPIO_L_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_07_0
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x112e4)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_L_SCR_07_0
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_INPUT_07_0
#define GPIO_L_INPUT_07_0                       _MK_ADDR_CONST(0x112e8)
#define GPIO_L_INPUT_07_0_SECURE                        0x0
#define GPIO_L_INPUT_07_0_SCR                   GPIO_L_SCR_07_0
#define GPIO_L_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_L_OUTPUT_CONTROL_07_0
#define GPIO_L_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x112ec)
#define GPIO_L_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_07_0_SCR                  GPIO_L_SCR_07_0
#define GPIO_L_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_07_0
#define GPIO_L_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x112f0)
#define GPIO_L_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_07_0_SCR                    GPIO_L_SCR_07_0
#define GPIO_L_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_CLEAR_07_0
#define GPIO_L_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x112f4)
#define GPIO_L_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_07_0_SCR                         GPIO_L_SCR_07_0
#define GPIO_L_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70392 [0x112f8]

// Reserved address 70396 [0x112fc]

// Register GPIO_L_INTERRUPT_STATUS_G0_0
#define GPIO_L_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11300)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G1_0
#define GPIO_L_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11304)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G2_0
#define GPIO_L_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11308)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G3_0
#define GPIO_L_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1130c)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G4_0
#define GPIO_L_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11310)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G5_0
#define GPIO_L_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11314)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G6_0
#define GPIO_L_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11318)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_L_INTERRUPT_STATUS_G7_0
#define GPIO_L_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1131c)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 70432 [0x11320]

// Reserved address 70436 [0x11324]

// Reserved address 70440 [0x11328]

// Reserved address 70444 [0x1132c]

// Reserved address 70448 [0x11330]

// Reserved address 70452 [0x11334]

// Reserved address 70456 [0x11338]

// Reserved address 70460 [0x1133c]

// Reserved address 70464 [0x11340]

// Reserved address 70468 [0x11344]

// Reserved address 70472 [0x11348]

// Reserved address 70476 [0x1134c]

// Reserved address 70480 [0x11350]

// Reserved address 70484 [0x11354]

// Reserved address 70488 [0x11358]

// Reserved address 70492 [0x1135c]

// Reserved address 70496 [0x11360]

// Reserved address 70500 [0x11364]

// Reserved address 70504 [0x11368]

// Reserved address 70508 [0x1136c]

// Reserved address 70512 [0x11370]

// Reserved address 70516 [0x11374]

// Reserved address 70520 [0x11378]

// Reserved address 70524 [0x1137c]

// Reserved address 70528 [0x11380]

// Reserved address 70532 [0x11384]

// Reserved address 70536 [0x11388]

// Reserved address 70540 [0x1138c]

// Reserved address 70544 [0x11390]

// Reserved address 70548 [0x11394]

// Reserved address 70552 [0x11398]

// Reserved address 70556 [0x1139c]

// Reserved address 70560 [0x113a0]

// Reserved address 70564 [0x113a4]

// Reserved address 70568 [0x113a8]

// Reserved address 70572 [0x113ac]

// Reserved address 70576 [0x113b0]

// Reserved address 70580 [0x113b4]

// Reserved address 70584 [0x113b8]

// Reserved address 70588 [0x113bc]

// Reserved address 70592 [0x113c0]

// Reserved address 70596 [0x113c4]

// Reserved address 70600 [0x113c8]

// Reserved address 70604 [0x113cc]

// Reserved address 70608 [0x113d0]

// Reserved address 70612 [0x113d4]

// Reserved address 70616 [0x113d8]

// Reserved address 70620 [0x113dc]

// Reserved address 70624 [0x113e0]

// Reserved address 70628 [0x113e4]

// Reserved address 70632 [0x113e8]

// Reserved address 70636 [0x113ec]

// Reserved address 70640 [0x113f0]

// Reserved address 70644 [0x113f4]

// Reserved address 70648 [0x113f8]

// Reserved address 70652 [0x113fc]

// Register GPIO_X_ENABLE_CONFIG_00_0
#define GPIO_X_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11400)
#define GPIO_X_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11404)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_X_SCR_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_00_0
#define GPIO_X_INPUT_00_0                       _MK_ADDR_CONST(0x11408)
#define GPIO_X_INPUT_00_0_SECURE                        0x0
#define GPIO_X_INPUT_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1140c)
#define GPIO_X_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_SCR                  GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_00_0
#define GPIO_X_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11410)
#define GPIO_X_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_00_0_SCR                    GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11414)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_SCR                         GPIO_X_SCR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70680 [0x11418]

// Reserved address 70684 [0x1141c]

// Register GPIO_X_ENABLE_CONFIG_01_0
#define GPIO_X_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11420)
#define GPIO_X_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11424)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_X_SCR_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_01_0
#define GPIO_X_INPUT_01_0                       _MK_ADDR_CONST(0x11428)
#define GPIO_X_INPUT_01_0_SECURE                        0x0
#define GPIO_X_INPUT_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1142c)
#define GPIO_X_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_SCR                  GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_01_0
#define GPIO_X_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11430)
#define GPIO_X_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_01_0_SCR                    GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11434)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_SCR                         GPIO_X_SCR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70712 [0x11438]

// Reserved address 70716 [0x1143c]

// Register GPIO_X_ENABLE_CONFIG_02_0
#define GPIO_X_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11440)
#define GPIO_X_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11444)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_X_SCR_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_02_0
#define GPIO_X_INPUT_02_0                       _MK_ADDR_CONST(0x11448)
#define GPIO_X_INPUT_02_0_SECURE                        0x0
#define GPIO_X_INPUT_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1144c)
#define GPIO_X_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_SCR                  GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_02_0
#define GPIO_X_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11450)
#define GPIO_X_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_02_0_SCR                    GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11454)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_SCR                         GPIO_X_SCR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70744 [0x11458]

// Reserved address 70748 [0x1145c]

// Register GPIO_X_ENABLE_CONFIG_03_0
#define GPIO_X_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11460)
#define GPIO_X_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11464)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_X_SCR_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_03_0
#define GPIO_X_INPUT_03_0                       _MK_ADDR_CONST(0x11468)
#define GPIO_X_INPUT_03_0_SECURE                        0x0
#define GPIO_X_INPUT_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1146c)
#define GPIO_X_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_SCR                  GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_03_0
#define GPIO_X_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11470)
#define GPIO_X_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_03_0_SCR                    GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11474)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_SCR                         GPIO_X_SCR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70776 [0x11478]

// Reserved address 70780 [0x1147c]

// Register GPIO_X_ENABLE_CONFIG_04_0
#define GPIO_X_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11480)
#define GPIO_X_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11484)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_X_SCR_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_04_0
#define GPIO_X_INPUT_04_0                       _MK_ADDR_CONST(0x11488)
#define GPIO_X_INPUT_04_0_SECURE                        0x0
#define GPIO_X_INPUT_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1148c)
#define GPIO_X_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_SCR                  GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_04_0
#define GPIO_X_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11490)
#define GPIO_X_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_04_0_SCR                    GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11494)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_SCR                         GPIO_X_SCR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70808 [0x11498]

// Reserved address 70812 [0x1149c]

// Register GPIO_X_ENABLE_CONFIG_05_0
#define GPIO_X_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x114a0)
#define GPIO_X_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x114a4)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_X_SCR_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_05_0
#define GPIO_X_INPUT_05_0                       _MK_ADDR_CONST(0x114a8)
#define GPIO_X_INPUT_05_0_SECURE                        0x0
#define GPIO_X_INPUT_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x114ac)
#define GPIO_X_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_SCR                  GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_05_0
#define GPIO_X_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x114b0)
#define GPIO_X_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_05_0_SCR                    GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x114b4)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_SCR                         GPIO_X_SCR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70840 [0x114b8]

// Reserved address 70844 [0x114bc]

// Register GPIO_X_ENABLE_CONFIG_06_0
#define GPIO_X_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x114c0)
#define GPIO_X_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x114c4)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_X_SCR_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_06_0
#define GPIO_X_INPUT_06_0                       _MK_ADDR_CONST(0x114c8)
#define GPIO_X_INPUT_06_0_SECURE                        0x0
#define GPIO_X_INPUT_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x114cc)
#define GPIO_X_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_SCR                  GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_06_0
#define GPIO_X_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x114d0)
#define GPIO_X_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_06_0_SCR                    GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x114d4)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_SCR                         GPIO_X_SCR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70872 [0x114d8]

// Reserved address 70876 [0x114dc]

// Register GPIO_X_ENABLE_CONFIG_07_0
#define GPIO_X_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x114e0)
#define GPIO_X_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x114e4)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_X_SCR_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_INPUT_07_0
#define GPIO_X_INPUT_07_0                       _MK_ADDR_CONST(0x114e8)
#define GPIO_X_INPUT_07_0_SECURE                        0x0
#define GPIO_X_INPUT_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_X_OUTPUT_CONTROL_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x114ec)
#define GPIO_X_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_SCR                  GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_07_0
#define GPIO_X_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x114f0)
#define GPIO_X_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_07_0_SCR                    GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_CLEAR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x114f4)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_SCR                         GPIO_X_SCR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 70904 [0x114f8]

// Reserved address 70908 [0x114fc]

// Register GPIO_X_INTERRUPT_STATUS_G0_0
#define GPIO_X_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11500)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G1_0
#define GPIO_X_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11504)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G2_0
#define GPIO_X_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11508)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G3_0
#define GPIO_X_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1150c)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G4_0
#define GPIO_X_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11510)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G5_0
#define GPIO_X_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11514)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G6_0
#define GPIO_X_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11518)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_X_INTERRUPT_STATUS_G7_0
#define GPIO_X_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1151c)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 70944 [0x11520]

// Reserved address 70948 [0x11524]

// Reserved address 70952 [0x11528]

// Reserved address 70956 [0x1152c]

// Reserved address 70960 [0x11530]

// Reserved address 70964 [0x11534]

// Reserved address 70968 [0x11538]

// Reserved address 70972 [0x1153c]

// Reserved address 70976 [0x11540]

// Reserved address 70980 [0x11544]

// Reserved address 70984 [0x11548]

// Reserved address 70988 [0x1154c]

// Reserved address 70992 [0x11550]

// Reserved address 70996 [0x11554]

// Reserved address 71000 [0x11558]

// Reserved address 71004 [0x1155c]

// Reserved address 71008 [0x11560]

// Reserved address 71012 [0x11564]

// Reserved address 71016 [0x11568]

// Reserved address 71020 [0x1156c]

// Reserved address 71024 [0x11570]

// Reserved address 71028 [0x11574]

// Reserved address 71032 [0x11578]

// Reserved address 71036 [0x1157c]

// Reserved address 71040 [0x11580]

// Reserved address 71044 [0x11584]

// Reserved address 71048 [0x11588]

// Reserved address 71052 [0x1158c]

// Reserved address 71056 [0x11590]

// Reserved address 71060 [0x11594]

// Reserved address 71064 [0x11598]

// Reserved address 71068 [0x1159c]

// Reserved address 71072 [0x115a0]

// Reserved address 71076 [0x115a4]

// Reserved address 71080 [0x115a8]

// Reserved address 71084 [0x115ac]

// Reserved address 71088 [0x115b0]

// Reserved address 71092 [0x115b4]

// Reserved address 71096 [0x115b8]

// Reserved address 71100 [0x115bc]

// Reserved address 71104 [0x115c0]

// Reserved address 71108 [0x115c4]

// Reserved address 71112 [0x115c8]

// Reserved address 71116 [0x115cc]

// Reserved address 71120 [0x115d0]

// Reserved address 71124 [0x115d4]

// Reserved address 71128 [0x115d8]

// Reserved address 71132 [0x115dc]

// Reserved address 71136 [0x115e0]

// Reserved address 71140 [0x115e4]

// Reserved address 71144 [0x115e8]

// Reserved address 71148 [0x115ec]

// Reserved address 71152 [0x115f0]

// Reserved address 71156 [0x115f4]

// Reserved address 71160 [0x115f8]

// Reserved address 71164 [0x115fc]

// Register GPIO_Y_ENABLE_CONFIG_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11600)
#define GPIO_Y_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11604)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Y_SCR_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_00_0
#define GPIO_Y_INPUT_00_0                       _MK_ADDR_CONST(0x11608)
#define GPIO_Y_INPUT_00_0_SECURE                        0x0
#define GPIO_Y_INPUT_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1160c)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_SCR                  GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11610)
#define GPIO_Y_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_SCR                    GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11614)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Y_SCR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71192 [0x11618]

// Reserved address 71196 [0x1161c]

// Register GPIO_Y_ENABLE_CONFIG_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11620)
#define GPIO_Y_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11624)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Y_SCR_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_01_0
#define GPIO_Y_INPUT_01_0                       _MK_ADDR_CONST(0x11628)
#define GPIO_Y_INPUT_01_0_SECURE                        0x0
#define GPIO_Y_INPUT_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1162c)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_SCR                  GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11630)
#define GPIO_Y_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_SCR                    GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11634)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Y_SCR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71224 [0x11638]

// Reserved address 71228 [0x1163c]

// Register GPIO_Y_ENABLE_CONFIG_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11640)
#define GPIO_Y_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11644)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Y_SCR_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_02_0
#define GPIO_Y_INPUT_02_0                       _MK_ADDR_CONST(0x11648)
#define GPIO_Y_INPUT_02_0_SECURE                        0x0
#define GPIO_Y_INPUT_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1164c)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_SCR                  GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11650)
#define GPIO_Y_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_SCR                    GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11654)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Y_SCR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71256 [0x11658]

// Reserved address 71260 [0x1165c]

// Register GPIO_Y_ENABLE_CONFIG_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11660)
#define GPIO_Y_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11664)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Y_SCR_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_03_0
#define GPIO_Y_INPUT_03_0                       _MK_ADDR_CONST(0x11668)
#define GPIO_Y_INPUT_03_0_SECURE                        0x0
#define GPIO_Y_INPUT_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1166c)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_SCR                  GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11670)
#define GPIO_Y_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_SCR                    GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11674)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Y_SCR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71288 [0x11678]

// Reserved address 71292 [0x1167c]

// Register GPIO_Y_ENABLE_CONFIG_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11680)
#define GPIO_Y_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11684)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Y_SCR_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_04_0
#define GPIO_Y_INPUT_04_0                       _MK_ADDR_CONST(0x11688)
#define GPIO_Y_INPUT_04_0_SECURE                        0x0
#define GPIO_Y_INPUT_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1168c)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_SCR                  GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11690)
#define GPIO_Y_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_SCR                    GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11694)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Y_SCR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71320 [0x11698]

// Reserved address 71324 [0x1169c]

// Register GPIO_Y_ENABLE_CONFIG_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x116a0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x116a4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Y_SCR_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_05_0
#define GPIO_Y_INPUT_05_0                       _MK_ADDR_CONST(0x116a8)
#define GPIO_Y_INPUT_05_0_SECURE                        0x0
#define GPIO_Y_INPUT_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x116ac)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_SCR                  GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x116b0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_SCR                    GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x116b4)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Y_SCR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71352 [0x116b8]

// Reserved address 71356 [0x116bc]

// Register GPIO_Y_ENABLE_CONFIG_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x116c0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x116c4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Y_SCR_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_INPUT_06_0
#define GPIO_Y_INPUT_06_0                       _MK_ADDR_CONST(0x116c8)
#define GPIO_Y_INPUT_06_0_SECURE                        0x0
#define GPIO_Y_INPUT_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_Y_OUTPUT_CONTROL_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x116cc)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_SCR                  GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x116d0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_SCR                    GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_CLEAR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x116d4)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Y_SCR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 71384 [0x116d8]

// Reserved address 71388 [0x116dc]

// Reserved address 71392 [0x116e0]

// Reserved address 71396 [0x116e4]

// Reserved address 71400 [0x116e8]

// Reserved address 71404 [0x116ec]

// Reserved address 71408 [0x116f0]

// Reserved address 71412 [0x116f4]

// Reserved address 71416 [0x116f8]

// Reserved address 71420 [0x116fc]

// Register GPIO_Y_INTERRUPT_STATUS_G0_0
#define GPIO_Y_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11700)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G1_0
#define GPIO_Y_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11704)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G2_0
#define GPIO_Y_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11708)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G3_0
#define GPIO_Y_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1170c)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G4_0
#define GPIO_Y_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11710)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G5_0
#define GPIO_Y_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11714)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G6_0
#define GPIO_Y_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11718)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_Y_INTERRUPT_STATUS_G7_0
#define GPIO_Y_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1171c)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 71456 [0x11720]

// Reserved address 71460 [0x11724]

// Reserved address 71464 [0x11728]

// Reserved address 71468 [0x1172c]

// Reserved address 71472 [0x11730]

// Reserved address 71476 [0x11734]

// Reserved address 71480 [0x11738]

// Reserved address 71484 [0x1173c]

// Reserved address 71488 [0x11740]

// Reserved address 71492 [0x11744]

// Reserved address 71496 [0x11748]

// Reserved address 71500 [0x1174c]

// Reserved address 71504 [0x11750]

// Reserved address 71508 [0x11754]

// Reserved address 71512 [0x11758]

// Reserved address 71516 [0x1175c]

// Reserved address 71520 [0x11760]

// Reserved address 71524 [0x11764]

// Reserved address 71528 [0x11768]

// Reserved address 71532 [0x1176c]

// Reserved address 71536 [0x11770]

// Reserved address 71540 [0x11774]

// Reserved address 71544 [0x11778]

// Reserved address 71548 [0x1177c]

// Reserved address 71552 [0x11780]

// Reserved address 71556 [0x11784]

// Reserved address 71560 [0x11788]

// Reserved address 71564 [0x1178c]

// Reserved address 71568 [0x11790]

// Reserved address 71572 [0x11794]

// Reserved address 71576 [0x11798]

// Reserved address 71580 [0x1179c]

// Reserved address 71584 [0x117a0]

// Reserved address 71588 [0x117a4]

// Reserved address 71592 [0x117a8]

// Reserved address 71596 [0x117ac]

// Reserved address 71600 [0x117b0]

// Reserved address 71604 [0x117b4]

// Reserved address 71608 [0x117b8]

// Reserved address 71612 [0x117bc]

// Reserved address 71616 [0x117c0]

// Reserved address 71620 [0x117c4]

// Reserved address 71624 [0x117c8]

// Reserved address 71628 [0x117cc]

// Reserved address 71632 [0x117d0]

// Reserved address 71636 [0x117d4]

// Reserved address 71640 [0x117d8]

// Reserved address 71644 [0x117dc]

// Reserved address 71648 [0x117e0]

// Reserved address 71652 [0x117e4]

// Reserved address 71656 [0x117e8]

// Reserved address 71660 [0x117ec]

// Reserved address 71664 [0x117f0]

// Reserved address 71668 [0x117f4]

// Reserved address 71672 [0x117f8]

// Reserved address 71676 [0x117fc]

// Register GPIO_A_ENABLE_CONFIG_00_0
#define GPIO_A_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12000)
#define GPIO_A_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12004)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_A_SCR_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_00_0
#define GPIO_A_INPUT_00_0                       _MK_ADDR_CONST(0x12008)
#define GPIO_A_INPUT_00_0_SECURE                        0x0
#define GPIO_A_INPUT_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1200c)
#define GPIO_A_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_SCR                  GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_00_0
#define GPIO_A_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12010)
#define GPIO_A_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_00_0_SCR                    GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12014)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_SCR                         GPIO_A_SCR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73752 [0x12018]

// Reserved address 73756 [0x1201c]

// Register GPIO_A_ENABLE_CONFIG_01_0
#define GPIO_A_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12020)
#define GPIO_A_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12024)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_A_SCR_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_01_0
#define GPIO_A_INPUT_01_0                       _MK_ADDR_CONST(0x12028)
#define GPIO_A_INPUT_01_0_SECURE                        0x0
#define GPIO_A_INPUT_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1202c)
#define GPIO_A_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_SCR                  GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_01_0
#define GPIO_A_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12030)
#define GPIO_A_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_01_0_SCR                    GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12034)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_SCR                         GPIO_A_SCR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73784 [0x12038]

// Reserved address 73788 [0x1203c]

// Register GPIO_A_ENABLE_CONFIG_02_0
#define GPIO_A_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12040)
#define GPIO_A_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12044)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_A_SCR_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_02_0
#define GPIO_A_INPUT_02_0                       _MK_ADDR_CONST(0x12048)
#define GPIO_A_INPUT_02_0_SECURE                        0x0
#define GPIO_A_INPUT_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1204c)
#define GPIO_A_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_SCR                  GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_02_0
#define GPIO_A_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12050)
#define GPIO_A_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_02_0_SCR                    GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12054)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_SCR                         GPIO_A_SCR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73816 [0x12058]

// Reserved address 73820 [0x1205c]

// Register GPIO_A_ENABLE_CONFIG_03_0
#define GPIO_A_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12060)
#define GPIO_A_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12064)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_A_SCR_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_03_0
#define GPIO_A_INPUT_03_0                       _MK_ADDR_CONST(0x12068)
#define GPIO_A_INPUT_03_0_SECURE                        0x0
#define GPIO_A_INPUT_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1206c)
#define GPIO_A_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_SCR                  GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_03_0
#define GPIO_A_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12070)
#define GPIO_A_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_03_0_SCR                    GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12074)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_SCR                         GPIO_A_SCR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73848 [0x12078]

// Reserved address 73852 [0x1207c]

// Register GPIO_A_ENABLE_CONFIG_04_0
#define GPIO_A_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12080)
#define GPIO_A_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12084)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_A_SCR_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_04_0
#define GPIO_A_INPUT_04_0                       _MK_ADDR_CONST(0x12088)
#define GPIO_A_INPUT_04_0_SECURE                        0x0
#define GPIO_A_INPUT_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1208c)
#define GPIO_A_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_SCR                  GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_04_0
#define GPIO_A_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12090)
#define GPIO_A_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_04_0_SCR                    GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12094)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_SCR                         GPIO_A_SCR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73880 [0x12098]

// Reserved address 73884 [0x1209c]

// Register GPIO_A_ENABLE_CONFIG_05_0
#define GPIO_A_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x120a0)
#define GPIO_A_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x120a4)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_A_SCR_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_05_0
#define GPIO_A_INPUT_05_0                       _MK_ADDR_CONST(0x120a8)
#define GPIO_A_INPUT_05_0_SECURE                        0x0
#define GPIO_A_INPUT_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x120ac)
#define GPIO_A_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_SCR                  GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_05_0
#define GPIO_A_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x120b0)
#define GPIO_A_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_05_0_SCR                    GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x120b4)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_SCR                         GPIO_A_SCR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73912 [0x120b8]

// Reserved address 73916 [0x120bc]

// Register GPIO_A_ENABLE_CONFIG_06_0
#define GPIO_A_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x120c0)
#define GPIO_A_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x120c4)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_A_SCR_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_INPUT_06_0
#define GPIO_A_INPUT_06_0                       _MK_ADDR_CONST(0x120c8)
#define GPIO_A_INPUT_06_0_SECURE                        0x0
#define GPIO_A_INPUT_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_A_OUTPUT_CONTROL_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x120cc)
#define GPIO_A_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_SCR                  GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_06_0
#define GPIO_A_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x120d0)
#define GPIO_A_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_06_0_SCR                    GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_CLEAR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x120d4)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_SCR                         GPIO_A_SCR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 73944 [0x120d8]

// Reserved address 73948 [0x120dc]

// Reserved address 73952 [0x120e0]

// Reserved address 73956 [0x120e4]

// Reserved address 73960 [0x120e8]

// Reserved address 73964 [0x120ec]

// Reserved address 73968 [0x120f0]

// Reserved address 73972 [0x120f4]

// Reserved address 73976 [0x120f8]

// Reserved address 73980 [0x120fc]

// Register GPIO_A_INTERRUPT_STATUS_G0_0
#define GPIO_A_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12100)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G1_0
#define GPIO_A_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12104)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G2_0
#define GPIO_A_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12108)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G3_0
#define GPIO_A_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1210c)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G4_0
#define GPIO_A_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12110)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G5_0
#define GPIO_A_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12114)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G6_0
#define GPIO_A_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12118)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_A_INTERRUPT_STATUS_G7_0
#define GPIO_A_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1211c)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 74016 [0x12120]

// Reserved address 74020 [0x12124]

// Reserved address 74024 [0x12128]

// Reserved address 74028 [0x1212c]

// Reserved address 74032 [0x12130]

// Reserved address 74036 [0x12134]

// Reserved address 74040 [0x12138]

// Reserved address 74044 [0x1213c]

// Reserved address 74048 [0x12140]

// Reserved address 74052 [0x12144]

// Reserved address 74056 [0x12148]

// Reserved address 74060 [0x1214c]

// Reserved address 74064 [0x12150]

// Reserved address 74068 [0x12154]

// Reserved address 74072 [0x12158]

// Reserved address 74076 [0x1215c]

// Reserved address 74080 [0x12160]

// Reserved address 74084 [0x12164]

// Reserved address 74088 [0x12168]

// Reserved address 74092 [0x1216c]

// Reserved address 74096 [0x12170]

// Reserved address 74100 [0x12174]

// Reserved address 74104 [0x12178]

// Reserved address 74108 [0x1217c]

// Reserved address 74112 [0x12180]

// Reserved address 74116 [0x12184]

// Reserved address 74120 [0x12188]

// Reserved address 74124 [0x1218c]

// Reserved address 74128 [0x12190]

// Reserved address 74132 [0x12194]

// Reserved address 74136 [0x12198]

// Reserved address 74140 [0x1219c]

// Reserved address 74144 [0x121a0]

// Reserved address 74148 [0x121a4]

// Reserved address 74152 [0x121a8]

// Reserved address 74156 [0x121ac]

// Reserved address 74160 [0x121b0]

// Reserved address 74164 [0x121b4]

// Reserved address 74168 [0x121b8]

// Reserved address 74172 [0x121bc]

// Reserved address 74176 [0x121c0]

// Reserved address 74180 [0x121c4]

// Reserved address 74184 [0x121c8]

// Reserved address 74188 [0x121cc]

// Reserved address 74192 [0x121d0]

// Reserved address 74196 [0x121d4]

// Reserved address 74200 [0x121d8]

// Reserved address 74204 [0x121dc]

// Reserved address 74208 [0x121e0]

// Reserved address 74212 [0x121e4]

// Reserved address 74216 [0x121e8]

// Reserved address 74220 [0x121ec]

// Reserved address 74224 [0x121f0]

// Reserved address 74228 [0x121f4]

// Reserved address 74232 [0x121f8]

// Reserved address 74236 [0x121fc]

// Register GPIO_E_ENABLE_CONFIG_00_0
#define GPIO_E_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12200)
#define GPIO_E_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12204)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_E_SCR_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_00_0
#define GPIO_E_INPUT_00_0                       _MK_ADDR_CONST(0x12208)
#define GPIO_E_INPUT_00_0_SECURE                        0x0
#define GPIO_E_INPUT_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1220c)
#define GPIO_E_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_SCR                  GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_00_0
#define GPIO_E_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12210)
#define GPIO_E_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_00_0_SCR                    GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12214)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_SCR                         GPIO_E_SCR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74264 [0x12218]

// Reserved address 74268 [0x1221c]

// Register GPIO_E_ENABLE_CONFIG_01_0
#define GPIO_E_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12220)
#define GPIO_E_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12224)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_E_SCR_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_01_0
#define GPIO_E_INPUT_01_0                       _MK_ADDR_CONST(0x12228)
#define GPIO_E_INPUT_01_0_SECURE                        0x0
#define GPIO_E_INPUT_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1222c)
#define GPIO_E_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_SCR                  GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_01_0
#define GPIO_E_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12230)
#define GPIO_E_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_01_0_SCR                    GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12234)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_SCR                         GPIO_E_SCR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74296 [0x12238]

// Reserved address 74300 [0x1223c]

// Register GPIO_E_ENABLE_CONFIG_02_0
#define GPIO_E_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12240)
#define GPIO_E_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12244)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_E_SCR_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_02_0
#define GPIO_E_INPUT_02_0                       _MK_ADDR_CONST(0x12248)
#define GPIO_E_INPUT_02_0_SECURE                        0x0
#define GPIO_E_INPUT_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1224c)
#define GPIO_E_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_SCR                  GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_02_0
#define GPIO_E_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12250)
#define GPIO_E_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_02_0_SCR                    GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12254)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_SCR                         GPIO_E_SCR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74328 [0x12258]

// Reserved address 74332 [0x1225c]

// Register GPIO_E_ENABLE_CONFIG_03_0
#define GPIO_E_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12260)
#define GPIO_E_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12264)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_E_SCR_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_03_0
#define GPIO_E_INPUT_03_0                       _MK_ADDR_CONST(0x12268)
#define GPIO_E_INPUT_03_0_SECURE                        0x0
#define GPIO_E_INPUT_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1226c)
#define GPIO_E_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_SCR                  GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_03_0
#define GPIO_E_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12270)
#define GPIO_E_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_03_0_SCR                    GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12274)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_SCR                         GPIO_E_SCR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74360 [0x12278]

// Reserved address 74364 [0x1227c]

// Register GPIO_E_ENABLE_CONFIG_04_0
#define GPIO_E_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12280)
#define GPIO_E_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12284)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_E_SCR_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_04_0
#define GPIO_E_INPUT_04_0                       _MK_ADDR_CONST(0x12288)
#define GPIO_E_INPUT_04_0_SECURE                        0x0
#define GPIO_E_INPUT_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1228c)
#define GPIO_E_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_SCR                  GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_04_0
#define GPIO_E_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12290)
#define GPIO_E_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_04_0_SCR                    GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12294)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_SCR                         GPIO_E_SCR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74392 [0x12298]

// Reserved address 74396 [0x1229c]

// Register GPIO_E_ENABLE_CONFIG_05_0
#define GPIO_E_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x122a0)
#define GPIO_E_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x122a4)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_E_SCR_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_05_0
#define GPIO_E_INPUT_05_0                       _MK_ADDR_CONST(0x122a8)
#define GPIO_E_INPUT_05_0_SECURE                        0x0
#define GPIO_E_INPUT_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x122ac)
#define GPIO_E_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_SCR                  GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_05_0
#define GPIO_E_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x122b0)
#define GPIO_E_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_05_0_SCR                    GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x122b4)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_SCR                         GPIO_E_SCR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74424 [0x122b8]

// Reserved address 74428 [0x122bc]

// Register GPIO_E_ENABLE_CONFIG_06_0
#define GPIO_E_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x122c0)
#define GPIO_E_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x122c4)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_E_SCR_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_06_0
#define GPIO_E_INPUT_06_0                       _MK_ADDR_CONST(0x122c8)
#define GPIO_E_INPUT_06_0_SECURE                        0x0
#define GPIO_E_INPUT_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x122cc)
#define GPIO_E_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_SCR                  GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_06_0
#define GPIO_E_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x122d0)
#define GPIO_E_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_06_0_SCR                    GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x122d4)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_SCR                         GPIO_E_SCR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74456 [0x122d8]

// Reserved address 74460 [0x122dc]

// Register GPIO_E_ENABLE_CONFIG_07_0
#define GPIO_E_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x122e0)
#define GPIO_E_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x122e4)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_E_SCR_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_INPUT_07_0
#define GPIO_E_INPUT_07_0                       _MK_ADDR_CONST(0x122e8)
#define GPIO_E_INPUT_07_0_SECURE                        0x0
#define GPIO_E_INPUT_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_E_OUTPUT_CONTROL_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x122ec)
#define GPIO_E_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_SCR                  GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_07_0
#define GPIO_E_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x122f0)
#define GPIO_E_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_07_0_SCR                    GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_CLEAR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x122f4)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_SCR                         GPIO_E_SCR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74488 [0x122f8]

// Reserved address 74492 [0x122fc]

// Register GPIO_E_INTERRUPT_STATUS_G0_0
#define GPIO_E_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12300)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G1_0
#define GPIO_E_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12304)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G2_0
#define GPIO_E_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12308)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G3_0
#define GPIO_E_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1230c)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G4_0
#define GPIO_E_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12310)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G5_0
#define GPIO_E_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12314)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G6_0
#define GPIO_E_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12318)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_E_INTERRUPT_STATUS_G7_0
#define GPIO_E_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1231c)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 74528 [0x12320]

// Reserved address 74532 [0x12324]

// Reserved address 74536 [0x12328]

// Reserved address 74540 [0x1232c]

// Reserved address 74544 [0x12330]

// Reserved address 74548 [0x12334]

// Reserved address 74552 [0x12338]

// Reserved address 74556 [0x1233c]

// Reserved address 74560 [0x12340]

// Reserved address 74564 [0x12344]

// Reserved address 74568 [0x12348]

// Reserved address 74572 [0x1234c]

// Reserved address 74576 [0x12350]

// Reserved address 74580 [0x12354]

// Reserved address 74584 [0x12358]

// Reserved address 74588 [0x1235c]

// Reserved address 74592 [0x12360]

// Reserved address 74596 [0x12364]

// Reserved address 74600 [0x12368]

// Reserved address 74604 [0x1236c]

// Reserved address 74608 [0x12370]

// Reserved address 74612 [0x12374]

// Reserved address 74616 [0x12378]

// Reserved address 74620 [0x1237c]

// Reserved address 74624 [0x12380]

// Reserved address 74628 [0x12384]

// Reserved address 74632 [0x12388]

// Reserved address 74636 [0x1238c]

// Reserved address 74640 [0x12390]

// Reserved address 74644 [0x12394]

// Reserved address 74648 [0x12398]

// Reserved address 74652 [0x1239c]

// Reserved address 74656 [0x123a0]

// Reserved address 74660 [0x123a4]

// Reserved address 74664 [0x123a8]

// Reserved address 74668 [0x123ac]

// Reserved address 74672 [0x123b0]

// Reserved address 74676 [0x123b4]

// Reserved address 74680 [0x123b8]

// Reserved address 74684 [0x123bc]

// Reserved address 74688 [0x123c0]

// Reserved address 74692 [0x123c4]

// Reserved address 74696 [0x123c8]

// Reserved address 74700 [0x123cc]

// Reserved address 74704 [0x123d0]

// Reserved address 74708 [0x123d4]

// Reserved address 74712 [0x123d8]

// Reserved address 74716 [0x123dc]

// Reserved address 74720 [0x123e0]

// Reserved address 74724 [0x123e4]

// Reserved address 74728 [0x123e8]

// Reserved address 74732 [0x123ec]

// Reserved address 74736 [0x123f0]

// Reserved address 74740 [0x123f4]

// Reserved address 74744 [0x123f8]

// Reserved address 74748 [0x123fc]

// Register GPIO_F_ENABLE_CONFIG_00_0
#define GPIO_F_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12400)
#define GPIO_F_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12404)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_F_SCR_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_00_0
#define GPIO_F_INPUT_00_0                       _MK_ADDR_CONST(0x12408)
#define GPIO_F_INPUT_00_0_SECURE                        0x0
#define GPIO_F_INPUT_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1240c)
#define GPIO_F_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_SCR                  GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_00_0
#define GPIO_F_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12410)
#define GPIO_F_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_00_0_SCR                    GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12414)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_SCR                         GPIO_F_SCR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74776 [0x12418]

// Reserved address 74780 [0x1241c]

// Register GPIO_F_ENABLE_CONFIG_01_0
#define GPIO_F_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12420)
#define GPIO_F_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12424)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_F_SCR_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_01_0
#define GPIO_F_INPUT_01_0                       _MK_ADDR_CONST(0x12428)
#define GPIO_F_INPUT_01_0_SECURE                        0x0
#define GPIO_F_INPUT_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1242c)
#define GPIO_F_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_SCR                  GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_01_0
#define GPIO_F_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12430)
#define GPIO_F_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_01_0_SCR                    GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12434)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_SCR                         GPIO_F_SCR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74808 [0x12438]

// Reserved address 74812 [0x1243c]

// Register GPIO_F_ENABLE_CONFIG_02_0
#define GPIO_F_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12440)
#define GPIO_F_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12444)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_F_SCR_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_02_0
#define GPIO_F_INPUT_02_0                       _MK_ADDR_CONST(0x12448)
#define GPIO_F_INPUT_02_0_SECURE                        0x0
#define GPIO_F_INPUT_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1244c)
#define GPIO_F_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_SCR                  GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_02_0
#define GPIO_F_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12450)
#define GPIO_F_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_02_0_SCR                    GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12454)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_SCR                         GPIO_F_SCR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74840 [0x12458]

// Reserved address 74844 [0x1245c]

// Register GPIO_F_ENABLE_CONFIG_03_0
#define GPIO_F_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12460)
#define GPIO_F_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12464)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_F_SCR_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_03_0
#define GPIO_F_INPUT_03_0                       _MK_ADDR_CONST(0x12468)
#define GPIO_F_INPUT_03_0_SECURE                        0x0
#define GPIO_F_INPUT_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1246c)
#define GPIO_F_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_SCR                  GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_03_0
#define GPIO_F_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12470)
#define GPIO_F_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_03_0_SCR                    GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12474)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_SCR                         GPIO_F_SCR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74872 [0x12478]

// Reserved address 74876 [0x1247c]

// Register GPIO_F_ENABLE_CONFIG_04_0
#define GPIO_F_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12480)
#define GPIO_F_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12484)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_F_SCR_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_04_0
#define GPIO_F_INPUT_04_0                       _MK_ADDR_CONST(0x12488)
#define GPIO_F_INPUT_04_0_SECURE                        0x0
#define GPIO_F_INPUT_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1248c)
#define GPIO_F_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_SCR                  GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_04_0
#define GPIO_F_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12490)
#define GPIO_F_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_04_0_SCR                    GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12494)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_SCR                         GPIO_F_SCR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74904 [0x12498]

// Reserved address 74908 [0x1249c]

// Register GPIO_F_ENABLE_CONFIG_05_0
#define GPIO_F_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x124a0)
#define GPIO_F_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x124a4)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_F_SCR_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_INPUT_05_0
#define GPIO_F_INPUT_05_0                       _MK_ADDR_CONST(0x124a8)
#define GPIO_F_INPUT_05_0_SECURE                        0x0
#define GPIO_F_INPUT_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_F_OUTPUT_CONTROL_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x124ac)
#define GPIO_F_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_SCR                  GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_05_0
#define GPIO_F_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x124b0)
#define GPIO_F_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_05_0_SCR                    GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_CLEAR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x124b4)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_SCR                         GPIO_F_SCR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 74936 [0x124b8]

// Reserved address 74940 [0x124bc]

// Reserved address 74944 [0x124c0]

// Reserved address 74948 [0x124c4]

// Reserved address 74952 [0x124c8]

// Reserved address 74956 [0x124cc]

// Reserved address 74960 [0x124d0]

// Reserved address 74964 [0x124d4]

// Reserved address 74968 [0x124d8]

// Reserved address 74972 [0x124dc]

// Reserved address 74976 [0x124e0]

// Reserved address 74980 [0x124e4]

// Reserved address 74984 [0x124e8]

// Reserved address 74988 [0x124ec]

// Reserved address 74992 [0x124f0]

// Reserved address 74996 [0x124f4]

// Reserved address 75000 [0x124f8]

// Reserved address 75004 [0x124fc]

// Register GPIO_F_INTERRUPT_STATUS_G0_0
#define GPIO_F_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12500)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G1_0
#define GPIO_F_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12504)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G2_0
#define GPIO_F_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12508)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G3_0
#define GPIO_F_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1250c)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G4_0
#define GPIO_F_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12510)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G5_0
#define GPIO_F_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12514)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G6_0
#define GPIO_F_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12518)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_F_INTERRUPT_STATUS_G7_0
#define GPIO_F_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1251c)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 75040 [0x12520]

// Reserved address 75044 [0x12524]

// Reserved address 75048 [0x12528]

// Reserved address 75052 [0x1252c]

// Reserved address 75056 [0x12530]

// Reserved address 75060 [0x12534]

// Reserved address 75064 [0x12538]

// Reserved address 75068 [0x1253c]

// Reserved address 75072 [0x12540]

// Reserved address 75076 [0x12544]

// Reserved address 75080 [0x12548]

// Reserved address 75084 [0x1254c]

// Reserved address 75088 [0x12550]

// Reserved address 75092 [0x12554]

// Reserved address 75096 [0x12558]

// Reserved address 75100 [0x1255c]

// Reserved address 75104 [0x12560]

// Reserved address 75108 [0x12564]

// Reserved address 75112 [0x12568]

// Reserved address 75116 [0x1256c]

// Reserved address 75120 [0x12570]

// Reserved address 75124 [0x12574]

// Reserved address 75128 [0x12578]

// Reserved address 75132 [0x1257c]

// Reserved address 75136 [0x12580]

// Reserved address 75140 [0x12584]

// Reserved address 75144 [0x12588]

// Reserved address 75148 [0x1258c]

// Reserved address 75152 [0x12590]

// Reserved address 75156 [0x12594]

// Reserved address 75160 [0x12598]

// Reserved address 75164 [0x1259c]

// Reserved address 75168 [0x125a0]

// Reserved address 75172 [0x125a4]

// Reserved address 75176 [0x125a8]

// Reserved address 75180 [0x125ac]

// Reserved address 75184 [0x125b0]

// Reserved address 75188 [0x125b4]

// Reserved address 75192 [0x125b8]

// Reserved address 75196 [0x125bc]

// Reserved address 75200 [0x125c0]

// Reserved address 75204 [0x125c4]

// Reserved address 75208 [0x125c8]

// Reserved address 75212 [0x125cc]

// Reserved address 75216 [0x125d0]

// Reserved address 75220 [0x125d4]

// Reserved address 75224 [0x125d8]

// Reserved address 75228 [0x125dc]

// Reserved address 75232 [0x125e0]

// Reserved address 75236 [0x125e4]

// Reserved address 75240 [0x125e8]

// Reserved address 75244 [0x125ec]

// Reserved address 75248 [0x125f0]

// Reserved address 75252 [0x125f4]

// Reserved address 75256 [0x125f8]

// Reserved address 75260 [0x125fc]

// Register GPIO_BB_ENABLE_CONFIG_00_0
#define GPIO_BB_ENABLE_CONFIG_00_0                      _MK_ADDR_CONST(0x12600)
#define GPIO_BB_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_SCR                  GPIO_BB_SCR_00_0
#define GPIO_BB_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_00_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0                 _MK_ADDR_CONST(0x12604)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_BB_SCR_00_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_BB_INPUT_00_0
#define GPIO_BB_INPUT_00_0                      _MK_ADDR_CONST(0x12608)
#define GPIO_BB_INPUT_00_0_SECURE                       0x0
#define GPIO_BB_INPUT_00_0_SCR                  GPIO_BB_SCR_00_0
#define GPIO_BB_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_00_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_BB_OUTPUT_CONTROL_00_0
#define GPIO_BB_OUTPUT_CONTROL_00_0                     _MK_ADDR_CONST(0x1260c)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_00_0_SCR                         GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_00_0
#define GPIO_BB_OUTPUT_VALUE_00_0                       _MK_ADDR_CONST(0x12610)
#define GPIO_BB_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_00_0_SCR                   GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_CLEAR_00_0
#define GPIO_BB_INTERRUPT_CLEAR_00_0                    _MK_ADDR_CONST(0x12614)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SCR                        GPIO_BB_SCR_00_0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 75288 [0x12618]

// Reserved address 75292 [0x1261c]

// Register GPIO_BB_ENABLE_CONFIG_01_0
#define GPIO_BB_ENABLE_CONFIG_01_0                      _MK_ADDR_CONST(0x12620)
#define GPIO_BB_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_SCR                  GPIO_BB_SCR_01_0
#define GPIO_BB_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_01_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0                 _MK_ADDR_CONST(0x12624)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_BB_SCR_01_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_BB_INPUT_01_0
#define GPIO_BB_INPUT_01_0                      _MK_ADDR_CONST(0x12628)
#define GPIO_BB_INPUT_01_0_SECURE                       0x0
#define GPIO_BB_INPUT_01_0_SCR                  GPIO_BB_SCR_01_0
#define GPIO_BB_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_01_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_BB_OUTPUT_CONTROL_01_0
#define GPIO_BB_OUTPUT_CONTROL_01_0                     _MK_ADDR_CONST(0x1262c)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_01_0_SCR                         GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_01_0
#define GPIO_BB_OUTPUT_VALUE_01_0                       _MK_ADDR_CONST(0x12630)
#define GPIO_BB_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_01_0_SCR                   GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_CLEAR_01_0
#define GPIO_BB_INTERRUPT_CLEAR_01_0                    _MK_ADDR_CONST(0x12634)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SCR                        GPIO_BB_SCR_01_0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 75320 [0x12638]

// Reserved address 75324 [0x1263c]

// Reserved address 75328 [0x12640]

// Reserved address 75332 [0x12644]

// Reserved address 75336 [0x12648]

// Reserved address 75340 [0x1264c]

// Reserved address 75344 [0x12650]

// Reserved address 75348 [0x12654]

// Reserved address 75352 [0x12658]

// Reserved address 75356 [0x1265c]

// Reserved address 75360 [0x12660]

// Reserved address 75364 [0x12664]

// Reserved address 75368 [0x12668]

// Reserved address 75372 [0x1266c]

// Reserved address 75376 [0x12670]

// Reserved address 75380 [0x12674]

// Reserved address 75384 [0x12678]

// Reserved address 75388 [0x1267c]

// Reserved address 75392 [0x12680]

// Reserved address 75396 [0x12684]

// Reserved address 75400 [0x12688]

// Reserved address 75404 [0x1268c]

// Reserved address 75408 [0x12690]

// Reserved address 75412 [0x12694]

// Reserved address 75416 [0x12698]

// Reserved address 75420 [0x1269c]

// Reserved address 75424 [0x126a0]

// Reserved address 75428 [0x126a4]

// Reserved address 75432 [0x126a8]

// Reserved address 75436 [0x126ac]

// Reserved address 75440 [0x126b0]

// Reserved address 75444 [0x126b4]

// Reserved address 75448 [0x126b8]

// Reserved address 75452 [0x126bc]

// Reserved address 75456 [0x126c0]

// Reserved address 75460 [0x126c4]

// Reserved address 75464 [0x126c8]

// Reserved address 75468 [0x126cc]

// Reserved address 75472 [0x126d0]

// Reserved address 75476 [0x126d4]

// Reserved address 75480 [0x126d8]

// Reserved address 75484 [0x126dc]

// Reserved address 75488 [0x126e0]

// Reserved address 75492 [0x126e4]

// Reserved address 75496 [0x126e8]

// Reserved address 75500 [0x126ec]

// Reserved address 75504 [0x126f0]

// Reserved address 75508 [0x126f4]

// Reserved address 75512 [0x126f8]

// Reserved address 75516 [0x126fc]

// Register GPIO_BB_INTERRUPT_STATUS_G0_0
#define GPIO_BB_INTERRUPT_STATUS_G0_0                   _MK_ADDR_CONST(0x12700)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G1_0
#define GPIO_BB_INTERRUPT_STATUS_G1_0                   _MK_ADDR_CONST(0x12704)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G2_0
#define GPIO_BB_INTERRUPT_STATUS_G2_0                   _MK_ADDR_CONST(0x12708)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G3_0
#define GPIO_BB_INTERRUPT_STATUS_G3_0                   _MK_ADDR_CONST(0x1270c)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G4_0
#define GPIO_BB_INTERRUPT_STATUS_G4_0                   _MK_ADDR_CONST(0x12710)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G5_0
#define GPIO_BB_INTERRUPT_STATUS_G5_0                   _MK_ADDR_CONST(0x12714)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G6_0
#define GPIO_BB_INTERRUPT_STATUS_G6_0                   _MK_ADDR_CONST(0x12718)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_BB_INTERRUPT_STATUS_G7_0
#define GPIO_BB_INTERRUPT_STATUS_G7_0                   _MK_ADDR_CONST(0x1271c)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 75552 [0x12720]

// Reserved address 75556 [0x12724]

// Reserved address 75560 [0x12728]

// Reserved address 75564 [0x1272c]

// Reserved address 75568 [0x12730]

// Reserved address 75572 [0x12734]

// Reserved address 75576 [0x12738]

// Reserved address 75580 [0x1273c]

// Reserved address 75584 [0x12740]

// Reserved address 75588 [0x12744]

// Reserved address 75592 [0x12748]

// Reserved address 75596 [0x1274c]

// Reserved address 75600 [0x12750]

// Reserved address 75604 [0x12754]

// Reserved address 75608 [0x12758]

// Reserved address 75612 [0x1275c]

// Reserved address 75616 [0x12760]

// Reserved address 75620 [0x12764]

// Reserved address 75624 [0x12768]

// Reserved address 75628 [0x1276c]

// Reserved address 75632 [0x12770]

// Reserved address 75636 [0x12774]

// Reserved address 75640 [0x12778]

// Reserved address 75644 [0x1277c]

// Reserved address 75648 [0x12780]

// Reserved address 75652 [0x12784]

// Reserved address 75656 [0x12788]

// Reserved address 75660 [0x1278c]

// Reserved address 75664 [0x12790]

// Reserved address 75668 [0x12794]

// Reserved address 75672 [0x12798]

// Reserved address 75676 [0x1279c]

// Reserved address 75680 [0x127a0]

// Reserved address 75684 [0x127a4]

// Reserved address 75688 [0x127a8]

// Reserved address 75692 [0x127ac]

// Reserved address 75696 [0x127b0]

// Reserved address 75700 [0x127b4]

// Reserved address 75704 [0x127b8]

// Reserved address 75708 [0x127bc]

// Reserved address 75712 [0x127c0]

// Reserved address 75716 [0x127c4]

// Reserved address 75720 [0x127c8]

// Reserved address 75724 [0x127cc]

// Reserved address 75728 [0x127d0]

// Reserved address 75732 [0x127d4]

// Reserved address 75736 [0x127d8]

// Reserved address 75740 [0x127dc]

// Reserved address 75744 [0x127e0]

// Reserved address 75748 [0x127e4]

// Reserved address 75752 [0x127e8]

// Reserved address 75756 [0x127ec]

// Reserved address 75760 [0x127f0]

// Reserved address 75764 [0x127f4]

// Reserved address 75768 [0x127f8]

// Reserved address 75772 [0x127fc]

// Register GPIO_B_ENABLE_CONFIG_00_0
#define GPIO_B_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13000)
#define GPIO_B_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13004)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_B_SCR_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_00_0
#define GPIO_B_INPUT_00_0                       _MK_ADDR_CONST(0x13008)
#define GPIO_B_INPUT_00_0_SECURE                        0x0
#define GPIO_B_INPUT_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1300c)
#define GPIO_B_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_SCR                  GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_00_0
#define GPIO_B_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13010)
#define GPIO_B_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_00_0_SCR                    GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13014)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_SCR                         GPIO_B_SCR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 77848 [0x13018]

// Reserved address 77852 [0x1301c]

// Register GPIO_B_ENABLE_CONFIG_01_0
#define GPIO_B_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13020)
#define GPIO_B_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_01_0_SCR                   GPIO_B_SCR_01_0
#define GPIO_B_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_01_0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13024)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_B_SCR_01_0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_01_0
#define GPIO_B_INPUT_01_0                       _MK_ADDR_CONST(0x13028)
#define GPIO_B_INPUT_01_0_SECURE                        0x0
#define GPIO_B_INPUT_01_0_SCR                   GPIO_B_SCR_01_0
#define GPIO_B_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_01_0
#define GPIO_B_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1302c)
#define GPIO_B_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_01_0_SCR                  GPIO_B_SCR_01_0
#define GPIO_B_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_01_0
#define GPIO_B_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13030)
#define GPIO_B_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_01_0_SCR                    GPIO_B_SCR_01_0
#define GPIO_B_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_01_0
#define GPIO_B_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13034)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_01_0_SCR                         GPIO_B_SCR_01_0
#define GPIO_B_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 77880 [0x13038]

// Reserved address 77884 [0x1303c]

// Register GPIO_B_ENABLE_CONFIG_02_0
#define GPIO_B_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13040)
#define GPIO_B_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_02_0_SCR                   GPIO_B_SCR_02_0
#define GPIO_B_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_02_0
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13044)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_B_SCR_02_0
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_02_0
#define GPIO_B_INPUT_02_0                       _MK_ADDR_CONST(0x13048)
#define GPIO_B_INPUT_02_0_SECURE                        0x0
#define GPIO_B_INPUT_02_0_SCR                   GPIO_B_SCR_02_0
#define GPIO_B_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_02_0
#define GPIO_B_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1304c)
#define GPIO_B_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_02_0_SCR                  GPIO_B_SCR_02_0
#define GPIO_B_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_02_0
#define GPIO_B_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13050)
#define GPIO_B_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_02_0_SCR                    GPIO_B_SCR_02_0
#define GPIO_B_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_02_0
#define GPIO_B_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13054)
#define GPIO_B_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_02_0_SCR                         GPIO_B_SCR_02_0
#define GPIO_B_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 77912 [0x13058]

// Reserved address 77916 [0x1305c]

// Register GPIO_B_ENABLE_CONFIG_03_0
#define GPIO_B_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13060)
#define GPIO_B_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_03_0_SCR                   GPIO_B_SCR_03_0
#define GPIO_B_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_03_0
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13064)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_B_SCR_03_0
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_03_0
#define GPIO_B_INPUT_03_0                       _MK_ADDR_CONST(0x13068)
#define GPIO_B_INPUT_03_0_SECURE                        0x0
#define GPIO_B_INPUT_03_0_SCR                   GPIO_B_SCR_03_0
#define GPIO_B_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_03_0
#define GPIO_B_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1306c)
#define GPIO_B_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_03_0_SCR                  GPIO_B_SCR_03_0
#define GPIO_B_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_03_0
#define GPIO_B_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13070)
#define GPIO_B_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_03_0_SCR                    GPIO_B_SCR_03_0
#define GPIO_B_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_03_0
#define GPIO_B_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13074)
#define GPIO_B_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_03_0_SCR                         GPIO_B_SCR_03_0
#define GPIO_B_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 77944 [0x13078]

// Reserved address 77948 [0x1307c]

// Register GPIO_B_ENABLE_CONFIG_04_0
#define GPIO_B_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13080)
#define GPIO_B_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_04_0_SCR                   GPIO_B_SCR_04_0
#define GPIO_B_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_04_0
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13084)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_B_SCR_04_0
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_04_0
#define GPIO_B_INPUT_04_0                       _MK_ADDR_CONST(0x13088)
#define GPIO_B_INPUT_04_0_SECURE                        0x0
#define GPIO_B_INPUT_04_0_SCR                   GPIO_B_SCR_04_0
#define GPIO_B_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_04_0
#define GPIO_B_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1308c)
#define GPIO_B_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_04_0_SCR                  GPIO_B_SCR_04_0
#define GPIO_B_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_04_0
#define GPIO_B_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13090)
#define GPIO_B_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_04_0_SCR                    GPIO_B_SCR_04_0
#define GPIO_B_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_04_0
#define GPIO_B_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13094)
#define GPIO_B_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_04_0_SCR                         GPIO_B_SCR_04_0
#define GPIO_B_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 77976 [0x13098]

// Reserved address 77980 [0x1309c]

// Register GPIO_B_ENABLE_CONFIG_05_0
#define GPIO_B_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x130a0)
#define GPIO_B_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_05_0_SCR                   GPIO_B_SCR_05_0
#define GPIO_B_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_05_0
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x130a4)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_B_SCR_05_0
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_05_0
#define GPIO_B_INPUT_05_0                       _MK_ADDR_CONST(0x130a8)
#define GPIO_B_INPUT_05_0_SECURE                        0x0
#define GPIO_B_INPUT_05_0_SCR                   GPIO_B_SCR_05_0
#define GPIO_B_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_05_0
#define GPIO_B_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x130ac)
#define GPIO_B_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_05_0_SCR                  GPIO_B_SCR_05_0
#define GPIO_B_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_05_0
#define GPIO_B_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x130b0)
#define GPIO_B_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_05_0_SCR                    GPIO_B_SCR_05_0
#define GPIO_B_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_05_0
#define GPIO_B_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x130b4)
#define GPIO_B_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_05_0_SCR                         GPIO_B_SCR_05_0
#define GPIO_B_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78008 [0x130b8]

// Reserved address 78012 [0x130bc]

// Register GPIO_B_ENABLE_CONFIG_06_0
#define GPIO_B_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x130c0)
#define GPIO_B_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_06_0_SCR                   GPIO_B_SCR_06_0
#define GPIO_B_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_06_0
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x130c4)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_B_SCR_06_0
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_INPUT_06_0
#define GPIO_B_INPUT_06_0                       _MK_ADDR_CONST(0x130c8)
#define GPIO_B_INPUT_06_0_SECURE                        0x0
#define GPIO_B_INPUT_06_0_SCR                   GPIO_B_SCR_06_0
#define GPIO_B_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_B_OUTPUT_CONTROL_06_0
#define GPIO_B_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x130cc)
#define GPIO_B_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_06_0_SCR                  GPIO_B_SCR_06_0
#define GPIO_B_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_06_0
#define GPIO_B_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x130d0)
#define GPIO_B_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_06_0_SCR                    GPIO_B_SCR_06_0
#define GPIO_B_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_CLEAR_06_0
#define GPIO_B_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x130d4)
#define GPIO_B_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_06_0_SCR                         GPIO_B_SCR_06_0
#define GPIO_B_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78040 [0x130d8]

// Reserved address 78044 [0x130dc]

// Reserved address 78048 [0x130e0]

// Reserved address 78052 [0x130e4]

// Reserved address 78056 [0x130e8]

// Reserved address 78060 [0x130ec]

// Reserved address 78064 [0x130f0]

// Reserved address 78068 [0x130f4]

// Reserved address 78072 [0x130f8]

// Reserved address 78076 [0x130fc]

// Register GPIO_B_INTERRUPT_STATUS_G0_0
#define GPIO_B_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13100)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G1_0
#define GPIO_B_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13104)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G2_0
#define GPIO_B_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13108)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G3_0
#define GPIO_B_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1310c)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G4_0
#define GPIO_B_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13110)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G5_0
#define GPIO_B_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13114)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G6_0
#define GPIO_B_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13118)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_B_INTERRUPT_STATUS_G7_0
#define GPIO_B_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1311c)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 78112 [0x13120]

// Reserved address 78116 [0x13124]

// Reserved address 78120 [0x13128]

// Reserved address 78124 [0x1312c]

// Reserved address 78128 [0x13130]

// Reserved address 78132 [0x13134]

// Reserved address 78136 [0x13138]

// Reserved address 78140 [0x1313c]

// Reserved address 78144 [0x13140]

// Reserved address 78148 [0x13144]

// Reserved address 78152 [0x13148]

// Reserved address 78156 [0x1314c]

// Reserved address 78160 [0x13150]

// Reserved address 78164 [0x13154]

// Reserved address 78168 [0x13158]

// Reserved address 78172 [0x1315c]

// Reserved address 78176 [0x13160]

// Reserved address 78180 [0x13164]

// Reserved address 78184 [0x13168]

// Reserved address 78188 [0x1316c]

// Reserved address 78192 [0x13170]

// Reserved address 78196 [0x13174]

// Reserved address 78200 [0x13178]

// Reserved address 78204 [0x1317c]

// Reserved address 78208 [0x13180]

// Reserved address 78212 [0x13184]

// Reserved address 78216 [0x13188]

// Reserved address 78220 [0x1318c]

// Reserved address 78224 [0x13190]

// Reserved address 78228 [0x13194]

// Reserved address 78232 [0x13198]

// Reserved address 78236 [0x1319c]

// Reserved address 78240 [0x131a0]

// Reserved address 78244 [0x131a4]

// Reserved address 78248 [0x131a8]

// Reserved address 78252 [0x131ac]

// Reserved address 78256 [0x131b0]

// Reserved address 78260 [0x131b4]

// Reserved address 78264 [0x131b8]

// Reserved address 78268 [0x131bc]

// Reserved address 78272 [0x131c0]

// Reserved address 78276 [0x131c4]

// Reserved address 78280 [0x131c8]

// Reserved address 78284 [0x131cc]

// Reserved address 78288 [0x131d0]

// Reserved address 78292 [0x131d4]

// Reserved address 78296 [0x131d8]

// Reserved address 78300 [0x131dc]

// Reserved address 78304 [0x131e0]

// Reserved address 78308 [0x131e4]

// Reserved address 78312 [0x131e8]

// Reserved address 78316 [0x131ec]

// Reserved address 78320 [0x131f0]

// Reserved address 78324 [0x131f4]

// Reserved address 78328 [0x131f8]

// Reserved address 78332 [0x131fc]

// Register GPIO_C_ENABLE_CONFIG_00_0
#define GPIO_C_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13200)
#define GPIO_C_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13204)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_C_SCR_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_00_0
#define GPIO_C_INPUT_00_0                       _MK_ADDR_CONST(0x13208)
#define GPIO_C_INPUT_00_0_SECURE                        0x0
#define GPIO_C_INPUT_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1320c)
#define GPIO_C_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_SCR                  GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_00_0
#define GPIO_C_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13210)
#define GPIO_C_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_00_0_SCR                    GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13214)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_SCR                         GPIO_C_SCR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78360 [0x13218]

// Reserved address 78364 [0x1321c]

// Register GPIO_C_ENABLE_CONFIG_01_0
#define GPIO_C_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13220)
#define GPIO_C_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13224)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_C_SCR_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_01_0
#define GPIO_C_INPUT_01_0                       _MK_ADDR_CONST(0x13228)
#define GPIO_C_INPUT_01_0_SECURE                        0x0
#define GPIO_C_INPUT_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1322c)
#define GPIO_C_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_SCR                  GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_01_0
#define GPIO_C_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13230)
#define GPIO_C_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_01_0_SCR                    GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13234)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_SCR                         GPIO_C_SCR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78392 [0x13238]

// Reserved address 78396 [0x1323c]

// Register GPIO_C_ENABLE_CONFIG_02_0
#define GPIO_C_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13240)
#define GPIO_C_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13244)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_C_SCR_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_02_0
#define GPIO_C_INPUT_02_0                       _MK_ADDR_CONST(0x13248)
#define GPIO_C_INPUT_02_0_SECURE                        0x0
#define GPIO_C_INPUT_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1324c)
#define GPIO_C_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_SCR                  GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_02_0
#define GPIO_C_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13250)
#define GPIO_C_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_02_0_SCR                    GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13254)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_SCR                         GPIO_C_SCR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78424 [0x13258]

// Reserved address 78428 [0x1325c]

// Register GPIO_C_ENABLE_CONFIG_03_0
#define GPIO_C_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13260)
#define GPIO_C_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13264)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_C_SCR_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_03_0
#define GPIO_C_INPUT_03_0                       _MK_ADDR_CONST(0x13268)
#define GPIO_C_INPUT_03_0_SECURE                        0x0
#define GPIO_C_INPUT_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1326c)
#define GPIO_C_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_SCR                  GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_03_0
#define GPIO_C_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13270)
#define GPIO_C_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_03_0_SCR                    GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13274)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_SCR                         GPIO_C_SCR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78456 [0x13278]

// Reserved address 78460 [0x1327c]

// Register GPIO_C_ENABLE_CONFIG_04_0
#define GPIO_C_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13280)
#define GPIO_C_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13284)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_C_SCR_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_04_0
#define GPIO_C_INPUT_04_0                       _MK_ADDR_CONST(0x13288)
#define GPIO_C_INPUT_04_0_SECURE                        0x0
#define GPIO_C_INPUT_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1328c)
#define GPIO_C_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_SCR                  GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_04_0
#define GPIO_C_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13290)
#define GPIO_C_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_04_0_SCR                    GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13294)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_SCR                         GPIO_C_SCR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78488 [0x13298]

// Reserved address 78492 [0x1329c]

// Register GPIO_C_ENABLE_CONFIG_05_0
#define GPIO_C_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x132a0)
#define GPIO_C_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x132a4)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_C_SCR_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_05_0
#define GPIO_C_INPUT_05_0                       _MK_ADDR_CONST(0x132a8)
#define GPIO_C_INPUT_05_0_SECURE                        0x0
#define GPIO_C_INPUT_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x132ac)
#define GPIO_C_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_SCR                  GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_05_0
#define GPIO_C_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x132b0)
#define GPIO_C_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_05_0_SCR                    GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x132b4)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_SCR                         GPIO_C_SCR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78520 [0x132b8]

// Reserved address 78524 [0x132bc]

// Register GPIO_C_ENABLE_CONFIG_06_0
#define GPIO_C_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x132c0)
#define GPIO_C_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x132c4)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_C_SCR_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_INPUT_06_0
#define GPIO_C_INPUT_06_0                       _MK_ADDR_CONST(0x132c8)
#define GPIO_C_INPUT_06_0_SECURE                        0x0
#define GPIO_C_INPUT_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_C_OUTPUT_CONTROL_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x132cc)
#define GPIO_C_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_SCR                  GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_06_0
#define GPIO_C_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x132d0)
#define GPIO_C_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_06_0_SCR                    GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_CLEAR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x132d4)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_SCR                         GPIO_C_SCR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78552 [0x132d8]

// Reserved address 78556 [0x132dc]

// Reserved address 78560 [0x132e0]

// Reserved address 78564 [0x132e4]

// Reserved address 78568 [0x132e8]

// Reserved address 78572 [0x132ec]

// Reserved address 78576 [0x132f0]

// Reserved address 78580 [0x132f4]

// Reserved address 78584 [0x132f8]

// Reserved address 78588 [0x132fc]

// Register GPIO_C_INTERRUPT_STATUS_G0_0
#define GPIO_C_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13300)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G1_0
#define GPIO_C_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13304)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G2_0
#define GPIO_C_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13308)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G3_0
#define GPIO_C_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1330c)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G4_0
#define GPIO_C_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13310)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G5_0
#define GPIO_C_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13314)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G6_0
#define GPIO_C_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13318)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_C_INTERRUPT_STATUS_G7_0
#define GPIO_C_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1331c)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 78624 [0x13320]

// Reserved address 78628 [0x13324]

// Reserved address 78632 [0x13328]

// Reserved address 78636 [0x1332c]

// Reserved address 78640 [0x13330]

// Reserved address 78644 [0x13334]

// Reserved address 78648 [0x13338]

// Reserved address 78652 [0x1333c]

// Reserved address 78656 [0x13340]

// Reserved address 78660 [0x13344]

// Reserved address 78664 [0x13348]

// Reserved address 78668 [0x1334c]

// Reserved address 78672 [0x13350]

// Reserved address 78676 [0x13354]

// Reserved address 78680 [0x13358]

// Reserved address 78684 [0x1335c]

// Reserved address 78688 [0x13360]

// Reserved address 78692 [0x13364]

// Reserved address 78696 [0x13368]

// Reserved address 78700 [0x1336c]

// Reserved address 78704 [0x13370]

// Reserved address 78708 [0x13374]

// Reserved address 78712 [0x13378]

// Reserved address 78716 [0x1337c]

// Reserved address 78720 [0x13380]

// Reserved address 78724 [0x13384]

// Reserved address 78728 [0x13388]

// Reserved address 78732 [0x1338c]

// Reserved address 78736 [0x13390]

// Reserved address 78740 [0x13394]

// Reserved address 78744 [0x13398]

// Reserved address 78748 [0x1339c]

// Reserved address 78752 [0x133a0]

// Reserved address 78756 [0x133a4]

// Reserved address 78760 [0x133a8]

// Reserved address 78764 [0x133ac]

// Reserved address 78768 [0x133b0]

// Reserved address 78772 [0x133b4]

// Reserved address 78776 [0x133b8]

// Reserved address 78780 [0x133bc]

// Reserved address 78784 [0x133c0]

// Reserved address 78788 [0x133c4]

// Reserved address 78792 [0x133c8]

// Reserved address 78796 [0x133cc]

// Reserved address 78800 [0x133d0]

// Reserved address 78804 [0x133d4]

// Reserved address 78808 [0x133d8]

// Reserved address 78812 [0x133dc]

// Reserved address 78816 [0x133e0]

// Reserved address 78820 [0x133e4]

// Reserved address 78824 [0x133e8]

// Reserved address 78828 [0x133ec]

// Reserved address 78832 [0x133f0]

// Reserved address 78836 [0x133f4]

// Reserved address 78840 [0x133f8]

// Reserved address 78844 [0x133fc]

// Register GPIO_D_ENABLE_CONFIG_00_0
#define GPIO_D_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13400)
#define GPIO_D_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13404)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_D_SCR_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_00_0
#define GPIO_D_INPUT_00_0                       _MK_ADDR_CONST(0x13408)
#define GPIO_D_INPUT_00_0_SECURE                        0x0
#define GPIO_D_INPUT_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1340c)
#define GPIO_D_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_SCR                  GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_00_0
#define GPIO_D_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13410)
#define GPIO_D_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_00_0_SCR                    GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13414)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_SCR                         GPIO_D_SCR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78872 [0x13418]

// Reserved address 78876 [0x1341c]

// Register GPIO_D_ENABLE_CONFIG_01_0
#define GPIO_D_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13420)
#define GPIO_D_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13424)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_D_SCR_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_01_0
#define GPIO_D_INPUT_01_0                       _MK_ADDR_CONST(0x13428)
#define GPIO_D_INPUT_01_0_SECURE                        0x0
#define GPIO_D_INPUT_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1342c)
#define GPIO_D_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_SCR                  GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_01_0
#define GPIO_D_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13430)
#define GPIO_D_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_01_0_SCR                    GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13434)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_SCR                         GPIO_D_SCR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78904 [0x13438]

// Reserved address 78908 [0x1343c]

// Register GPIO_D_ENABLE_CONFIG_02_0
#define GPIO_D_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13440)
#define GPIO_D_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13444)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_D_SCR_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_02_0
#define GPIO_D_INPUT_02_0                       _MK_ADDR_CONST(0x13448)
#define GPIO_D_INPUT_02_0_SECURE                        0x0
#define GPIO_D_INPUT_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1344c)
#define GPIO_D_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_SCR                  GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_02_0
#define GPIO_D_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13450)
#define GPIO_D_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_02_0_SCR                    GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13454)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_SCR                         GPIO_D_SCR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78936 [0x13458]

// Reserved address 78940 [0x1345c]

// Register GPIO_D_ENABLE_CONFIG_03_0
#define GPIO_D_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13460)
#define GPIO_D_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13464)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_D_SCR_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_03_0
#define GPIO_D_INPUT_03_0                       _MK_ADDR_CONST(0x13468)
#define GPIO_D_INPUT_03_0_SECURE                        0x0
#define GPIO_D_INPUT_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1346c)
#define GPIO_D_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_SCR                  GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_03_0
#define GPIO_D_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13470)
#define GPIO_D_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_03_0_SCR                    GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13474)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_SCR                         GPIO_D_SCR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 78968 [0x13478]

// Reserved address 78972 [0x1347c]

// Register GPIO_D_ENABLE_CONFIG_04_0
#define GPIO_D_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13480)
#define GPIO_D_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_04_0_SCR                   GPIO_D_SCR_04_0
#define GPIO_D_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_04_0
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13484)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_D_SCR_04_0
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_04_0
#define GPIO_D_INPUT_04_0                       _MK_ADDR_CONST(0x13488)
#define GPIO_D_INPUT_04_0_SECURE                        0x0
#define GPIO_D_INPUT_04_0_SCR                   GPIO_D_SCR_04_0
#define GPIO_D_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_04_0
#define GPIO_D_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1348c)
#define GPIO_D_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_04_0_SCR                  GPIO_D_SCR_04_0
#define GPIO_D_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_04_0
#define GPIO_D_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13490)
#define GPIO_D_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_04_0_SCR                    GPIO_D_SCR_04_0
#define GPIO_D_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_04_0
#define GPIO_D_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13494)
#define GPIO_D_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_04_0_SCR                         GPIO_D_SCR_04_0
#define GPIO_D_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 79000 [0x13498]

// Reserved address 79004 [0x1349c]

// Register GPIO_D_ENABLE_CONFIG_05_0
#define GPIO_D_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x134a0)
#define GPIO_D_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_05_0_SCR                   GPIO_D_SCR_05_0
#define GPIO_D_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_05_0
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x134a4)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_D_SCR_05_0
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_INPUT_05_0
#define GPIO_D_INPUT_05_0                       _MK_ADDR_CONST(0x134a8)
#define GPIO_D_INPUT_05_0_SECURE                        0x0
#define GPIO_D_INPUT_05_0_SCR                   GPIO_D_SCR_05_0
#define GPIO_D_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_D_OUTPUT_CONTROL_05_0
#define GPIO_D_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x134ac)
#define GPIO_D_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_05_0_SCR                  GPIO_D_SCR_05_0
#define GPIO_D_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_05_0
#define GPIO_D_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x134b0)
#define GPIO_D_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_05_0_SCR                    GPIO_D_SCR_05_0
#define GPIO_D_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_CLEAR_05_0
#define GPIO_D_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x134b4)
#define GPIO_D_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_05_0_SCR                         GPIO_D_SCR_05_0
#define GPIO_D_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 79032 [0x134b8]

// Reserved address 79036 [0x134bc]

// Reserved address 79040 [0x134c0]

// Reserved address 79044 [0x134c4]

// Reserved address 79048 [0x134c8]

// Reserved address 79052 [0x134cc]

// Reserved address 79056 [0x134d0]

// Reserved address 79060 [0x134d4]

// Reserved address 79064 [0x134d8]

// Reserved address 79068 [0x134dc]

// Reserved address 79072 [0x134e0]

// Reserved address 79076 [0x134e4]

// Reserved address 79080 [0x134e8]

// Reserved address 79084 [0x134ec]

// Reserved address 79088 [0x134f0]

// Reserved address 79092 [0x134f4]

// Reserved address 79096 [0x134f8]

// Reserved address 79100 [0x134fc]

// Register GPIO_D_INTERRUPT_STATUS_G0_0
#define GPIO_D_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13500)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G1_0
#define GPIO_D_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13504)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G2_0
#define GPIO_D_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13508)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G3_0
#define GPIO_D_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1350c)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G4_0
#define GPIO_D_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13510)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G5_0
#define GPIO_D_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13514)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G6_0
#define GPIO_D_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13518)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_D_INTERRUPT_STATUS_G7_0
#define GPIO_D_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1351c)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 79136 [0x13520]

// Reserved address 79140 [0x13524]

// Reserved address 79144 [0x13528]

// Reserved address 79148 [0x1352c]

// Reserved address 79152 [0x13530]

// Reserved address 79156 [0x13534]

// Reserved address 79160 [0x13538]

// Reserved address 79164 [0x1353c]

// Reserved address 79168 [0x13540]

// Reserved address 79172 [0x13544]

// Reserved address 79176 [0x13548]

// Reserved address 79180 [0x1354c]

// Reserved address 79184 [0x13550]

// Reserved address 79188 [0x13554]

// Reserved address 79192 [0x13558]

// Reserved address 79196 [0x1355c]

// Reserved address 79200 [0x13560]

// Reserved address 79204 [0x13564]

// Reserved address 79208 [0x13568]

// Reserved address 79212 [0x1356c]

// Reserved address 79216 [0x13570]

// Reserved address 79220 [0x13574]

// Reserved address 79224 [0x13578]

// Reserved address 79228 [0x1357c]

// Reserved address 79232 [0x13580]

// Reserved address 79236 [0x13584]

// Reserved address 79240 [0x13588]

// Reserved address 79244 [0x1358c]

// Reserved address 79248 [0x13590]

// Reserved address 79252 [0x13594]

// Reserved address 79256 [0x13598]

// Reserved address 79260 [0x1359c]

// Reserved address 79264 [0x135a0]

// Reserved address 79268 [0x135a4]

// Reserved address 79272 [0x135a8]

// Reserved address 79276 [0x135ac]

// Reserved address 79280 [0x135b0]

// Reserved address 79284 [0x135b4]

// Reserved address 79288 [0x135b8]

// Reserved address 79292 [0x135bc]

// Reserved address 79296 [0x135c0]

// Reserved address 79300 [0x135c4]

// Reserved address 79304 [0x135c8]

// Reserved address 79308 [0x135cc]

// Reserved address 79312 [0x135d0]

// Reserved address 79316 [0x135d4]

// Reserved address 79320 [0x135d8]

// Reserved address 79324 [0x135dc]

// Reserved address 79328 [0x135e0]

// Reserved address 79332 [0x135e4]

// Reserved address 79336 [0x135e8]

// Reserved address 79340 [0x135ec]

// Reserved address 79344 [0x135f0]

// Reserved address 79348 [0x135f4]

// Reserved address 79352 [0x135f8]

// Reserved address 79356 [0x135fc]

// Register GPIO_P_ENABLE_CONFIG_00_0
#define GPIO_P_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14000)
#define GPIO_P_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14004)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_P_SCR_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_00_0
#define GPIO_P_INPUT_00_0                       _MK_ADDR_CONST(0x14008)
#define GPIO_P_INPUT_00_0_SECURE                        0x0
#define GPIO_P_INPUT_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1400c)
#define GPIO_P_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_SCR                  GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_00_0
#define GPIO_P_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14010)
#define GPIO_P_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_00_0_SCR                    GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14014)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_SCR                         GPIO_P_SCR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 81944 [0x14018]

// Reserved address 81948 [0x1401c]

// Register GPIO_P_ENABLE_CONFIG_01_0
#define GPIO_P_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14020)
#define GPIO_P_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14024)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_P_SCR_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_01_0
#define GPIO_P_INPUT_01_0                       _MK_ADDR_CONST(0x14028)
#define GPIO_P_INPUT_01_0_SECURE                        0x0
#define GPIO_P_INPUT_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1402c)
#define GPIO_P_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_SCR                  GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_01_0
#define GPIO_P_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14030)
#define GPIO_P_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_01_0_SCR                    GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14034)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_SCR                         GPIO_P_SCR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 81976 [0x14038]

// Reserved address 81980 [0x1403c]

// Register GPIO_P_ENABLE_CONFIG_02_0
#define GPIO_P_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14040)
#define GPIO_P_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14044)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_P_SCR_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_02_0
#define GPIO_P_INPUT_02_0                       _MK_ADDR_CONST(0x14048)
#define GPIO_P_INPUT_02_0_SECURE                        0x0
#define GPIO_P_INPUT_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1404c)
#define GPIO_P_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_SCR                  GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_02_0
#define GPIO_P_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14050)
#define GPIO_P_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_02_0_SCR                    GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14054)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_SCR                         GPIO_P_SCR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82008 [0x14058]

// Reserved address 82012 [0x1405c]

// Register GPIO_P_ENABLE_CONFIG_03_0
#define GPIO_P_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14060)
#define GPIO_P_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14064)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_P_SCR_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_03_0
#define GPIO_P_INPUT_03_0                       _MK_ADDR_CONST(0x14068)
#define GPIO_P_INPUT_03_0_SECURE                        0x0
#define GPIO_P_INPUT_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1406c)
#define GPIO_P_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_SCR                  GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_03_0
#define GPIO_P_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14070)
#define GPIO_P_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_03_0_SCR                    GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14074)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_SCR                         GPIO_P_SCR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82040 [0x14078]

// Reserved address 82044 [0x1407c]

// Register GPIO_P_ENABLE_CONFIG_04_0
#define GPIO_P_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14080)
#define GPIO_P_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14084)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_P_SCR_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_04_0
#define GPIO_P_INPUT_04_0                       _MK_ADDR_CONST(0x14088)
#define GPIO_P_INPUT_04_0_SECURE                        0x0
#define GPIO_P_INPUT_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1408c)
#define GPIO_P_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_SCR                  GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_04_0
#define GPIO_P_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14090)
#define GPIO_P_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_04_0_SCR                    GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14094)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_SCR                         GPIO_P_SCR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82072 [0x14098]

// Reserved address 82076 [0x1409c]

// Register GPIO_P_ENABLE_CONFIG_05_0
#define GPIO_P_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x140a0)
#define GPIO_P_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x140a4)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_P_SCR_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_05_0
#define GPIO_P_INPUT_05_0                       _MK_ADDR_CONST(0x140a8)
#define GPIO_P_INPUT_05_0_SECURE                        0x0
#define GPIO_P_INPUT_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x140ac)
#define GPIO_P_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_SCR                  GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_05_0
#define GPIO_P_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x140b0)
#define GPIO_P_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_05_0_SCR                    GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x140b4)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_SCR                         GPIO_P_SCR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82104 [0x140b8]

// Reserved address 82108 [0x140bc]

// Register GPIO_P_ENABLE_CONFIG_06_0
#define GPIO_P_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x140c0)
#define GPIO_P_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x140c4)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_P_SCR_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_INPUT_06_0
#define GPIO_P_INPUT_06_0                       _MK_ADDR_CONST(0x140c8)
#define GPIO_P_INPUT_06_0_SECURE                        0x0
#define GPIO_P_INPUT_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_P_OUTPUT_CONTROL_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x140cc)
#define GPIO_P_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_SCR                  GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_06_0
#define GPIO_P_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x140d0)
#define GPIO_P_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_06_0_SCR                    GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_CLEAR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x140d4)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_SCR                         GPIO_P_SCR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82136 [0x140d8]

// Reserved address 82140 [0x140dc]

// Reserved address 82144 [0x140e0]

// Reserved address 82148 [0x140e4]

// Reserved address 82152 [0x140e8]

// Reserved address 82156 [0x140ec]

// Reserved address 82160 [0x140f0]

// Reserved address 82164 [0x140f4]

// Reserved address 82168 [0x140f8]

// Reserved address 82172 [0x140fc]

// Register GPIO_P_INTERRUPT_STATUS_G0_0
#define GPIO_P_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14100)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G1_0
#define GPIO_P_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14104)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G2_0
#define GPIO_P_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14108)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G3_0
#define GPIO_P_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1410c)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G4_0
#define GPIO_P_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14110)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G5_0
#define GPIO_P_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14114)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G6_0
#define GPIO_P_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14118)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_P_INTERRUPT_STATUS_G7_0
#define GPIO_P_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1411c)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7f, GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 82208 [0x14120]

// Reserved address 82212 [0x14124]

// Reserved address 82216 [0x14128]

// Reserved address 82220 [0x1412c]

// Reserved address 82224 [0x14130]

// Reserved address 82228 [0x14134]

// Reserved address 82232 [0x14138]

// Reserved address 82236 [0x1413c]

// Reserved address 82240 [0x14140]

// Reserved address 82244 [0x14144]

// Reserved address 82248 [0x14148]

// Reserved address 82252 [0x1414c]

// Reserved address 82256 [0x14150]

// Reserved address 82260 [0x14154]

// Reserved address 82264 [0x14158]

// Reserved address 82268 [0x1415c]

// Reserved address 82272 [0x14160]

// Reserved address 82276 [0x14164]

// Reserved address 82280 [0x14168]

// Reserved address 82284 [0x1416c]

// Reserved address 82288 [0x14170]

// Reserved address 82292 [0x14174]

// Reserved address 82296 [0x14178]

// Reserved address 82300 [0x1417c]

// Reserved address 82304 [0x14180]

// Reserved address 82308 [0x14184]

// Reserved address 82312 [0x14188]

// Reserved address 82316 [0x1418c]

// Reserved address 82320 [0x14190]

// Reserved address 82324 [0x14194]

// Reserved address 82328 [0x14198]

// Reserved address 82332 [0x1419c]

// Reserved address 82336 [0x141a0]

// Reserved address 82340 [0x141a4]

// Reserved address 82344 [0x141a8]

// Reserved address 82348 [0x141ac]

// Reserved address 82352 [0x141b0]

// Reserved address 82356 [0x141b4]

// Reserved address 82360 [0x141b8]

// Reserved address 82364 [0x141bc]

// Reserved address 82368 [0x141c0]

// Reserved address 82372 [0x141c4]

// Reserved address 82376 [0x141c8]

// Reserved address 82380 [0x141cc]

// Reserved address 82384 [0x141d0]

// Reserved address 82388 [0x141d4]

// Reserved address 82392 [0x141d8]

// Reserved address 82396 [0x141dc]

// Reserved address 82400 [0x141e0]

// Reserved address 82404 [0x141e4]

// Reserved address 82408 [0x141e8]

// Reserved address 82412 [0x141ec]

// Reserved address 82416 [0x141f0]

// Reserved address 82420 [0x141f4]

// Reserved address 82424 [0x141f8]

// Reserved address 82428 [0x141fc]

// Register GPIO_G_ENABLE_CONFIG_00_0
#define GPIO_G_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14200)
#define GPIO_G_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14204)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_G_SCR_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_00_0
#define GPIO_G_INPUT_00_0                       _MK_ADDR_CONST(0x14208)
#define GPIO_G_INPUT_00_0_SECURE                        0x0
#define GPIO_G_INPUT_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1420c)
#define GPIO_G_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_SCR                  GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_00_0
#define GPIO_G_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14210)
#define GPIO_G_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_00_0_SCR                    GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14214)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_SCR                         GPIO_G_SCR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82456 [0x14218]

// Reserved address 82460 [0x1421c]

// Register GPIO_G_ENABLE_CONFIG_01_0
#define GPIO_G_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14220)
#define GPIO_G_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14224)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_G_SCR_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_01_0
#define GPIO_G_INPUT_01_0                       _MK_ADDR_CONST(0x14228)
#define GPIO_G_INPUT_01_0_SECURE                        0x0
#define GPIO_G_INPUT_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1422c)
#define GPIO_G_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_SCR                  GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_01_0
#define GPIO_G_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14230)
#define GPIO_G_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_01_0_SCR                    GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14234)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_SCR                         GPIO_G_SCR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82488 [0x14238]

// Reserved address 82492 [0x1423c]

// Register GPIO_G_ENABLE_CONFIG_02_0
#define GPIO_G_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14240)
#define GPIO_G_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14244)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_G_SCR_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_02_0
#define GPIO_G_INPUT_02_0                       _MK_ADDR_CONST(0x14248)
#define GPIO_G_INPUT_02_0_SECURE                        0x0
#define GPIO_G_INPUT_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1424c)
#define GPIO_G_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_SCR                  GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_02_0
#define GPIO_G_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14250)
#define GPIO_G_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_02_0_SCR                    GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14254)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_SCR                         GPIO_G_SCR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82520 [0x14258]

// Reserved address 82524 [0x1425c]

// Register GPIO_G_ENABLE_CONFIG_03_0
#define GPIO_G_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14260)
#define GPIO_G_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14264)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_G_SCR_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_03_0
#define GPIO_G_INPUT_03_0                       _MK_ADDR_CONST(0x14268)
#define GPIO_G_INPUT_03_0_SECURE                        0x0
#define GPIO_G_INPUT_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1426c)
#define GPIO_G_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_SCR                  GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_03_0
#define GPIO_G_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14270)
#define GPIO_G_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_03_0_SCR                    GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14274)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_SCR                         GPIO_G_SCR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82552 [0x14278]

// Reserved address 82556 [0x1427c]

// Register GPIO_G_ENABLE_CONFIG_04_0
#define GPIO_G_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14280)
#define GPIO_G_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14284)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_G_SCR_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_04_0
#define GPIO_G_INPUT_04_0                       _MK_ADDR_CONST(0x14288)
#define GPIO_G_INPUT_04_0_SECURE                        0x0
#define GPIO_G_INPUT_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1428c)
#define GPIO_G_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_SCR                  GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_04_0
#define GPIO_G_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14290)
#define GPIO_G_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_04_0_SCR                    GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14294)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_SCR                         GPIO_G_SCR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82584 [0x14298]

// Reserved address 82588 [0x1429c]

// Register GPIO_G_ENABLE_CONFIG_05_0
#define GPIO_G_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x142a0)
#define GPIO_G_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x142a4)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_G_SCR_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_INPUT_05_0
#define GPIO_G_INPUT_05_0                       _MK_ADDR_CONST(0x142a8)
#define GPIO_G_INPUT_05_0_SECURE                        0x0
#define GPIO_G_INPUT_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_G_OUTPUT_CONTROL_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x142ac)
#define GPIO_G_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_SCR                  GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_05_0
#define GPIO_G_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x142b0)
#define GPIO_G_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_05_0_SCR                    GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_CLEAR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x142b4)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_SCR                         GPIO_G_SCR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 82616 [0x142b8]

// Reserved address 82620 [0x142bc]

// Reserved address 82624 [0x142c0]

// Reserved address 82628 [0x142c4]

// Reserved address 82632 [0x142c8]

// Reserved address 82636 [0x142cc]

// Reserved address 82640 [0x142d0]

// Reserved address 82644 [0x142d4]

// Reserved address 82648 [0x142d8]

// Reserved address 82652 [0x142dc]

// Reserved address 82656 [0x142e0]

// Reserved address 82660 [0x142e4]

// Reserved address 82664 [0x142e8]

// Reserved address 82668 [0x142ec]

// Reserved address 82672 [0x142f0]

// Reserved address 82676 [0x142f4]

// Reserved address 82680 [0x142f8]

// Reserved address 82684 [0x142fc]

// Register GPIO_G_INTERRUPT_STATUS_G0_0
#define GPIO_G_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14300)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G1_0
#define GPIO_G_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14304)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G2_0
#define GPIO_G_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14308)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G3_0
#define GPIO_G_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1430c)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G4_0
#define GPIO_G_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14310)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G5_0
#define GPIO_G_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14314)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G6_0
#define GPIO_G_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14318)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_G_INTERRUPT_STATUS_G7_0
#define GPIO_G_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1431c)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 82720 [0x14320]

// Reserved address 82724 [0x14324]

// Reserved address 82728 [0x14328]

// Reserved address 82732 [0x1432c]

// Reserved address 82736 [0x14330]

// Reserved address 82740 [0x14334]

// Reserved address 82744 [0x14338]

// Reserved address 82748 [0x1433c]

// Reserved address 82752 [0x14340]

// Reserved address 82756 [0x14344]

// Reserved address 82760 [0x14348]

// Reserved address 82764 [0x1434c]

// Reserved address 82768 [0x14350]

// Reserved address 82772 [0x14354]

// Reserved address 82776 [0x14358]

// Reserved address 82780 [0x1435c]

// Reserved address 82784 [0x14360]

// Reserved address 82788 [0x14364]

// Reserved address 82792 [0x14368]

// Reserved address 82796 [0x1436c]

// Reserved address 82800 [0x14370]

// Reserved address 82804 [0x14374]

// Reserved address 82808 [0x14378]

// Reserved address 82812 [0x1437c]

// Reserved address 82816 [0x14380]

// Reserved address 82820 [0x14384]

// Reserved address 82824 [0x14388]

// Reserved address 82828 [0x1438c]

// Reserved address 82832 [0x14390]

// Reserved address 82836 [0x14394]

// Reserved address 82840 [0x14398]

// Reserved address 82844 [0x1439c]

// Reserved address 82848 [0x143a0]

// Reserved address 82852 [0x143a4]

// Reserved address 82856 [0x143a8]

// Reserved address 82860 [0x143ac]

// Reserved address 82864 [0x143b0]

// Reserved address 82868 [0x143b4]

// Reserved address 82872 [0x143b8]

// Reserved address 82876 [0x143bc]

// Reserved address 82880 [0x143c0]

// Reserved address 82884 [0x143c4]

// Reserved address 82888 [0x143c8]

// Reserved address 82892 [0x143cc]

// Reserved address 82896 [0x143d0]

// Reserved address 82900 [0x143d4]

// Reserved address 82904 [0x143d8]

// Reserved address 82908 [0x143dc]

// Reserved address 82912 [0x143e0]

// Reserved address 82916 [0x143e4]

// Reserved address 82920 [0x143e8]

// Reserved address 82924 [0x143ec]

// Reserved address 82928 [0x143f0]

// Reserved address 82932 [0x143f4]

// Reserved address 82936 [0x143f8]

// Reserved address 82940 [0x143fc]

// Register GPIO_J_ENABLE_CONFIG_00_0
#define GPIO_J_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x15000)
#define GPIO_J_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x15004)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_J_SCR_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_00_0
#define GPIO_J_INPUT_00_0                       _MK_ADDR_CONST(0x15008)
#define GPIO_J_INPUT_00_0_SECURE                        0x0
#define GPIO_J_INPUT_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1500c)
#define GPIO_J_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_SCR                  GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_00_0
#define GPIO_J_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x15010)
#define GPIO_J_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_00_0_SCR                    GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x15014)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_SCR                         GPIO_J_SCR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86040 [0x15018]

// Reserved address 86044 [0x1501c]

// Register GPIO_J_ENABLE_CONFIG_01_0
#define GPIO_J_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x15020)
#define GPIO_J_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x15024)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_J_SCR_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_01_0
#define GPIO_J_INPUT_01_0                       _MK_ADDR_CONST(0x15028)
#define GPIO_J_INPUT_01_0_SECURE                        0x0
#define GPIO_J_INPUT_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1502c)
#define GPIO_J_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_SCR                  GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_01_0
#define GPIO_J_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x15030)
#define GPIO_J_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_01_0_SCR                    GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x15034)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_SCR                         GPIO_J_SCR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86072 [0x15038]

// Reserved address 86076 [0x1503c]

// Register GPIO_J_ENABLE_CONFIG_02_0
#define GPIO_J_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x15040)
#define GPIO_J_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x15044)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_J_SCR_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_02_0
#define GPIO_J_INPUT_02_0                       _MK_ADDR_CONST(0x15048)
#define GPIO_J_INPUT_02_0_SECURE                        0x0
#define GPIO_J_INPUT_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1504c)
#define GPIO_J_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_SCR                  GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_02_0
#define GPIO_J_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x15050)
#define GPIO_J_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_02_0_SCR                    GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x15054)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_SCR                         GPIO_J_SCR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86104 [0x15058]

// Reserved address 86108 [0x1505c]

// Register GPIO_J_ENABLE_CONFIG_03_0
#define GPIO_J_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x15060)
#define GPIO_J_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x15064)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_J_SCR_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_03_0
#define GPIO_J_INPUT_03_0                       _MK_ADDR_CONST(0x15068)
#define GPIO_J_INPUT_03_0_SECURE                        0x0
#define GPIO_J_INPUT_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1506c)
#define GPIO_J_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_SCR                  GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_03_0
#define GPIO_J_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x15070)
#define GPIO_J_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_03_0_SCR                    GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x15074)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_SCR                         GPIO_J_SCR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86136 [0x15078]

// Reserved address 86140 [0x1507c]

// Register GPIO_J_ENABLE_CONFIG_04_0
#define GPIO_J_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x15080)
#define GPIO_J_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x15084)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_J_SCR_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_04_0
#define GPIO_J_INPUT_04_0                       _MK_ADDR_CONST(0x15088)
#define GPIO_J_INPUT_04_0_SECURE                        0x0
#define GPIO_J_INPUT_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1508c)
#define GPIO_J_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_SCR                  GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_04_0
#define GPIO_J_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x15090)
#define GPIO_J_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_04_0_SCR                    GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x15094)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_SCR                         GPIO_J_SCR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86168 [0x15098]

// Reserved address 86172 [0x1509c]

// Register GPIO_J_ENABLE_CONFIG_05_0
#define GPIO_J_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x150a0)
#define GPIO_J_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x150a4)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_J_SCR_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_05_0
#define GPIO_J_INPUT_05_0                       _MK_ADDR_CONST(0x150a8)
#define GPIO_J_INPUT_05_0_SECURE                        0x0
#define GPIO_J_INPUT_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x150ac)
#define GPIO_J_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_SCR                  GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_05_0
#define GPIO_J_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x150b0)
#define GPIO_J_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_05_0_SCR                    GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x150b4)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_SCR                         GPIO_J_SCR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86200 [0x150b8]

// Reserved address 86204 [0x150bc]

// Register GPIO_J_ENABLE_CONFIG_06_0
#define GPIO_J_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x150c0)
#define GPIO_J_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_06_0_SCR                   GPIO_J_SCR_06_0
#define GPIO_J_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_06_0
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x150c4)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_J_SCR_06_0
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_06_0
#define GPIO_J_INPUT_06_0                       _MK_ADDR_CONST(0x150c8)
#define GPIO_J_INPUT_06_0_SECURE                        0x0
#define GPIO_J_INPUT_06_0_SCR                   GPIO_J_SCR_06_0
#define GPIO_J_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_06_0
#define GPIO_J_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x150cc)
#define GPIO_J_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_06_0_SCR                  GPIO_J_SCR_06_0
#define GPIO_J_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_06_0
#define GPIO_J_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x150d0)
#define GPIO_J_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_06_0_SCR                    GPIO_J_SCR_06_0
#define GPIO_J_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_06_0
#define GPIO_J_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x150d4)
#define GPIO_J_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_06_0_SCR                         GPIO_J_SCR_06_0
#define GPIO_J_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86232 [0x150d8]

// Reserved address 86236 [0x150dc]

// Register GPIO_J_ENABLE_CONFIG_07_0
#define GPIO_J_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x150e0)
#define GPIO_J_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_07_0_SCR                   GPIO_J_SCR_07_0
#define GPIO_J_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_07_0
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x150e4)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_J_SCR_07_0
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_INPUT_07_0
#define GPIO_J_INPUT_07_0                       _MK_ADDR_CONST(0x150e8)
#define GPIO_J_INPUT_07_0_SECURE                        0x0
#define GPIO_J_INPUT_07_0_SCR                   GPIO_J_SCR_07_0
#define GPIO_J_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_J_OUTPUT_CONTROL_07_0
#define GPIO_J_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x150ec)
#define GPIO_J_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_07_0_SCR                  GPIO_J_SCR_07_0
#define GPIO_J_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_07_0
#define GPIO_J_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x150f0)
#define GPIO_J_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_07_0_SCR                    GPIO_J_SCR_07_0
#define GPIO_J_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_CLEAR_07_0
#define GPIO_J_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x150f4)
#define GPIO_J_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_07_0_SCR                         GPIO_J_SCR_07_0
#define GPIO_J_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86264 [0x150f8]

// Reserved address 86268 [0x150fc]

// Register GPIO_J_INTERRUPT_STATUS_G0_0
#define GPIO_J_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x15100)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G1_0
#define GPIO_J_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x15104)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G2_0
#define GPIO_J_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x15108)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G3_0
#define GPIO_J_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1510c)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G4_0
#define GPIO_J_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x15110)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G5_0
#define GPIO_J_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x15114)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G6_0
#define GPIO_J_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x15118)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_J_INTERRUPT_STATUS_G7_0
#define GPIO_J_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1511c)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 86304 [0x15120]

// Reserved address 86308 [0x15124]

// Reserved address 86312 [0x15128]

// Reserved address 86316 [0x1512c]

// Reserved address 86320 [0x15130]

// Reserved address 86324 [0x15134]

// Reserved address 86328 [0x15138]

// Reserved address 86332 [0x1513c]

// Reserved address 86336 [0x15140]

// Reserved address 86340 [0x15144]

// Reserved address 86344 [0x15148]

// Reserved address 86348 [0x1514c]

// Reserved address 86352 [0x15150]

// Reserved address 86356 [0x15154]

// Reserved address 86360 [0x15158]

// Reserved address 86364 [0x1515c]

// Reserved address 86368 [0x15160]

// Reserved address 86372 [0x15164]

// Reserved address 86376 [0x15168]

// Reserved address 86380 [0x1516c]

// Reserved address 86384 [0x15170]

// Reserved address 86388 [0x15174]

// Reserved address 86392 [0x15178]

// Reserved address 86396 [0x1517c]

// Reserved address 86400 [0x15180]

// Reserved address 86404 [0x15184]

// Reserved address 86408 [0x15188]

// Reserved address 86412 [0x1518c]

// Reserved address 86416 [0x15190]

// Reserved address 86420 [0x15194]

// Reserved address 86424 [0x15198]

// Reserved address 86428 [0x1519c]

// Reserved address 86432 [0x151a0]

// Reserved address 86436 [0x151a4]

// Reserved address 86440 [0x151a8]

// Reserved address 86444 [0x151ac]

// Reserved address 86448 [0x151b0]

// Reserved address 86452 [0x151b4]

// Reserved address 86456 [0x151b8]

// Reserved address 86460 [0x151bc]

// Reserved address 86464 [0x151c0]

// Reserved address 86468 [0x151c4]

// Reserved address 86472 [0x151c8]

// Reserved address 86476 [0x151cc]

// Reserved address 86480 [0x151d0]

// Reserved address 86484 [0x151d4]

// Reserved address 86488 [0x151d8]

// Reserved address 86492 [0x151dc]

// Reserved address 86496 [0x151e0]

// Reserved address 86500 [0x151e4]

// Reserved address 86504 [0x151e8]

// Reserved address 86508 [0x151ec]

// Reserved address 86512 [0x151f0]

// Reserved address 86516 [0x151f4]

// Reserved address 86520 [0x151f8]

// Reserved address 86524 [0x151fc]

// Register GPIO_K_ENABLE_CONFIG_00_0
#define GPIO_K_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x15200)
#define GPIO_K_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x15204)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_K_SCR_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_K_INPUT_00_0
#define GPIO_K_INPUT_00_0                       _MK_ADDR_CONST(0x15208)
#define GPIO_K_INPUT_00_0_SECURE                        0x0
#define GPIO_K_INPUT_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_K_OUTPUT_CONTROL_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1520c)
#define GPIO_K_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_SCR                  GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_00_0
#define GPIO_K_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x15210)
#define GPIO_K_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_00_0_SCR                    GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_CLEAR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x15214)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_SCR                         GPIO_K_SCR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 86552 [0x15218]

// Reserved address 86556 [0x1521c]

// Reserved address 86560 [0x15220]

// Reserved address 86564 [0x15224]

// Reserved address 86568 [0x15228]

// Reserved address 86572 [0x1522c]

// Reserved address 86576 [0x15230]

// Reserved address 86580 [0x15234]

// Reserved address 86584 [0x15238]

// Reserved address 86588 [0x1523c]

// Reserved address 86592 [0x15240]

// Reserved address 86596 [0x15244]

// Reserved address 86600 [0x15248]

// Reserved address 86604 [0x1524c]

// Reserved address 86608 [0x15250]

// Reserved address 86612 [0x15254]

// Reserved address 86616 [0x15258]

// Reserved address 86620 [0x1525c]

// Reserved address 86624 [0x15260]

// Reserved address 86628 [0x15264]

// Reserved address 86632 [0x15268]

// Reserved address 86636 [0x1526c]

// Reserved address 86640 [0x15270]

// Reserved address 86644 [0x15274]

// Reserved address 86648 [0x15278]

// Reserved address 86652 [0x1527c]

// Reserved address 86656 [0x15280]

// Reserved address 86660 [0x15284]

// Reserved address 86664 [0x15288]

// Reserved address 86668 [0x1528c]

// Reserved address 86672 [0x15290]

// Reserved address 86676 [0x15294]

// Reserved address 86680 [0x15298]

// Reserved address 86684 [0x1529c]

// Reserved address 86688 [0x152a0]

// Reserved address 86692 [0x152a4]

// Reserved address 86696 [0x152a8]

// Reserved address 86700 [0x152ac]

// Reserved address 86704 [0x152b0]

// Reserved address 86708 [0x152b4]

// Reserved address 86712 [0x152b8]

// Reserved address 86716 [0x152bc]

// Reserved address 86720 [0x152c0]

// Reserved address 86724 [0x152c4]

// Reserved address 86728 [0x152c8]

// Reserved address 86732 [0x152cc]

// Reserved address 86736 [0x152d0]

// Reserved address 86740 [0x152d4]

// Reserved address 86744 [0x152d8]

// Reserved address 86748 [0x152dc]

// Reserved address 86752 [0x152e0]

// Reserved address 86756 [0x152e4]

// Reserved address 86760 [0x152e8]

// Reserved address 86764 [0x152ec]

// Reserved address 86768 [0x152f0]

// Reserved address 86772 [0x152f4]

// Reserved address 86776 [0x152f8]

// Reserved address 86780 [0x152fc]

// Register GPIO_K_INTERRUPT_STATUS_G0_0
#define GPIO_K_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x15300)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G1_0
#define GPIO_K_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x15304)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G2_0
#define GPIO_K_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x15308)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G3_0
#define GPIO_K_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1530c)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G4_0
#define GPIO_K_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x15310)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G5_0
#define GPIO_K_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x15314)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G6_0
#define GPIO_K_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x15318)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_K_INTERRUPT_STATUS_G7_0
#define GPIO_K_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1531c)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 86816 [0x15320]

// Reserved address 86820 [0x15324]

// Reserved address 86824 [0x15328]

// Reserved address 86828 [0x1532c]

// Reserved address 86832 [0x15330]

// Reserved address 86836 [0x15334]

// Reserved address 86840 [0x15338]

// Reserved address 86844 [0x1533c]

// Reserved address 86848 [0x15340]

// Reserved address 86852 [0x15344]

// Reserved address 86856 [0x15348]

// Reserved address 86860 [0x1534c]

// Reserved address 86864 [0x15350]

// Reserved address 86868 [0x15354]

// Reserved address 86872 [0x15358]

// Reserved address 86876 [0x1535c]

// Reserved address 86880 [0x15360]

// Reserved address 86884 [0x15364]

// Reserved address 86888 [0x15368]

// Reserved address 86892 [0x1536c]

// Reserved address 86896 [0x15370]

// Reserved address 86900 [0x15374]

// Reserved address 86904 [0x15378]

// Reserved address 86908 [0x1537c]

// Reserved address 86912 [0x15380]

// Reserved address 86916 [0x15384]

// Reserved address 86920 [0x15388]

// Reserved address 86924 [0x1538c]

// Reserved address 86928 [0x15390]

// Reserved address 86932 [0x15394]

// Reserved address 86936 [0x15398]

// Reserved address 86940 [0x1539c]

// Reserved address 86944 [0x153a0]

// Reserved address 86948 [0x153a4]

// Reserved address 86952 [0x153a8]

// Reserved address 86956 [0x153ac]

// Reserved address 86960 [0x153b0]

// Reserved address 86964 [0x153b4]

// Reserved address 86968 [0x153b8]

// Reserved address 86972 [0x153bc]

// Reserved address 86976 [0x153c0]

// Reserved address 86980 [0x153c4]

// Reserved address 86984 [0x153c8]

// Reserved address 86988 [0x153cc]

// Reserved address 86992 [0x153d0]

// Reserved address 86996 [0x153d4]

// Reserved address 87000 [0x153d8]

// Reserved address 87004 [0x153dc]

// Reserved address 87008 [0x153e0]

// Reserved address 87012 [0x153e4]

// Reserved address 87016 [0x153e8]

// Reserved address 87020 [0x153ec]

// Reserved address 87024 [0x153f0]

// Reserved address 87028 [0x153f4]

// Reserved address 87032 [0x153f8]

// Reserved address 87036 [0x153fc]

// Register GPIO_CC_ENABLE_CONFIG_00_0
#define GPIO_CC_ENABLE_CONFIG_00_0                      _MK_ADDR_CONST(0x15400)
#define GPIO_CC_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_SCR                  GPIO_CC_SCR_00_0
#define GPIO_CC_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_00_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0                 _MK_ADDR_CONST(0x15404)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_CC_SCR_00_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_INPUT_00_0
#define GPIO_CC_INPUT_00_0                      _MK_ADDR_CONST(0x15408)
#define GPIO_CC_INPUT_00_0_SECURE                       0x0
#define GPIO_CC_INPUT_00_0_SCR                  GPIO_CC_SCR_00_0
#define GPIO_CC_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_00_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_OUTPUT_CONTROL_00_0
#define GPIO_CC_OUTPUT_CONTROL_00_0                     _MK_ADDR_CONST(0x1540c)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_00_0_SCR                         GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_00_0
#define GPIO_CC_OUTPUT_VALUE_00_0                       _MK_ADDR_CONST(0x15410)
#define GPIO_CC_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_00_0_SCR                   GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_CLEAR_00_0
#define GPIO_CC_INTERRUPT_CLEAR_00_0                    _MK_ADDR_CONST(0x15414)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SCR                        GPIO_CC_SCR_00_0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 87064 [0x15418]

// Reserved address 87068 [0x1541c]

// Register GPIO_CC_ENABLE_CONFIG_01_0
#define GPIO_CC_ENABLE_CONFIG_01_0                      _MK_ADDR_CONST(0x15420)
#define GPIO_CC_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_SCR                  GPIO_CC_SCR_01_0
#define GPIO_CC_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_01_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0                 _MK_ADDR_CONST(0x15424)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_CC_SCR_01_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_INPUT_01_0
#define GPIO_CC_INPUT_01_0                      _MK_ADDR_CONST(0x15428)
#define GPIO_CC_INPUT_01_0_SECURE                       0x0
#define GPIO_CC_INPUT_01_0_SCR                  GPIO_CC_SCR_01_0
#define GPIO_CC_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_01_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_OUTPUT_CONTROL_01_0
#define GPIO_CC_OUTPUT_CONTROL_01_0                     _MK_ADDR_CONST(0x1542c)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_01_0_SCR                         GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_01_0
#define GPIO_CC_OUTPUT_VALUE_01_0                       _MK_ADDR_CONST(0x15430)
#define GPIO_CC_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_01_0_SCR                   GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_CLEAR_01_0
#define GPIO_CC_INTERRUPT_CLEAR_01_0                    _MK_ADDR_CONST(0x15434)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SCR                        GPIO_CC_SCR_01_0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 87096 [0x15438]

// Reserved address 87100 [0x1543c]

// Register GPIO_CC_ENABLE_CONFIG_02_0
#define GPIO_CC_ENABLE_CONFIG_02_0                      _MK_ADDR_CONST(0x15440)
#define GPIO_CC_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_SCR                  GPIO_CC_SCR_02_0
#define GPIO_CC_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_02_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0                 _MK_ADDR_CONST(0x15444)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_CC_SCR_02_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_INPUT_02_0
#define GPIO_CC_INPUT_02_0                      _MK_ADDR_CONST(0x15448)
#define GPIO_CC_INPUT_02_0_SECURE                       0x0
#define GPIO_CC_INPUT_02_0_SCR                  GPIO_CC_SCR_02_0
#define GPIO_CC_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_02_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_02_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_OUTPUT_CONTROL_02_0
#define GPIO_CC_OUTPUT_CONTROL_02_0                     _MK_ADDR_CONST(0x1544c)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_02_0_SCR                         GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_02_0
#define GPIO_CC_OUTPUT_VALUE_02_0                       _MK_ADDR_CONST(0x15450)
#define GPIO_CC_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_02_0_SCR                   GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_CLEAR_02_0
#define GPIO_CC_INTERRUPT_CLEAR_02_0                    _MK_ADDR_CONST(0x15454)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SCR                        GPIO_CC_SCR_02_0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 87128 [0x15458]

// Reserved address 87132 [0x1545c]

// Register GPIO_CC_ENABLE_CONFIG_03_0
#define GPIO_CC_ENABLE_CONFIG_03_0                      _MK_ADDR_CONST(0x15460)
#define GPIO_CC_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_SCR                  GPIO_CC_SCR_03_0
#define GPIO_CC_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_03_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0                 _MK_ADDR_CONST(0x15464)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_CC_SCR_03_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_INPUT_03_0
#define GPIO_CC_INPUT_03_0                      _MK_ADDR_CONST(0x15468)
#define GPIO_CC_INPUT_03_0_SECURE                       0x0
#define GPIO_CC_INPUT_03_0_SCR                  GPIO_CC_SCR_03_0
#define GPIO_CC_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_03_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_03_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_CC_OUTPUT_CONTROL_03_0
#define GPIO_CC_OUTPUT_CONTROL_03_0                     _MK_ADDR_CONST(0x1546c)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_03_0_SCR                         GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_03_0
#define GPIO_CC_OUTPUT_VALUE_03_0                       _MK_ADDR_CONST(0x15470)
#define GPIO_CC_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_03_0_SCR                   GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_CLEAR_03_0
#define GPIO_CC_INTERRUPT_CLEAR_03_0                    _MK_ADDR_CONST(0x15474)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SCR                        GPIO_CC_SCR_03_0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 87160 [0x15478]

// Reserved address 87164 [0x1547c]

// Reserved address 87168 [0x15480]

// Reserved address 87172 [0x15484]

// Reserved address 87176 [0x15488]

// Reserved address 87180 [0x1548c]

// Reserved address 87184 [0x15490]

// Reserved address 87188 [0x15494]

// Reserved address 87192 [0x15498]

// Reserved address 87196 [0x1549c]

// Reserved address 87200 [0x154a0]

// Reserved address 87204 [0x154a4]

// Reserved address 87208 [0x154a8]

// Reserved address 87212 [0x154ac]

// Reserved address 87216 [0x154b0]

// Reserved address 87220 [0x154b4]

// Reserved address 87224 [0x154b8]

// Reserved address 87228 [0x154bc]

// Reserved address 87232 [0x154c0]

// Reserved address 87236 [0x154c4]

// Reserved address 87240 [0x154c8]

// Reserved address 87244 [0x154cc]

// Reserved address 87248 [0x154d0]

// Reserved address 87252 [0x154d4]

// Reserved address 87256 [0x154d8]

// Reserved address 87260 [0x154dc]

// Reserved address 87264 [0x154e0]

// Reserved address 87268 [0x154e4]

// Reserved address 87272 [0x154e8]

// Reserved address 87276 [0x154ec]

// Reserved address 87280 [0x154f0]

// Reserved address 87284 [0x154f4]

// Reserved address 87288 [0x154f8]

// Reserved address 87292 [0x154fc]

// Register GPIO_CC_INTERRUPT_STATUS_G0_0
#define GPIO_CC_INTERRUPT_STATUS_G0_0                   _MK_ADDR_CONST(0x15500)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G1_0
#define GPIO_CC_INTERRUPT_STATUS_G1_0                   _MK_ADDR_CONST(0x15504)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G2_0
#define GPIO_CC_INTERRUPT_STATUS_G2_0                   _MK_ADDR_CONST(0x15508)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G3_0
#define GPIO_CC_INTERRUPT_STATUS_G3_0                   _MK_ADDR_CONST(0x1550c)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G4_0
#define GPIO_CC_INTERRUPT_STATUS_G4_0                   _MK_ADDR_CONST(0x15510)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G5_0
#define GPIO_CC_INTERRUPT_STATUS_G5_0                   _MK_ADDR_CONST(0x15514)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G6_0
#define GPIO_CC_INTERRUPT_STATUS_G6_0                   _MK_ADDR_CONST(0x15518)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register GPIO_CC_INTERRUPT_STATUS_G7_0
#define GPIO_CC_INTERRUPT_STATUS_G7_0                   _MK_ADDR_CONST(0x1551c)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0xf, GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 87328 [0x15520]

// Reserved address 87332 [0x15524]

// Reserved address 87336 [0x15528]

// Reserved address 87340 [0x1552c]

// Reserved address 87344 [0x15530]

// Reserved address 87348 [0x15534]

// Reserved address 87352 [0x15538]

// Reserved address 87356 [0x1553c]

// Reserved address 87360 [0x15540]

// Reserved address 87364 [0x15544]

// Reserved address 87368 [0x15548]

// Reserved address 87372 [0x1554c]

// Reserved address 87376 [0x15550]

// Reserved address 87380 [0x15554]

// Reserved address 87384 [0x15558]

// Reserved address 87388 [0x1555c]

// Reserved address 87392 [0x15560]

// Reserved address 87396 [0x15564]

// Reserved address 87400 [0x15568]

// Reserved address 87404 [0x1556c]

// Reserved address 87408 [0x15570]

// Reserved address 87412 [0x15574]

// Reserved address 87416 [0x15578]

// Reserved address 87420 [0x1557c]

// Reserved address 87424 [0x15580]

// Reserved address 87428 [0x15584]

// Reserved address 87432 [0x15588]

// Reserved address 87436 [0x1558c]

// Reserved address 87440 [0x15590]

// Reserved address 87444 [0x15594]

// Reserved address 87448 [0x15598]

// Reserved address 87452 [0x1559c]

// Reserved address 87456 [0x155a0]

// Reserved address 87460 [0x155a4]

// Reserved address 87464 [0x155a8]

// Reserved address 87468 [0x155ac]

// Reserved address 87472 [0x155b0]

// Reserved address 87476 [0x155b4]

// Reserved address 87480 [0x155b8]

// Reserved address 87484 [0x155bc]

// Reserved address 87488 [0x155c0]

// Reserved address 87492 [0x155c4]

// Reserved address 87496 [0x155c8]

// Reserved address 87500 [0x155cc]

// Reserved address 87504 [0x155d0]

// Reserved address 87508 [0x155d4]

// Reserved address 87512 [0x155d8]

// Reserved address 87516 [0x155dc]

// Reserved address 87520 [0x155e0]

// Reserved address 87524 [0x155e4]

// Reserved address 87528 [0x155e8]

// Reserved address 87532 [0x155ec]

// Reserved address 87536 [0x155f0]

// Reserved address 87540 [0x155f4]

// Reserved address 87544 [0x155f8]

// Reserved address 87548 [0x155fc]

// Register GPIO_M_ENABLE_CONFIG_00_0
#define GPIO_M_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x15600)
#define GPIO_M_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x15604)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_M_SCR_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_00_0
#define GPIO_M_INPUT_00_0                       _MK_ADDR_CONST(0x15608)
#define GPIO_M_INPUT_00_0_SECURE                        0x0
#define GPIO_M_INPUT_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1560c)
#define GPIO_M_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_SCR                  GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_00_0
#define GPIO_M_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x15610)
#define GPIO_M_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_00_0_SCR                    GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x15614)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_SCR                         GPIO_M_SCR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87576 [0x15618]

// Reserved address 87580 [0x1561c]

// Register GPIO_M_ENABLE_CONFIG_01_0
#define GPIO_M_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x15620)
#define GPIO_M_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x15624)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_M_SCR_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_01_0
#define GPIO_M_INPUT_01_0                       _MK_ADDR_CONST(0x15628)
#define GPIO_M_INPUT_01_0_SECURE                        0x0
#define GPIO_M_INPUT_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1562c)
#define GPIO_M_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_SCR                  GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_01_0
#define GPIO_M_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x15630)
#define GPIO_M_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_01_0_SCR                    GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x15634)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_SCR                         GPIO_M_SCR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87608 [0x15638]

// Reserved address 87612 [0x1563c]

// Register GPIO_M_ENABLE_CONFIG_02_0
#define GPIO_M_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x15640)
#define GPIO_M_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x15644)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_M_SCR_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_02_0
#define GPIO_M_INPUT_02_0                       _MK_ADDR_CONST(0x15648)
#define GPIO_M_INPUT_02_0_SECURE                        0x0
#define GPIO_M_INPUT_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1564c)
#define GPIO_M_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_SCR                  GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_02_0
#define GPIO_M_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x15650)
#define GPIO_M_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_02_0_SCR                    GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x15654)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_SCR                         GPIO_M_SCR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87640 [0x15658]

// Reserved address 87644 [0x1565c]

// Register GPIO_M_ENABLE_CONFIG_03_0
#define GPIO_M_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x15660)
#define GPIO_M_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x15664)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_M_SCR_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_03_0
#define GPIO_M_INPUT_03_0                       _MK_ADDR_CONST(0x15668)
#define GPIO_M_INPUT_03_0_SECURE                        0x0
#define GPIO_M_INPUT_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1566c)
#define GPIO_M_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_SCR                  GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_03_0
#define GPIO_M_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x15670)
#define GPIO_M_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_03_0_SCR                    GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x15674)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_SCR                         GPIO_M_SCR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87672 [0x15678]

// Reserved address 87676 [0x1567c]

// Register GPIO_M_ENABLE_CONFIG_04_0
#define GPIO_M_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x15680)
#define GPIO_M_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x15684)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_M_SCR_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_04_0
#define GPIO_M_INPUT_04_0                       _MK_ADDR_CONST(0x15688)
#define GPIO_M_INPUT_04_0_SECURE                        0x0
#define GPIO_M_INPUT_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1568c)
#define GPIO_M_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_SCR                  GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_04_0
#define GPIO_M_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x15690)
#define GPIO_M_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_04_0_SCR                    GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x15694)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_SCR                         GPIO_M_SCR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87704 [0x15698]

// Reserved address 87708 [0x1569c]

// Register GPIO_M_ENABLE_CONFIG_05_0
#define GPIO_M_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x156a0)
#define GPIO_M_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x156a4)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_M_SCR_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_INPUT_05_0
#define GPIO_M_INPUT_05_0                       _MK_ADDR_CONST(0x156a8)
#define GPIO_M_INPUT_05_0_SECURE                        0x0
#define GPIO_M_INPUT_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register GPIO_M_OUTPUT_CONTROL_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x156ac)
#define GPIO_M_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_SCR                  GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_05_0
#define GPIO_M_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x156b0)
#define GPIO_M_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_05_0_SCR                    GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_CLEAR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x156b4)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_SCR                         GPIO_M_SCR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 87736 [0x156b8]

// Reserved address 87740 [0x156bc]

// Reserved address 87744 [0x156c0]

// Reserved address 87748 [0x156c4]

// Reserved address 87752 [0x156c8]

// Reserved address 87756 [0x156cc]

// Reserved address 87760 [0x156d0]

// Reserved address 87764 [0x156d4]

// Reserved address 87768 [0x156d8]

// Reserved address 87772 [0x156dc]

// Reserved address 87776 [0x156e0]

// Reserved address 87780 [0x156e4]

// Reserved address 87784 [0x156e8]

// Reserved address 87788 [0x156ec]

// Reserved address 87792 [0x156f0]

// Reserved address 87796 [0x156f4]

// Reserved address 87800 [0x156f8]

// Reserved address 87804 [0x156fc]

// Register GPIO_M_INTERRUPT_STATUS_G0_0
#define GPIO_M_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x15700)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G1_0
#define GPIO_M_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x15704)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G2_0
#define GPIO_M_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x15708)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G3_0
#define GPIO_M_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1570c)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G4_0
#define GPIO_M_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x15710)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G5_0
#define GPIO_M_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x15714)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G6_0
#define GPIO_M_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x15718)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register GPIO_M_INTERRUPT_STATUS_G7_0
#define GPIO_M_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1571c)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 87840 [0x15720]

// Reserved address 87844 [0x15724]

// Reserved address 87848 [0x15728]

// Reserved address 87852 [0x1572c]

// Reserved address 87856 [0x15730]

// Reserved address 87860 [0x15734]

// Reserved address 87864 [0x15738]

// Reserved address 87868 [0x1573c]

// Reserved address 87872 [0x15740]

// Reserved address 87876 [0x15744]

// Reserved address 87880 [0x15748]

// Reserved address 87884 [0x1574c]

// Reserved address 87888 [0x15750]

// Reserved address 87892 [0x15754]

// Reserved address 87896 [0x15758]

// Reserved address 87900 [0x1575c]

// Reserved address 87904 [0x15760]

// Reserved address 87908 [0x15764]

// Reserved address 87912 [0x15768]

// Reserved address 87916 [0x1576c]

// Reserved address 87920 [0x15770]

// Reserved address 87924 [0x15774]

// Reserved address 87928 [0x15778]

// Reserved address 87932 [0x1577c]

// Reserved address 87936 [0x15780]

// Reserved address 87940 [0x15784]

// Reserved address 87944 [0x15788]

// Reserved address 87948 [0x1578c]

// Reserved address 87952 [0x15790]

// Reserved address 87956 [0x15794]

// Reserved address 87960 [0x15798]

// Reserved address 87964 [0x1579c]

// Reserved address 87968 [0x157a0]

// Reserved address 87972 [0x157a4]

// Reserved address 87976 [0x157a8]

// Reserved address 87980 [0x157ac]

// Reserved address 87984 [0x157b0]

// Reserved address 87988 [0x157b4]

// Reserved address 87992 [0x157b8]

// Reserved address 87996 [0x157bc]

// Reserved address 88000 [0x157c0]

// Reserved address 88004 [0x157c4]

// Reserved address 88008 [0x157c8]

// Reserved address 88012 [0x157cc]

// Reserved address 88016 [0x157d0]

// Reserved address 88020 [0x157d4]

// Reserved address 88024 [0x157d8]

// Reserved address 88028 [0x157dc]

// Reserved address 88032 [0x157e0]

// Reserved address 88036 [0x157e4]

// Reserved address 88040 [0x157e8]

// Reserved address 88044 [0x157ec]

// Reserved address 88048 [0x157f0]

// Reserved address 88052 [0x157f4]

// Reserved address 88056 [0x157f8]

// Reserved address 88060 [0x157fc]

//
// REGISTER LIST
//
#define LIST_ARGPIO_REGS(_op_) \
_op_(GPIO_N_VM_00_0) \
_op_(GPIO_N_SCR_00_0) \
_op_(GPIO_N_VM_01_0) \
_op_(GPIO_N_SCR_01_0) \
_op_(GPIO_N_VM_02_0) \
_op_(GPIO_N_SCR_02_0) \
_op_(GPIO_N_VM_03_0) \
_op_(GPIO_N_SCR_03_0) \
_op_(GPIO_N_VM_04_0) \
_op_(GPIO_N_SCR_04_0) \
_op_(GPIO_N_VM_05_0) \
_op_(GPIO_N_SCR_05_0) \
_op_(GPIO_N_VM_06_0) \
_op_(GPIO_N_SCR_06_0) \
_op_(GPIO_O_VM_00_0) \
_op_(GPIO_O_SCR_00_0) \
_op_(GPIO_O_VM_01_0) \
_op_(GPIO_O_SCR_01_0) \
_op_(GPIO_O_VM_02_0) \
_op_(GPIO_O_SCR_02_0) \
_op_(GPIO_O_VM_03_0) \
_op_(GPIO_O_SCR_03_0) \
_op_(GPIO_Q_VM_00_0) \
_op_(GPIO_Q_SCR_00_0) \
_op_(GPIO_Q_VM_01_0) \
_op_(GPIO_Q_SCR_01_0) \
_op_(GPIO_Q_VM_02_0) \
_op_(GPIO_Q_SCR_02_0) \
_op_(GPIO_Q_VM_03_0) \
_op_(GPIO_Q_SCR_03_0) \
_op_(GPIO_Q_VM_04_0) \
_op_(GPIO_Q_SCR_04_0) \
_op_(GPIO_Q_VM_05_0) \
_op_(GPIO_Q_SCR_05_0) \
_op_(GPIO_T_VM_00_0) \
_op_(GPIO_T_SCR_00_0) \
_op_(GPIO_T_VM_01_0) \
_op_(GPIO_T_SCR_01_0) \
_op_(GPIO_T_VM_02_0) \
_op_(GPIO_T_SCR_02_0) \
_op_(GPIO_T_VM_03_0) \
_op_(GPIO_T_SCR_03_0) \
_op_(GPIO_I_VM_00_0) \
_op_(GPIO_I_SCR_00_0) \
_op_(GPIO_I_VM_01_0) \
_op_(GPIO_I_SCR_01_0) \
_op_(GPIO_I_VM_02_0) \
_op_(GPIO_I_SCR_02_0) \
_op_(GPIO_I_VM_03_0) \
_op_(GPIO_I_SCR_03_0) \
_op_(GPIO_I_VM_04_0) \
_op_(GPIO_I_SCR_04_0) \
_op_(GPIO_I_VM_05_0) \
_op_(GPIO_I_SCR_05_0) \
_op_(GPIO_I_VM_06_0) \
_op_(GPIO_I_SCR_06_0) \
_op_(GPIO_I_VM_07_0) \
_op_(GPIO_I_SCR_07_0) \
_op_(GPIO_R_VM_00_0) \
_op_(GPIO_R_SCR_00_0) \
_op_(GPIO_R_VM_01_0) \
_op_(GPIO_R_SCR_01_0) \
_op_(GPIO_R_VM_02_0) \
_op_(GPIO_R_SCR_02_0) \
_op_(GPIO_R_VM_03_0) \
_op_(GPIO_R_SCR_03_0) \
_op_(GPIO_R_VM_04_0) \
_op_(GPIO_R_SCR_04_0) \
_op_(GPIO_R_VM_05_0) \
_op_(GPIO_R_SCR_05_0) \
_op_(GPIO_CTL0_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL0_SCR_0) \
_op_(GPIO_CTL0_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL0_SPARE_0) \
_op_(GPIO_H_VM_00_0) \
_op_(GPIO_H_SCR_00_0) \
_op_(GPIO_H_VM_01_0) \
_op_(GPIO_H_SCR_01_0) \
_op_(GPIO_H_VM_02_0) \
_op_(GPIO_H_SCR_02_0) \
_op_(GPIO_H_VM_03_0) \
_op_(GPIO_H_SCR_03_0) \
_op_(GPIO_H_VM_04_0) \
_op_(GPIO_H_SCR_04_0) \
_op_(GPIO_H_VM_05_0) \
_op_(GPIO_H_SCR_05_0) \
_op_(GPIO_H_VM_06_0) \
_op_(GPIO_H_SCR_06_0) \
_op_(GPIO_L_VM_00_0) \
_op_(GPIO_L_SCR_00_0) \
_op_(GPIO_L_VM_01_0) \
_op_(GPIO_L_SCR_01_0) \
_op_(GPIO_L_VM_02_0) \
_op_(GPIO_L_SCR_02_0) \
_op_(GPIO_L_VM_03_0) \
_op_(GPIO_L_SCR_03_0) \
_op_(GPIO_L_VM_04_0) \
_op_(GPIO_L_SCR_04_0) \
_op_(GPIO_L_VM_05_0) \
_op_(GPIO_L_SCR_05_0) \
_op_(GPIO_L_VM_06_0) \
_op_(GPIO_L_SCR_06_0) \
_op_(GPIO_L_VM_07_0) \
_op_(GPIO_L_SCR_07_0) \
_op_(GPIO_X_VM_00_0) \
_op_(GPIO_X_SCR_00_0) \
_op_(GPIO_X_VM_01_0) \
_op_(GPIO_X_SCR_01_0) \
_op_(GPIO_X_VM_02_0) \
_op_(GPIO_X_SCR_02_0) \
_op_(GPIO_X_VM_03_0) \
_op_(GPIO_X_SCR_03_0) \
_op_(GPIO_X_VM_04_0) \
_op_(GPIO_X_SCR_04_0) \
_op_(GPIO_X_VM_05_0) \
_op_(GPIO_X_SCR_05_0) \
_op_(GPIO_X_VM_06_0) \
_op_(GPIO_X_SCR_06_0) \
_op_(GPIO_X_VM_07_0) \
_op_(GPIO_X_SCR_07_0) \
_op_(GPIO_Y_VM_00_0) \
_op_(GPIO_Y_SCR_00_0) \
_op_(GPIO_Y_VM_01_0) \
_op_(GPIO_Y_SCR_01_0) \
_op_(GPIO_Y_VM_02_0) \
_op_(GPIO_Y_SCR_02_0) \
_op_(GPIO_Y_VM_03_0) \
_op_(GPIO_Y_SCR_03_0) \
_op_(GPIO_Y_VM_04_0) \
_op_(GPIO_Y_SCR_04_0) \
_op_(GPIO_Y_VM_05_0) \
_op_(GPIO_Y_SCR_05_0) \
_op_(GPIO_Y_VM_06_0) \
_op_(GPIO_Y_SCR_06_0) \
_op_(GPIO_CTL1_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL1_SCR_0) \
_op_(GPIO_CTL1_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL1_SPARE_0) \
_op_(GPIO_A_VM_00_0) \
_op_(GPIO_A_SCR_00_0) \
_op_(GPIO_A_VM_01_0) \
_op_(GPIO_A_SCR_01_0) \
_op_(GPIO_A_VM_02_0) \
_op_(GPIO_A_SCR_02_0) \
_op_(GPIO_A_VM_03_0) \
_op_(GPIO_A_SCR_03_0) \
_op_(GPIO_A_VM_04_0) \
_op_(GPIO_A_SCR_04_0) \
_op_(GPIO_A_VM_05_0) \
_op_(GPIO_A_SCR_05_0) \
_op_(GPIO_A_VM_06_0) \
_op_(GPIO_A_SCR_06_0) \
_op_(GPIO_E_VM_00_0) \
_op_(GPIO_E_SCR_00_0) \
_op_(GPIO_E_VM_01_0) \
_op_(GPIO_E_SCR_01_0) \
_op_(GPIO_E_VM_02_0) \
_op_(GPIO_E_SCR_02_0) \
_op_(GPIO_E_VM_03_0) \
_op_(GPIO_E_SCR_03_0) \
_op_(GPIO_E_VM_04_0) \
_op_(GPIO_E_SCR_04_0) \
_op_(GPIO_E_VM_05_0) \
_op_(GPIO_E_SCR_05_0) \
_op_(GPIO_E_VM_06_0) \
_op_(GPIO_E_SCR_06_0) \
_op_(GPIO_E_VM_07_0) \
_op_(GPIO_E_SCR_07_0) \
_op_(GPIO_F_VM_00_0) \
_op_(GPIO_F_SCR_00_0) \
_op_(GPIO_F_VM_01_0) \
_op_(GPIO_F_SCR_01_0) \
_op_(GPIO_F_VM_02_0) \
_op_(GPIO_F_SCR_02_0) \
_op_(GPIO_F_VM_03_0) \
_op_(GPIO_F_SCR_03_0) \
_op_(GPIO_F_VM_04_0) \
_op_(GPIO_F_SCR_04_0) \
_op_(GPIO_F_VM_05_0) \
_op_(GPIO_F_SCR_05_0) \
_op_(GPIO_BB_VM_00_0) \
_op_(GPIO_BB_SCR_00_0) \
_op_(GPIO_BB_VM_01_0) \
_op_(GPIO_BB_SCR_01_0) \
_op_(GPIO_CTL2_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL2_SCR_0) \
_op_(GPIO_CTL2_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL2_SPARE_0) \
_op_(GPIO_B_VM_00_0) \
_op_(GPIO_B_SCR_00_0) \
_op_(GPIO_B_VM_01_0) \
_op_(GPIO_B_SCR_01_0) \
_op_(GPIO_B_VM_02_0) \
_op_(GPIO_B_SCR_02_0) \
_op_(GPIO_B_VM_03_0) \
_op_(GPIO_B_SCR_03_0) \
_op_(GPIO_B_VM_04_0) \
_op_(GPIO_B_SCR_04_0) \
_op_(GPIO_B_VM_05_0) \
_op_(GPIO_B_SCR_05_0) \
_op_(GPIO_B_VM_06_0) \
_op_(GPIO_B_SCR_06_0) \
_op_(GPIO_C_VM_00_0) \
_op_(GPIO_C_SCR_00_0) \
_op_(GPIO_C_VM_01_0) \
_op_(GPIO_C_SCR_01_0) \
_op_(GPIO_C_VM_02_0) \
_op_(GPIO_C_SCR_02_0) \
_op_(GPIO_C_VM_03_0) \
_op_(GPIO_C_SCR_03_0) \
_op_(GPIO_C_VM_04_0) \
_op_(GPIO_C_SCR_04_0) \
_op_(GPIO_C_VM_05_0) \
_op_(GPIO_C_SCR_05_0) \
_op_(GPIO_C_VM_06_0) \
_op_(GPIO_C_SCR_06_0) \
_op_(GPIO_D_VM_00_0) \
_op_(GPIO_D_SCR_00_0) \
_op_(GPIO_D_VM_01_0) \
_op_(GPIO_D_SCR_01_0) \
_op_(GPIO_D_VM_02_0) \
_op_(GPIO_D_SCR_02_0) \
_op_(GPIO_D_VM_03_0) \
_op_(GPIO_D_SCR_03_0) \
_op_(GPIO_D_VM_04_0) \
_op_(GPIO_D_SCR_04_0) \
_op_(GPIO_D_VM_05_0) \
_op_(GPIO_D_SCR_05_0) \
_op_(GPIO_CTL3_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL3_SCR_0) \
_op_(GPIO_CTL3_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL3_SPARE_0) \
_op_(GPIO_P_VM_00_0) \
_op_(GPIO_P_SCR_00_0) \
_op_(GPIO_P_VM_01_0) \
_op_(GPIO_P_SCR_01_0) \
_op_(GPIO_P_VM_02_0) \
_op_(GPIO_P_SCR_02_0) \
_op_(GPIO_P_VM_03_0) \
_op_(GPIO_P_SCR_03_0) \
_op_(GPIO_P_VM_04_0) \
_op_(GPIO_P_SCR_04_0) \
_op_(GPIO_P_VM_05_0) \
_op_(GPIO_P_SCR_05_0) \
_op_(GPIO_P_VM_06_0) \
_op_(GPIO_P_SCR_06_0) \
_op_(GPIO_G_VM_00_0) \
_op_(GPIO_G_SCR_00_0) \
_op_(GPIO_G_VM_01_0) \
_op_(GPIO_G_SCR_01_0) \
_op_(GPIO_G_VM_02_0) \
_op_(GPIO_G_SCR_02_0) \
_op_(GPIO_G_VM_03_0) \
_op_(GPIO_G_SCR_03_0) \
_op_(GPIO_G_VM_04_0) \
_op_(GPIO_G_SCR_04_0) \
_op_(GPIO_G_VM_05_0) \
_op_(GPIO_G_SCR_05_0) \
_op_(GPIO_CTL4_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL4_SCR_0) \
_op_(GPIO_CTL4_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL4_SPARE_0) \
_op_(GPIO_J_VM_00_0) \
_op_(GPIO_J_SCR_00_0) \
_op_(GPIO_J_VM_01_0) \
_op_(GPIO_J_SCR_01_0) \
_op_(GPIO_J_VM_02_0) \
_op_(GPIO_J_SCR_02_0) \
_op_(GPIO_J_VM_03_0) \
_op_(GPIO_J_SCR_03_0) \
_op_(GPIO_J_VM_04_0) \
_op_(GPIO_J_SCR_04_0) \
_op_(GPIO_J_VM_05_0) \
_op_(GPIO_J_SCR_05_0) \
_op_(GPIO_J_VM_06_0) \
_op_(GPIO_J_SCR_06_0) \
_op_(GPIO_J_VM_07_0) \
_op_(GPIO_J_SCR_07_0) \
_op_(GPIO_K_VM_00_0) \
_op_(GPIO_K_SCR_00_0) \
_op_(GPIO_CC_VM_00_0) \
_op_(GPIO_CC_SCR_00_0) \
_op_(GPIO_CC_VM_01_0) \
_op_(GPIO_CC_SCR_01_0) \
_op_(GPIO_CC_VM_02_0) \
_op_(GPIO_CC_SCR_02_0) \
_op_(GPIO_CC_VM_03_0) \
_op_(GPIO_CC_SCR_03_0) \
_op_(GPIO_M_VM_00_0) \
_op_(GPIO_M_SCR_00_0) \
_op_(GPIO_M_VM_01_0) \
_op_(GPIO_M_SCR_01_0) \
_op_(GPIO_M_VM_02_0) \
_op_(GPIO_M_SCR_02_0) \
_op_(GPIO_M_VM_03_0) \
_op_(GPIO_M_SCR_03_0) \
_op_(GPIO_M_VM_04_0) \
_op_(GPIO_M_SCR_04_0) \
_op_(GPIO_M_VM_05_0) \
_op_(GPIO_M_SCR_05_0) \
_op_(GPIO_CTL5_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL5_SCR_0) \
_op_(GPIO_CTL5_ICG_EN_OVERRIDE_0) \
_op_(GPIO_CTL5_SPARE_0) \
_op_(GPIO_N_ENABLE_CONFIG_00_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_N_INPUT_00_0) \
_op_(GPIO_N_OUTPUT_CONTROL_00_0) \
_op_(GPIO_N_OUTPUT_VALUE_00_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_N_ENABLE_CONFIG_01_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_N_INPUT_01_0) \
_op_(GPIO_N_OUTPUT_CONTROL_01_0) \
_op_(GPIO_N_OUTPUT_VALUE_01_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_N_ENABLE_CONFIG_02_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_N_INPUT_02_0) \
_op_(GPIO_N_OUTPUT_CONTROL_02_0) \
_op_(GPIO_N_OUTPUT_VALUE_02_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_N_ENABLE_CONFIG_03_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_N_INPUT_03_0) \
_op_(GPIO_N_OUTPUT_CONTROL_03_0) \
_op_(GPIO_N_OUTPUT_VALUE_03_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_N_ENABLE_CONFIG_04_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_N_INPUT_04_0) \
_op_(GPIO_N_OUTPUT_CONTROL_04_0) \
_op_(GPIO_N_OUTPUT_VALUE_04_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_N_ENABLE_CONFIG_05_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_N_INPUT_05_0) \
_op_(GPIO_N_OUTPUT_CONTROL_05_0) \
_op_(GPIO_N_OUTPUT_VALUE_05_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_N_ENABLE_CONFIG_06_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_N_INPUT_06_0) \
_op_(GPIO_N_OUTPUT_CONTROL_06_0) \
_op_(GPIO_N_OUTPUT_VALUE_06_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_O_ENABLE_CONFIG_00_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_O_INPUT_00_0) \
_op_(GPIO_O_OUTPUT_CONTROL_00_0) \
_op_(GPIO_O_OUTPUT_VALUE_00_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_O_ENABLE_CONFIG_01_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_O_INPUT_01_0) \
_op_(GPIO_O_OUTPUT_CONTROL_01_0) \
_op_(GPIO_O_OUTPUT_VALUE_01_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_O_ENABLE_CONFIG_02_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_O_INPUT_02_0) \
_op_(GPIO_O_OUTPUT_CONTROL_02_0) \
_op_(GPIO_O_OUTPUT_VALUE_02_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_O_ENABLE_CONFIG_03_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_O_INPUT_03_0) \
_op_(GPIO_O_OUTPUT_CONTROL_03_0) \
_op_(GPIO_O_OUTPUT_VALUE_03_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Q_ENABLE_CONFIG_00_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Q_INPUT_00_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Q_OUTPUT_VALUE_00_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Q_ENABLE_CONFIG_01_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Q_INPUT_01_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Q_OUTPUT_VALUE_01_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Q_ENABLE_CONFIG_02_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Q_INPUT_02_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Q_OUTPUT_VALUE_02_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Q_ENABLE_CONFIG_03_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Q_INPUT_03_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Q_OUTPUT_VALUE_03_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Q_ENABLE_CONFIG_04_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Q_INPUT_04_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Q_OUTPUT_VALUE_04_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Q_ENABLE_CONFIG_05_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Q_INPUT_05_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Q_OUTPUT_VALUE_05_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_T_ENABLE_CONFIG_00_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_T_INPUT_00_0) \
_op_(GPIO_T_OUTPUT_CONTROL_00_0) \
_op_(GPIO_T_OUTPUT_VALUE_00_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_T_ENABLE_CONFIG_01_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_T_INPUT_01_0) \
_op_(GPIO_T_OUTPUT_CONTROL_01_0) \
_op_(GPIO_T_OUTPUT_VALUE_01_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_T_ENABLE_CONFIG_02_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_T_INPUT_02_0) \
_op_(GPIO_T_OUTPUT_CONTROL_02_0) \
_op_(GPIO_T_OUTPUT_VALUE_02_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_T_ENABLE_CONFIG_03_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_T_INPUT_03_0) \
_op_(GPIO_T_OUTPUT_CONTROL_03_0) \
_op_(GPIO_T_OUTPUT_VALUE_03_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_I_ENABLE_CONFIG_00_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_I_INPUT_00_0) \
_op_(GPIO_I_OUTPUT_CONTROL_00_0) \
_op_(GPIO_I_OUTPUT_VALUE_00_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_I_ENABLE_CONFIG_01_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_I_INPUT_01_0) \
_op_(GPIO_I_OUTPUT_CONTROL_01_0) \
_op_(GPIO_I_OUTPUT_VALUE_01_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_I_ENABLE_CONFIG_02_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_I_INPUT_02_0) \
_op_(GPIO_I_OUTPUT_CONTROL_02_0) \
_op_(GPIO_I_OUTPUT_VALUE_02_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_I_ENABLE_CONFIG_03_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_I_INPUT_03_0) \
_op_(GPIO_I_OUTPUT_CONTROL_03_0) \
_op_(GPIO_I_OUTPUT_VALUE_03_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_I_ENABLE_CONFIG_04_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_I_INPUT_04_0) \
_op_(GPIO_I_OUTPUT_CONTROL_04_0) \
_op_(GPIO_I_OUTPUT_VALUE_04_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_I_ENABLE_CONFIG_05_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_I_INPUT_05_0) \
_op_(GPIO_I_OUTPUT_CONTROL_05_0) \
_op_(GPIO_I_OUTPUT_VALUE_05_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_I_ENABLE_CONFIG_06_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_I_INPUT_06_0) \
_op_(GPIO_I_OUTPUT_CONTROL_06_0) \
_op_(GPIO_I_OUTPUT_VALUE_06_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_I_ENABLE_CONFIG_07_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_I_INPUT_07_0) \
_op_(GPIO_I_OUTPUT_CONTROL_07_0) \
_op_(GPIO_I_OUTPUT_VALUE_07_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_R_ENABLE_CONFIG_00_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_R_INPUT_00_0) \
_op_(GPIO_R_OUTPUT_CONTROL_00_0) \
_op_(GPIO_R_OUTPUT_VALUE_00_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_R_ENABLE_CONFIG_01_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_R_INPUT_01_0) \
_op_(GPIO_R_OUTPUT_CONTROL_01_0) \
_op_(GPIO_R_OUTPUT_VALUE_01_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_R_ENABLE_CONFIG_02_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_R_INPUT_02_0) \
_op_(GPIO_R_OUTPUT_CONTROL_02_0) \
_op_(GPIO_R_OUTPUT_VALUE_02_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_R_ENABLE_CONFIG_03_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_R_INPUT_03_0) \
_op_(GPIO_R_OUTPUT_CONTROL_03_0) \
_op_(GPIO_R_OUTPUT_VALUE_03_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_R_ENABLE_CONFIG_04_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_R_INPUT_04_0) \
_op_(GPIO_R_OUTPUT_CONTROL_04_0) \
_op_(GPIO_R_OUTPUT_VALUE_04_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_R_ENABLE_CONFIG_05_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_R_INPUT_05_0) \
_op_(GPIO_R_OUTPUT_CONTROL_05_0) \
_op_(GPIO_R_OUTPUT_VALUE_05_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_H_ENABLE_CONFIG_00_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_H_INPUT_00_0) \
_op_(GPIO_H_OUTPUT_CONTROL_00_0) \
_op_(GPIO_H_OUTPUT_VALUE_00_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_H_ENABLE_CONFIG_01_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_H_INPUT_01_0) \
_op_(GPIO_H_OUTPUT_CONTROL_01_0) \
_op_(GPIO_H_OUTPUT_VALUE_01_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_H_ENABLE_CONFIG_02_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_H_INPUT_02_0) \
_op_(GPIO_H_OUTPUT_CONTROL_02_0) \
_op_(GPIO_H_OUTPUT_VALUE_02_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_H_ENABLE_CONFIG_03_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_H_INPUT_03_0) \
_op_(GPIO_H_OUTPUT_CONTROL_03_0) \
_op_(GPIO_H_OUTPUT_VALUE_03_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_H_ENABLE_CONFIG_04_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_H_INPUT_04_0) \
_op_(GPIO_H_OUTPUT_CONTROL_04_0) \
_op_(GPIO_H_OUTPUT_VALUE_04_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_H_ENABLE_CONFIG_05_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_H_INPUT_05_0) \
_op_(GPIO_H_OUTPUT_CONTROL_05_0) \
_op_(GPIO_H_OUTPUT_VALUE_05_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_H_ENABLE_CONFIG_06_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_H_INPUT_06_0) \
_op_(GPIO_H_OUTPUT_CONTROL_06_0) \
_op_(GPIO_H_OUTPUT_VALUE_06_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_L_ENABLE_CONFIG_00_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_L_INPUT_00_0) \
_op_(GPIO_L_OUTPUT_CONTROL_00_0) \
_op_(GPIO_L_OUTPUT_VALUE_00_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_L_ENABLE_CONFIG_01_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_L_INPUT_01_0) \
_op_(GPIO_L_OUTPUT_CONTROL_01_0) \
_op_(GPIO_L_OUTPUT_VALUE_01_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_L_ENABLE_CONFIG_02_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_L_INPUT_02_0) \
_op_(GPIO_L_OUTPUT_CONTROL_02_0) \
_op_(GPIO_L_OUTPUT_VALUE_02_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_L_ENABLE_CONFIG_03_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_L_INPUT_03_0) \
_op_(GPIO_L_OUTPUT_CONTROL_03_0) \
_op_(GPIO_L_OUTPUT_VALUE_03_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_L_ENABLE_CONFIG_04_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_L_INPUT_04_0) \
_op_(GPIO_L_OUTPUT_CONTROL_04_0) \
_op_(GPIO_L_OUTPUT_VALUE_04_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_L_ENABLE_CONFIG_05_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_L_INPUT_05_0) \
_op_(GPIO_L_OUTPUT_CONTROL_05_0) \
_op_(GPIO_L_OUTPUT_VALUE_05_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_L_ENABLE_CONFIG_06_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_L_INPUT_06_0) \
_op_(GPIO_L_OUTPUT_CONTROL_06_0) \
_op_(GPIO_L_OUTPUT_VALUE_06_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_L_ENABLE_CONFIG_07_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_L_INPUT_07_0) \
_op_(GPIO_L_OUTPUT_CONTROL_07_0) \
_op_(GPIO_L_OUTPUT_VALUE_07_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_X_ENABLE_CONFIG_00_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_X_INPUT_00_0) \
_op_(GPIO_X_OUTPUT_CONTROL_00_0) \
_op_(GPIO_X_OUTPUT_VALUE_00_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_X_ENABLE_CONFIG_01_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_X_INPUT_01_0) \
_op_(GPIO_X_OUTPUT_CONTROL_01_0) \
_op_(GPIO_X_OUTPUT_VALUE_01_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_X_ENABLE_CONFIG_02_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_X_INPUT_02_0) \
_op_(GPIO_X_OUTPUT_CONTROL_02_0) \
_op_(GPIO_X_OUTPUT_VALUE_02_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_X_ENABLE_CONFIG_03_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_X_INPUT_03_0) \
_op_(GPIO_X_OUTPUT_CONTROL_03_0) \
_op_(GPIO_X_OUTPUT_VALUE_03_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_X_ENABLE_CONFIG_04_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_X_INPUT_04_0) \
_op_(GPIO_X_OUTPUT_CONTROL_04_0) \
_op_(GPIO_X_OUTPUT_VALUE_04_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_X_ENABLE_CONFIG_05_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_X_INPUT_05_0) \
_op_(GPIO_X_OUTPUT_CONTROL_05_0) \
_op_(GPIO_X_OUTPUT_VALUE_05_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_X_ENABLE_CONFIG_06_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_X_INPUT_06_0) \
_op_(GPIO_X_OUTPUT_CONTROL_06_0) \
_op_(GPIO_X_OUTPUT_VALUE_06_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_X_ENABLE_CONFIG_07_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_X_INPUT_07_0) \
_op_(GPIO_X_OUTPUT_CONTROL_07_0) \
_op_(GPIO_X_OUTPUT_VALUE_07_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Y_ENABLE_CONFIG_00_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Y_INPUT_00_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Y_OUTPUT_VALUE_00_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Y_ENABLE_CONFIG_01_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Y_INPUT_01_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Y_OUTPUT_VALUE_01_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Y_ENABLE_CONFIG_02_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Y_INPUT_02_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Y_OUTPUT_VALUE_02_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Y_ENABLE_CONFIG_03_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Y_INPUT_03_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Y_OUTPUT_VALUE_03_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Y_ENABLE_CONFIG_04_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Y_INPUT_04_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Y_OUTPUT_VALUE_04_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Y_ENABLE_CONFIG_05_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Y_INPUT_05_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Y_OUTPUT_VALUE_05_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Y_ENABLE_CONFIG_06_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Y_INPUT_06_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Y_OUTPUT_VALUE_06_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_A_ENABLE_CONFIG_00_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_A_INPUT_00_0) \
_op_(GPIO_A_OUTPUT_CONTROL_00_0) \
_op_(GPIO_A_OUTPUT_VALUE_00_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_A_ENABLE_CONFIG_01_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_A_INPUT_01_0) \
_op_(GPIO_A_OUTPUT_CONTROL_01_0) \
_op_(GPIO_A_OUTPUT_VALUE_01_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_A_ENABLE_CONFIG_02_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_A_INPUT_02_0) \
_op_(GPIO_A_OUTPUT_CONTROL_02_0) \
_op_(GPIO_A_OUTPUT_VALUE_02_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_A_ENABLE_CONFIG_03_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_A_INPUT_03_0) \
_op_(GPIO_A_OUTPUT_CONTROL_03_0) \
_op_(GPIO_A_OUTPUT_VALUE_03_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_A_ENABLE_CONFIG_04_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_A_INPUT_04_0) \
_op_(GPIO_A_OUTPUT_CONTROL_04_0) \
_op_(GPIO_A_OUTPUT_VALUE_04_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_A_ENABLE_CONFIG_05_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_A_INPUT_05_0) \
_op_(GPIO_A_OUTPUT_CONTROL_05_0) \
_op_(GPIO_A_OUTPUT_VALUE_05_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_A_ENABLE_CONFIG_06_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_A_INPUT_06_0) \
_op_(GPIO_A_OUTPUT_CONTROL_06_0) \
_op_(GPIO_A_OUTPUT_VALUE_06_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_E_ENABLE_CONFIG_00_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_E_INPUT_00_0) \
_op_(GPIO_E_OUTPUT_CONTROL_00_0) \
_op_(GPIO_E_OUTPUT_VALUE_00_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_E_ENABLE_CONFIG_01_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_E_INPUT_01_0) \
_op_(GPIO_E_OUTPUT_CONTROL_01_0) \
_op_(GPIO_E_OUTPUT_VALUE_01_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_E_ENABLE_CONFIG_02_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_E_INPUT_02_0) \
_op_(GPIO_E_OUTPUT_CONTROL_02_0) \
_op_(GPIO_E_OUTPUT_VALUE_02_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_E_ENABLE_CONFIG_03_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_E_INPUT_03_0) \
_op_(GPIO_E_OUTPUT_CONTROL_03_0) \
_op_(GPIO_E_OUTPUT_VALUE_03_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_E_ENABLE_CONFIG_04_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_E_INPUT_04_0) \
_op_(GPIO_E_OUTPUT_CONTROL_04_0) \
_op_(GPIO_E_OUTPUT_VALUE_04_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_E_ENABLE_CONFIG_05_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_E_INPUT_05_0) \
_op_(GPIO_E_OUTPUT_CONTROL_05_0) \
_op_(GPIO_E_OUTPUT_VALUE_05_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_E_ENABLE_CONFIG_06_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_E_INPUT_06_0) \
_op_(GPIO_E_OUTPUT_CONTROL_06_0) \
_op_(GPIO_E_OUTPUT_VALUE_06_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_E_ENABLE_CONFIG_07_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_E_INPUT_07_0) \
_op_(GPIO_E_OUTPUT_CONTROL_07_0) \
_op_(GPIO_E_OUTPUT_VALUE_07_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_F_ENABLE_CONFIG_00_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_F_INPUT_00_0) \
_op_(GPIO_F_OUTPUT_CONTROL_00_0) \
_op_(GPIO_F_OUTPUT_VALUE_00_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_F_ENABLE_CONFIG_01_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_F_INPUT_01_0) \
_op_(GPIO_F_OUTPUT_CONTROL_01_0) \
_op_(GPIO_F_OUTPUT_VALUE_01_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_F_ENABLE_CONFIG_02_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_F_INPUT_02_0) \
_op_(GPIO_F_OUTPUT_CONTROL_02_0) \
_op_(GPIO_F_OUTPUT_VALUE_02_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_F_ENABLE_CONFIG_03_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_F_INPUT_03_0) \
_op_(GPIO_F_OUTPUT_CONTROL_03_0) \
_op_(GPIO_F_OUTPUT_VALUE_03_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_F_ENABLE_CONFIG_04_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_F_INPUT_04_0) \
_op_(GPIO_F_OUTPUT_CONTROL_04_0) \
_op_(GPIO_F_OUTPUT_VALUE_04_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_F_ENABLE_CONFIG_05_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_F_INPUT_05_0) \
_op_(GPIO_F_OUTPUT_CONTROL_05_0) \
_op_(GPIO_F_OUTPUT_VALUE_05_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_BB_ENABLE_CONFIG_00_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_BB_INPUT_00_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_00_0) \
_op_(GPIO_BB_OUTPUT_VALUE_00_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_BB_ENABLE_CONFIG_01_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_BB_INPUT_01_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_01_0) \
_op_(GPIO_BB_OUTPUT_VALUE_01_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_B_ENABLE_CONFIG_00_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_B_INPUT_00_0) \
_op_(GPIO_B_OUTPUT_CONTROL_00_0) \
_op_(GPIO_B_OUTPUT_VALUE_00_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_B_ENABLE_CONFIG_01_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_B_INPUT_01_0) \
_op_(GPIO_B_OUTPUT_CONTROL_01_0) \
_op_(GPIO_B_OUTPUT_VALUE_01_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_B_ENABLE_CONFIG_02_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_B_INPUT_02_0) \
_op_(GPIO_B_OUTPUT_CONTROL_02_0) \
_op_(GPIO_B_OUTPUT_VALUE_02_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_B_ENABLE_CONFIG_03_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_B_INPUT_03_0) \
_op_(GPIO_B_OUTPUT_CONTROL_03_0) \
_op_(GPIO_B_OUTPUT_VALUE_03_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_B_ENABLE_CONFIG_04_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_B_INPUT_04_0) \
_op_(GPIO_B_OUTPUT_CONTROL_04_0) \
_op_(GPIO_B_OUTPUT_VALUE_04_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_B_ENABLE_CONFIG_05_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_B_INPUT_05_0) \
_op_(GPIO_B_OUTPUT_CONTROL_05_0) \
_op_(GPIO_B_OUTPUT_VALUE_05_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_B_ENABLE_CONFIG_06_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_B_INPUT_06_0) \
_op_(GPIO_B_OUTPUT_CONTROL_06_0) \
_op_(GPIO_B_OUTPUT_VALUE_06_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_C_ENABLE_CONFIG_00_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_C_INPUT_00_0) \
_op_(GPIO_C_OUTPUT_CONTROL_00_0) \
_op_(GPIO_C_OUTPUT_VALUE_00_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_C_ENABLE_CONFIG_01_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_C_INPUT_01_0) \
_op_(GPIO_C_OUTPUT_CONTROL_01_0) \
_op_(GPIO_C_OUTPUT_VALUE_01_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_C_ENABLE_CONFIG_02_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_C_INPUT_02_0) \
_op_(GPIO_C_OUTPUT_CONTROL_02_0) \
_op_(GPIO_C_OUTPUT_VALUE_02_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_C_ENABLE_CONFIG_03_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_C_INPUT_03_0) \
_op_(GPIO_C_OUTPUT_CONTROL_03_0) \
_op_(GPIO_C_OUTPUT_VALUE_03_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_C_ENABLE_CONFIG_04_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_C_INPUT_04_0) \
_op_(GPIO_C_OUTPUT_CONTROL_04_0) \
_op_(GPIO_C_OUTPUT_VALUE_04_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_C_ENABLE_CONFIG_05_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_C_INPUT_05_0) \
_op_(GPIO_C_OUTPUT_CONTROL_05_0) \
_op_(GPIO_C_OUTPUT_VALUE_05_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_C_ENABLE_CONFIG_06_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_C_INPUT_06_0) \
_op_(GPIO_C_OUTPUT_CONTROL_06_0) \
_op_(GPIO_C_OUTPUT_VALUE_06_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_D_ENABLE_CONFIG_00_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_D_INPUT_00_0) \
_op_(GPIO_D_OUTPUT_CONTROL_00_0) \
_op_(GPIO_D_OUTPUT_VALUE_00_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_D_ENABLE_CONFIG_01_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_D_INPUT_01_0) \
_op_(GPIO_D_OUTPUT_CONTROL_01_0) \
_op_(GPIO_D_OUTPUT_VALUE_01_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_D_ENABLE_CONFIG_02_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_D_INPUT_02_0) \
_op_(GPIO_D_OUTPUT_CONTROL_02_0) \
_op_(GPIO_D_OUTPUT_VALUE_02_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_D_ENABLE_CONFIG_03_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_D_INPUT_03_0) \
_op_(GPIO_D_OUTPUT_CONTROL_03_0) \
_op_(GPIO_D_OUTPUT_VALUE_03_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_D_ENABLE_CONFIG_04_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_D_INPUT_04_0) \
_op_(GPIO_D_OUTPUT_CONTROL_04_0) \
_op_(GPIO_D_OUTPUT_VALUE_04_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_D_ENABLE_CONFIG_05_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_D_INPUT_05_0) \
_op_(GPIO_D_OUTPUT_CONTROL_05_0) \
_op_(GPIO_D_OUTPUT_VALUE_05_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_P_ENABLE_CONFIG_00_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_P_INPUT_00_0) \
_op_(GPIO_P_OUTPUT_CONTROL_00_0) \
_op_(GPIO_P_OUTPUT_VALUE_00_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_P_ENABLE_CONFIG_01_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_P_INPUT_01_0) \
_op_(GPIO_P_OUTPUT_CONTROL_01_0) \
_op_(GPIO_P_OUTPUT_VALUE_01_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_P_ENABLE_CONFIG_02_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_P_INPUT_02_0) \
_op_(GPIO_P_OUTPUT_CONTROL_02_0) \
_op_(GPIO_P_OUTPUT_VALUE_02_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_P_ENABLE_CONFIG_03_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_P_INPUT_03_0) \
_op_(GPIO_P_OUTPUT_CONTROL_03_0) \
_op_(GPIO_P_OUTPUT_VALUE_03_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_P_ENABLE_CONFIG_04_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_P_INPUT_04_0) \
_op_(GPIO_P_OUTPUT_CONTROL_04_0) \
_op_(GPIO_P_OUTPUT_VALUE_04_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_P_ENABLE_CONFIG_05_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_P_INPUT_05_0) \
_op_(GPIO_P_OUTPUT_CONTROL_05_0) \
_op_(GPIO_P_OUTPUT_VALUE_05_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_P_ENABLE_CONFIG_06_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_P_INPUT_06_0) \
_op_(GPIO_P_OUTPUT_CONTROL_06_0) \
_op_(GPIO_P_OUTPUT_VALUE_06_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_G_ENABLE_CONFIG_00_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_G_INPUT_00_0) \
_op_(GPIO_G_OUTPUT_CONTROL_00_0) \
_op_(GPIO_G_OUTPUT_VALUE_00_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_G_ENABLE_CONFIG_01_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_G_INPUT_01_0) \
_op_(GPIO_G_OUTPUT_CONTROL_01_0) \
_op_(GPIO_G_OUTPUT_VALUE_01_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_G_ENABLE_CONFIG_02_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_G_INPUT_02_0) \
_op_(GPIO_G_OUTPUT_CONTROL_02_0) \
_op_(GPIO_G_OUTPUT_VALUE_02_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_G_ENABLE_CONFIG_03_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_G_INPUT_03_0) \
_op_(GPIO_G_OUTPUT_CONTROL_03_0) \
_op_(GPIO_G_OUTPUT_VALUE_03_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_G_ENABLE_CONFIG_04_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_G_INPUT_04_0) \
_op_(GPIO_G_OUTPUT_CONTROL_04_0) \
_op_(GPIO_G_OUTPUT_VALUE_04_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_G_ENABLE_CONFIG_05_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_G_INPUT_05_0) \
_op_(GPIO_G_OUTPUT_CONTROL_05_0) \
_op_(GPIO_G_OUTPUT_VALUE_05_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_J_ENABLE_CONFIG_00_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_J_INPUT_00_0) \
_op_(GPIO_J_OUTPUT_CONTROL_00_0) \
_op_(GPIO_J_OUTPUT_VALUE_00_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_J_ENABLE_CONFIG_01_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_J_INPUT_01_0) \
_op_(GPIO_J_OUTPUT_CONTROL_01_0) \
_op_(GPIO_J_OUTPUT_VALUE_01_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_J_ENABLE_CONFIG_02_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_J_INPUT_02_0) \
_op_(GPIO_J_OUTPUT_CONTROL_02_0) \
_op_(GPIO_J_OUTPUT_VALUE_02_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_J_ENABLE_CONFIG_03_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_J_INPUT_03_0) \
_op_(GPIO_J_OUTPUT_CONTROL_03_0) \
_op_(GPIO_J_OUTPUT_VALUE_03_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_J_ENABLE_CONFIG_04_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_J_INPUT_04_0) \
_op_(GPIO_J_OUTPUT_CONTROL_04_0) \
_op_(GPIO_J_OUTPUT_VALUE_04_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_J_ENABLE_CONFIG_05_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_J_INPUT_05_0) \
_op_(GPIO_J_OUTPUT_CONTROL_05_0) \
_op_(GPIO_J_OUTPUT_VALUE_05_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_J_ENABLE_CONFIG_06_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_J_INPUT_06_0) \
_op_(GPIO_J_OUTPUT_CONTROL_06_0) \
_op_(GPIO_J_OUTPUT_VALUE_06_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_J_ENABLE_CONFIG_07_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_J_INPUT_07_0) \
_op_(GPIO_J_OUTPUT_CONTROL_07_0) \
_op_(GPIO_J_OUTPUT_VALUE_07_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_K_ENABLE_CONFIG_00_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_K_INPUT_00_0) \
_op_(GPIO_K_OUTPUT_CONTROL_00_0) \
_op_(GPIO_K_OUTPUT_VALUE_00_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_CC_ENABLE_CONFIG_00_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_CC_INPUT_00_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_00_0) \
_op_(GPIO_CC_OUTPUT_VALUE_00_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_CC_ENABLE_CONFIG_01_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_CC_INPUT_01_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_01_0) \
_op_(GPIO_CC_OUTPUT_VALUE_01_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_CC_ENABLE_CONFIG_02_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_CC_INPUT_02_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_02_0) \
_op_(GPIO_CC_OUTPUT_VALUE_02_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_CC_ENABLE_CONFIG_03_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_CC_INPUT_03_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_03_0) \
_op_(GPIO_CC_OUTPUT_VALUE_03_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_M_ENABLE_CONFIG_00_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_M_INPUT_00_0) \
_op_(GPIO_M_OUTPUT_CONTROL_00_0) \
_op_(GPIO_M_OUTPUT_VALUE_00_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_M_ENABLE_CONFIG_01_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_M_INPUT_01_0) \
_op_(GPIO_M_OUTPUT_CONTROL_01_0) \
_op_(GPIO_M_OUTPUT_VALUE_01_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_M_ENABLE_CONFIG_02_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_M_INPUT_02_0) \
_op_(GPIO_M_OUTPUT_CONTROL_02_0) \
_op_(GPIO_M_OUTPUT_VALUE_02_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_M_ENABLE_CONFIG_03_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_M_INPUT_03_0) \
_op_(GPIO_M_OUTPUT_CONTROL_03_0) \
_op_(GPIO_M_OUTPUT_VALUE_03_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_M_ENABLE_CONFIG_04_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_M_INPUT_04_0) \
_op_(GPIO_M_OUTPUT_CONTROL_04_0) \
_op_(GPIO_M_OUTPUT_VALUE_04_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_M_ENABLE_CONFIG_05_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_M_INPUT_05_0) \
_op_(GPIO_M_OUTPUT_CONTROL_05_0) \
_op_(GPIO_M_OUTPUT_VALUE_05_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G7_0)


//
// ADDRESS SPACES
//


//
// ARGPIO REGISTER BANKS
//


// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARGPIO_H_INC_
