//
// Copyright (c) 2016 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//  * Redistributions of source code must retain the above copyright
//    notice, this list of conditions and the following disclaimer.
//  * Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimer in the
//    documentation and/or other materials provided with the distribution.
//  * Neither the name of NVIDIA CORPORATION nor the names of its
//    contributors may be used to endorse or promote products derived
//    from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARCLK_RST_H_INC_
#define ___ARCLK_RST_H_INC_

// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0                    _MK_ADDR_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0_SWR_TOP_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0                        _MK_ADDR_CONST(0x4)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0_SET_SWR_TOP_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0                        _MK_ADDR_CONST(0x8)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0_CLR_SWR_TOP_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SHSP_0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0                       _MK_ADDR_CONST(0xc)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_0_SWR_SHSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0                   _MK_ADDR_CONST(0x10)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0_SET_SWR_SHSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0                   _MK_ADDR_CONST(0x14)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0_CLR_SWR_SHSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0                    _MK_ADDR_CONST(0x18)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0_SWR_TMR_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0                        _MK_ADDR_CONST(0x1c)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0_SET_SWR_TMR_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0                        _MK_ADDR_CONST(0x20)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0_CLR_SWR_TMR_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0                      _MK_ADDR_CONST(0x24)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_0_SWR_KFUSE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0                  _MK_ADDR_CONST(0x28)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0_SET_SWR_KFUSE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0                  _MK_ADDR_CONST(0x2c)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0_CLR_SWR_KFUSE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0                        _MK_ADDR_CONST(0x30)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_0_SWR_GPU_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0                    _MK_ADDR_CONST(0x34)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0_SET_SWR_GPU_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0                    _MK_ADDR_CONST(0x38)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0_CLR_SWR_GPU_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0                   _MK_ADDR_CONST(0x1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0_CLK_ENB_FUSE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0                       _MK_ADDR_CONST(0x1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0_SET_CLK_ENB_FUSE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0                       _MK_ADDR_CONST(0x1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0_CLR_CLK_ENB_FUSE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0                    _MK_ADDR_CONST(0x100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_PLLG_REF_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0_CLK_ENB_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0                        _MK_ADDR_CONST(0x1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_PLLG_REF_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0_SET_CLK_ENB_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0                        _MK_ADDR_CONST(0x1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_PLLG_REF_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0_CLR_CLK_ENB_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0                   _MK_ADDR_CONST(0x2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0                    _MK_ADDR_CONST(0x2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_PLLG_REF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0_BOND_OUT_GPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE0_0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0                 _MK_ADDR_CONST(0x3000)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_RANGE                  31:0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE0_0_RESERVED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE1_0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0                 _MK_ADDR_CONST(0x3004)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_RANGE                  31:0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE1_0_RESERVED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE2_0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0                 _MK_ADDR_CONST(0x3008)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_FIELD                   _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_RANGE                   31:0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE2_0_RESERVED_CLK_SOURCE_OSC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0                      _MK_ADDR_CONST(0x300c)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SHIFT)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_RANGE                    0:0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0_CAR_ISOB_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0                 _MK_ADDR_CONST(0x3010)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SCR                     0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_RESET_MASK                      _MK_MASK_CONST(0x87)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_READ_MASK                       _MK_MASK_CONST(0x87)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_WRITE_MASK                      _MK_MASK_CONST(0x87)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_RANGE                   7:7
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SOR0_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_RANGE                    2:2
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_RX_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_RANGE                    1:1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_CH2_TX_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_RANGE                  0:0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0_SATA_FPCI_CH2_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0                 _MK_ADDR_CONST(0x3014)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SCR                     0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_MASK                      _MK_MASK_CONST(0x10001000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_READ_MASK                       _MK_MASK_CONST(0x10001000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WRITE_MASK                      _MK_MASK_CONST(0x10001000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_RANGE                   28:28
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_RANGE                     12:12
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0                 _MK_ADDR_CONST(0x3018)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SCR                     0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_MASK                      _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_READ_MASK                       _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WRITE_MASK                      _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_RANGE                       27:27
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPCORELP_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0                 _MK_ADDR_CONST(0x301c)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_SCR                     0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESET_MASK                      _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_READ_MASK                       _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_WRITE_MASK                      _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_RANGE                  29:29
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0_RESERVED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0                 _MK_ADDR_CONST(0x3020)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_SCR                     0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESET_MASK                      _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_READ_MASK                       _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_WRITE_MASK                      _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_RANGE                     29:29
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0_RESERVED_OVRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0                      _MK_ADDR_CONST(0x3024)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SCR                  0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_RANGE                 1:1
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_RESERVED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_RANGE                      0:0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 12328 [0x3028]

// Reserved address 12332 [0x302c]

// Reserved address 12336 [0x3030]

// Reserved address 12340 [0x3034]

// Reserved address 12344 [0x3038]

// Reserved address 12348 [0x303c]

// Reserved address 12352 [0x3040]

// Reserved address 12356 [0x3044]

// Reserved address 12360 [0x3048]

// Reserved address 12364 [0x304c]

// Reserved address 12368 [0x3050]

// Reserved address 12372 [0x3054]

// Reserved address 12376 [0x3058]

// Reserved address 12380 [0x305c]

// Reserved address 12384 [0x3060]

// Reserved address 12388 [0x3064]

// Reserved address 12392 [0x3068]

// Reserved address 12396 [0x306c]

// Reserved address 12400 [0x3070]

// Reserved address 12404 [0x3074]

// Reserved address 12408 [0x3078]

// Reserved address 12412 [0x307c]

// Reserved address 12416 [0x3080]

// Reserved address 12420 [0x3084]

// Reserved address 12424 [0x3088]

// Reserved address 12428 [0x308c]

// Reserved address 12432 [0x3090]

// Reserved address 12436 [0x3094]

// Reserved address 12440 [0x3098]

// Reserved address 12444 [0x309c]

// Reserved address 12448 [0x30a0]

// Register CLK_RST_CONTROLLER_INTSTATUS_0
#define CLK_RST_CONTROLLER_INTSTATUS_0                  _MK_ADDR_CONST(0x30a4)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_INTSTATUS_0_SCR                      0
#define CLK_RST_CONTROLLER_INTSTATUS_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_FIELD                    _MK_FIELD_CONST(0xfffff, CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SHIFT)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_RANGE                    19:0
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_DEFAULT_MASK                     _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTSTATUS_0_CAR_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SPARE_REG0_0
#define CLK_RST_CONTROLLER_SPARE_REG0_0                 _MK_ADDR_CONST(0x30a8)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SCR                     0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SPARE_REG0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_FIELD                       _MK_FIELD_CONST(0x3ffffff, CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_RANGE                       31:6
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_RANGE                   5:5
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_DIVIDER_FSM_CYA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_RANGE                      4:4
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_VAL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_RANGE                      0:0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SPARE_REG0_0_EMC_LATENCY_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 12460 [0x30ac]

// Reserved address 12464 [0x30b0]

// Reserved address 12468 [0x30b4]

// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       _MK_ADDR_CONST(0x30b8)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    _MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     _MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    _MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       _MK_ADDR_CONST(0x30bc)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SCR                   0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    _MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     _MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    _MK_MASK_CONST(0x10f00000)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_RANGE                        23:22
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_RANGE                        21:20
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 12480 [0x30c0]

// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0                   _MK_ADDR_CONST(0x30c4)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SCR                       0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_MASK                        _MK_MASK_CONST(0x3fffe60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_READ_MASK                         _MK_MASK_CONST(0x3fffe60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffe60f)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_RANGE                     29:29
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_OBS_CLK_POLARITY_INVERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_RANGE                 28:27
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_INIT_ENUM                     GATED
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_GATED                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_DIV1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_DIV4_RISING                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_DIV4_FALLING                  _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_CPU_EARLY                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_DIV_SEL_CPU_LATE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_FIELD                  _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_RANGE                  26:14
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_CLK_T                     _MK_ENUM_CONST(128)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_DIV2_FUNC_AND_FTM_CLK                     _MK_ENUM_CONST(129)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADSP_MUXED_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(130)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AO_TSOSC2PMC_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(256)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_APB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(257)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_I2C_SLOW_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(258)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_TOUCH_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(259)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_UART_FST_MIPI_CAL_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(260)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_AON_GATED_CLAMPED_CLK                  _MK_ENUM_CONST(261)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CLK_M_SYS_AO_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(262)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CLK_S_AO_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(263)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC5_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(264)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C10_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(265)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(266)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C8_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(267)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MSS_ENCRYPT_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(268)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_OSC_FREQ_DET_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(269)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM4_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(270)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(271)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(272)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_HS_REF_CLK                 _MK_ENUM_CONST(273)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_OSC_REF_CLK                        _MK_ENUM_CONST(274)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSC_REF_CLK_T                  _MK_ENUM_CONST(275)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTC_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(276)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTG_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(277)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLAON_PTO_DIV2                        _MK_ENUM_CONST(288)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLAON_PTO_OBS                 _MK_ENUM_CONST(289)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_CPU_CLK_T                  _MK_ENUM_CONST(384)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_CPU_NIC_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(385)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AON_NIC_CLK_T                  _MK_ENUM_CONST(386)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_CORE_CLK_T                        _MK_ENUM_CONST(387)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(388)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN1_HOST_CLK_T                        _MK_ENUM_CONST(389)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_CORE_CLK_T                        _MK_ENUM_CONST(390)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(391)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CAN2_HOST_CLK_T                        _MK_ENUM_CONST(392)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AHUB_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(512)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_APE_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(513)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_APE_GATED_CLK                  _MK_ENUM_CONST(514)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC1_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(515)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC2_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(516)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC3_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(517)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DMIC4_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(518)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK1_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(519)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK1_INTF_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(520)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK2_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(521)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSPK2_INTF_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(522)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(523)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(524)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S3_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(525)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S4_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(526)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S5_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(527)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2S6_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(528)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPDIF_IN_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(529)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPDIF_OUT_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(530)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA1_PTO_DIV2                 _MK_ENUM_CONST(544)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA1_PTO_OBS                  _MK_ENUM_CONST(545)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA_PTO_DIV2                  _MK_ENUM_CONST(546)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLA_PTO_OBS                   _MK_ENUM_CONST(547)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ACTMON_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(768)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_APB_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(769)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_CPU_NIC_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(770)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_BPMP_NIC_CLK_T                 _MK_ENUM_CONST(771)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SIMON_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(772)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU0_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(773)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU1_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(774)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU2_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(775)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU3_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(776)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU4_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(777)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_CPU5_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(778)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(779)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU0_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(780)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_GPU1_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(781)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOC_THERM_PLLX_TSOSC_OUT_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(782)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSENSOR_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(783)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_BPMP_CLK                  _MK_ENUM_CONST(784)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_BPMP_FLL_UPD_CLK                  _MK_ENUM_CONST(785)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_BPMP_PRE_SKP_CLK                  _MK_ENUM_CONST(786)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLBPMP_PTO_DIV2                     _MK_ENUM_CONST(787)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLBPMP_PTO_OBS                      _MK_ENUM_CONST(788)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLBPMPCAM_PTO_DIV2                    _MK_ENUM_CONST(789)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLBPMPCAM_PTO_OBS                     _MK_ENUM_CONST(790)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_JTAG_INTFC_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(896)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ADC_SOC_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(897)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ARM_JTAG_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(898)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DIRECTDC_PIPE_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(899)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HOST1X_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(900)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C_SLOW_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(901)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_LA_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(902)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC_LEGACY_TM_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(903)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR_SAFE_CLK_NG_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(904)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UART_FST_MIPI_CAL_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(905)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC2_PTO_DIV2                 _MK_ENUM_CONST(912)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC2_PTO_OBS                  _MK_ENUM_CONST(913)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC3_PTO_DIV2                 _MK_ENUM_CONST(914)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC3_PTO_OBS                  _MK_ENUM_CONST(915)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC_PTO_DIV2                  _MK_ENUM_CONST(916)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC_PTO_OBS                   _MK_ENUM_CONST(917)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLP_PTO_DIV2                  _MK_ENUM_CONST(918)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLP_PTO_OBS                   _MK_ENUM_CONST(919)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSITE_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(1024)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DBGAPB_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(1025)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_PAD_TCLKOUT_IN                     _MK_ENUM_CONST(1026)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVDISPLAYHUB_FLL_UPD_CLK                  _MK_ENUM_CONST(1152)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVDISPLAYHUB_PRE_SKP_CLK                  _MK_ENUM_CONST(1153)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDISPLAYHUB_PTO_DIV2                     _MK_ENUM_CONST(1154)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDISPLAYHUB_PTO_OBS                      _MK_ENUM_CONST(1155)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAYHUB_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(1156)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_DISP_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(1408)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_DSC_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(1409)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P0_CLK_T_OBS_OUT                     _MK_ENUM_CONST(1410)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(1411)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P1_CLK_T_OBS_OUT                     _MK_ENUM_CONST(1536)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(1537)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDISPHUB_PTO_DIV2                    _MK_ENUM_CONST(1538)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDISPHUB_PTO_OBS                     _MK_ENUM_CONST(1539)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P2_CLK_T_OBS_OUT                     _MK_ENUM_CONST(1664)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDISPLAY_P2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(1665)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_DLL_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(1792)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(1793)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMC_LATENCY_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(1794)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MC_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(1795)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_DLL_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(1920)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(1921)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EMCSB_LATENCY_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(1922)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCSB_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(1923)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_1_GATED_CLK                    _MK_ENUM_CONST(2048)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DTV_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(2049)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH1_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(2050)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH2_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(2051)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH3_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(2052)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EXTPERIPH4_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(2053)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL0_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(2054)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL1_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(2055)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C3_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2056)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C7_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2057)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C9_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2058)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM6_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2059)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM7_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2060)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM8_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2061)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI_2X_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(2062)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_QSPI_CLK_T                     _MK_ENUM_CONST(2063)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2064)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI3_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2065)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SPI4_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2066)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TACH_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2067)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTA_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(2068)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTB_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(2069)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTE_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(2070)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AUD_MCLK_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(2176)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL2_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(2177)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL5_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(2178)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_TX_LS_3XBIT_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(2179)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_TX_SYMB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(2180)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_TXCLKREF_DIV2                      _MK_ENUM_CONST(2181)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_TXCLKREF_SWITCH_FTM_CLK_OUT_GRP0_PTO_GATED                 _MK_ENUM_CONST(2182)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_TXCLKREF_SWITCH_FTM_CLK_OUT_GRP1_PTO_GATED                 _MK_ENUM_CONST(2183)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_TXCLKREF_SWITCH_FTM_CLK_OUT_GRP2_PTO_GATED                 _MK_ENUM_CONST(2184)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_USB_PAD_PLL0_TXCLKREF_FOR_RX_FTM_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2185)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_USB_PAD_PLL0_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(2186)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PEX_USB_PAD_PLL1_TXCLKREF_FOR_RX_FTM_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2187)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM5_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2188)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_L0_TXCLKREF_FOR_RX_FTM_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(2189)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_L0_TXCLKREF_FTM_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(2190)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC2_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(2191)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSB_PTO_DIV2                        _MK_ENUM_CONST(2944)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSB_PTO_OBS                 _MK_ENUM_CONST(2945)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSBB_PTO_DIV2                       _MK_ENUM_CONST(2946)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMSBB_PTO_OBS                        _MK_ENUM_CONST(2947)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLM_PTO_DIV2                  _MK_ENUM_CONST(3200)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLM_PTO_OBS                   _MK_ENUM_CONST(3201)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMB_PTO_DIV2                 _MK_ENUM_CONST(3202)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLMB_PTO_OBS                  _MK_ENUM_CONST(3203)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL3_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(3328)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3329)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC1_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(3330)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC4_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(3331)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC4_SHAPER_OBS_CLK                  _MK_ENUM_CONST(3332)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTD_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(3333)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC4_PTO_DIV2                 _MK_ENUM_CONST(3336)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLC4_PTO_OBS                  _MK_ENUM_CONST(3337)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_GPIO_CTL4_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(3456)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C4_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3457)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C5_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3458)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C6_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3459)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3460)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM2_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3461)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PWM3_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(3462)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SDMMC3_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(3463)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UARTF_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(3464)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_ISP_FLL_UPD_CLK                   _MK_ENUM_CONST(3712)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_ISP_PRE_SKP_CLK                   _MK_ENUM_CONST(3713)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLISP_PTO_DIV2                      _MK_ENUM_CONST(3714)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLISP_PTO_OBS                       _MK_ENUM_CONST(3715)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ISP_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(3716)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ISP_GATED_CLK                  _MK_ENUM_CONST(3717)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUB_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(4352)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CCPLEX2SOC_CLKS_OP_BCLK_OBS_CPUCLK                     _MK_ENUM_CONST(4480)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CCPLEX2SOC_CLKS_OP_BCLK_OBS_DFLL_DIV12_CLK                     _MK_ENUM_CONST(4481)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CCPLEX2SOC_CLKS_OP_BCLK_OBS_DFLL_DIV2_CLK                      _MK_ENUM_CONST(4482)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CCPLEX2SOC_CLKS_OP_BCLK_OBS_DIV2_CPUCLK                        _MK_ENUM_CONST(4483)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CPU_DIV2_FUNC_AND_FTM_CLK_DRV_CPU                      _MK_ENUM_CONST(4484)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CPU_FUNC_AND_FTM_CLK_DRV_CPU                   _MK_ENUM_CONST(4485)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_FCPU_DFLL_FEEDBACK_CLK_DIV2                    _MK_ENUM_CONST(4486)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_FCPU_DVFS_DIV12_CPU_CLK_DRV_CPU                        _MK_ENUM_CONST(4487)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLX_PTO_DIV2                  _MK_ENUM_CONST(4488)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLX_PTO_OBS                   _MK_ENUM_CONST(4489)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CCPLEX_GATED_CLK                       _MK_ENUM_CONST(4496)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DVFS_REF_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(4497)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUBB_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(4498)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_GPU_GATED_CLK                  _MK_ENUM_CONST(4608)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MCHUBBB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(4609)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_2_GATED_CLK                    _MK_ENUM_CONST(4736)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_4_GATED_CLK                    _MK_ENUM_CONST(4737)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_5_GATED_CLK                    _MK_ENUM_CONST(4738)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_CENTRAL_GATED_CLK                      _MK_ENUM_CONST(4739)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(4740)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_AXICBB_FLL_UPD_CLK                        _MK_ENUM_CONST(4744)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_AXICBB_PRE_SKP_CLK                        _MK_ENUM_CONST(4745)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLAXICBB_PTO_DIV2                   _MK_ENUM_CONST(4746)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLAXICBB_PTO_OBS                    _MK_ENUM_CONST(4747)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVDEC_FLL_UPD_CLK                 _MK_ENUM_CONST(4864)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVDEC_PRE_SKP_CLK                 _MK_ENUM_CONST(4865)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDEC_PTO_DIV2                    _MK_ENUM_CONST(4866)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVDEC_PTO_OBS                     _MK_ENUM_CONST(4867)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDEC_CLK_T                    _MK_ENUM_CONST(4868)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVDEC_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(4869)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVENC_FLL_UPD_CLK                 _MK_ENUM_CONST(5376)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVENC_PRE_SKP_CLK                 _MK_ENUM_CONST(5377)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVENC_PTO_DIV2                    _MK_ENUM_CONST(5378)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVENC_PTO_OBS                     _MK_ENUM_CONST(5379)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC_CLK_T                    _MK_ENUM_CONST(5380)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVENC_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(5381)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVJPG_FLL_UPD_CLK                 _MK_ENUM_CONST(6016)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_NVJPG_PRE_SKP_CLK                 _MK_ENUM_CONST(6017)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVJPG_PTO_DIV2                    _MK_ENUM_CONST(6018)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLNVJPG_PTO_OBS                     _MK_ENUM_CONST(6019)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVJPG_CLK_T                    _MK_ENUM_CONST(6020)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVJPG_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6021)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI_CBB_PCIE_GATED_CLK                 _MK_ENUM_CONST(6144)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_IPFS_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6145)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLE_PTO_DIV2                  _MK_ENUM_CONST(6272)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLE_PTO_OBS                   _MK_ENUM_CONST(6273)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLREFE_PTO_DIV2                       _MK_ENUM_CONST(6274)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLREFE_PTO_OBS                        _MK_ENUM_CONST(6275)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6276)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SATA_OOB_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(6277)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_SCE_CLK                   _MK_ENUM_CONST(6400)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_SCE_FLL_UPD_CLK                   _MK_ENUM_CONST(6401)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_SCE_PRE_SKP_CLK                   _MK_ENUM_CONST(6402)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSCE_PTO_DIV2                      _MK_ENUM_CONST(6403)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSCE_PTO_OBS                       _MK_ENUM_CONST(6404)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SCE_APB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6408)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SCE_CPU_NIC_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(6409)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SCE_NIC_CLK_T                  _MK_ENUM_CONST(6410)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_SE_FLL_UPD_CLK                    _MK_ENUM_CONST(6528)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_SE_PRE_SKP_CLK                    _MK_ENUM_CONST(6529)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_TSEC_FLL_UPD_CLK                  _MK_ENUM_CONST(6530)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_TSEC_PRE_SKP_CLK                  _MK_ENUM_CONST(6531)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_TSECB_FLL_UPD_CLK                 _MK_ENUM_CONST(6532)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_TSECB_PRE_SKP_CLK                 _MK_ENUM_CONST(6533)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSE_PTO_DIV2                       _MK_ENUM_CONST(6534)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLSE_PTO_OBS                        _MK_ENUM_CONST(6535)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSEC_PTO_DIV2                     _MK_ENUM_CONST(6536)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSEC_PTO_OBS                      _MK_ENUM_CONST(6537)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSECB_PTO_DIV2                    _MK_ENUM_CONST(6538)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLTSECB_PTO_OBS                     _MK_ENUM_CONST(6539)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_AXI2APB_3_GATED_CLK                    _MK_ENUM_CONST(6544)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_ENTROPY_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6545)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SE_CLK_T                       _MK_ENUM_CONST(6546)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SE_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(6547)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSEC_CLK_T                     _MK_ENUM_CONST(6548)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSEC_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6549)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSECB_CLK_T                    _MK_ENUM_CONST(6550)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_TSECB_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6551)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIA_IOBIST_RX_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(6656)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIA_LP_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6657)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIA_SLOWCLKP_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6658)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIB_IOBIST_RX_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(6659)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIB_LP_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6660)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIB_SLOWCLKP_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6661)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIC_IOBIST_RX_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(6662)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIC_LP_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6663)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSIC_SLOWCLKP_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6664)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSID_IOBIST_RX_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(6665)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSID_LP_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6666)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DSID_SLOWCLKP_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6667)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA2CODEC_2X_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6668)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA2CODEC_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(6669)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_HDA_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(6670)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_HDA2CODEC_2X_CLK_OBS_OUT                   _MK_ENUM_CONST(6671)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MAUD_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6672)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6673)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR0_REF_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(6674)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6675)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_SOR1_REF_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(6676)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD2_PTO_DIV2                 _MK_ENUM_CONST(6688)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD2_PTO_OBS                  _MK_ENUM_CONST(6689)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD3_PTO_DIV2                 _MK_ENUM_CONST(6690)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD3_PTO_OBS                  _MK_ENUM_CONST(6691)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDP_PTO_DIV2                 _MK_ENUM_CONST(6692)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLDP_PTO_OBS                  _MK_ENUM_CONST(6693)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_AXI_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(6784)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_PTP_REF_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6785)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_RX_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6786)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_EQOS_TX_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6787)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_CORE_PLL_FIXED_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(6788)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_IOBIST_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(6789)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_RX_LS_BIT_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(6790)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_L0_RX_SYMB_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6791)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_RX_PWM_BIT_CLK_FOR_FTM_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(6792)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_MPHY_TX_1MHZ_REF_FUNC_AND_FTM_CLK_OUT                  _MK_ENUM_CONST(6793)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UFSDEV_REF_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(6794)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UFSHC_CG_SYS_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6795)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSI_PADOUT_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(6912)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEA0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6913)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEA1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6914)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEB0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6915)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIAB_LANEB1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6916)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEA0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6917)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEA1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6918)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEB0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6919)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSICD_LANEB1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6920)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEA0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6921)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEA1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6922)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEB0_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6923)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_CSIEF_LANEB1_FUNC_AND_FTM_CLK_OUT                      _MK_ENUM_CONST(6924)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C12_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6925)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C13_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6926)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_I2C14_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6927)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVCSI_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(6928)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NVCSILP_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(6929)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_CLK_T                       _MK_ENUM_CONST(6930)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_FUNC_AND_FTM_CLK_OUT                        _MK_ENUM_CONST(6931)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VI_I2C_FUNC_AND_FTM_CLK_OUT                    _MK_ENUM_CONST(6932)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_VI_FLL_UPD_CLK                    _MK_ENUM_CONST(6944)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_VI_PRE_SKP_CLK                    _MK_ENUM_CONST(6945)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVI_PTO_DIV2                       _MK_ENUM_CONST(6946)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVI_PTO_OBS                        _MK_ENUM_CONST(6947)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD_PTO_DIV2                  _MK_ENUM_CONST(6948)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLD_PTO_OBS                   _MK_ENUM_CONST(6949)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLNVCSI_PTO_DIV2                      _MK_ENUM_CONST(6950)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_PLLNVCSI_PTO_OBS                       _MK_ENUM_CONST(6951)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_VIC_FLL_UPD_CLK                   _MK_ENUM_CONST(7040)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_DFLL_VIC_PRE_SKP_CLK                   _MK_ENUM_CONST(7041)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVIC_PTO_DIV2                      _MK_ENUM_CONST(7042)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_NAFLLVIC_PTO_OBS                       _MK_ENUM_CONST(7043)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VIC_CLK_T                      _MK_ENUM_CONST(7044)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_VIC_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(7045)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_0                        _MK_ENUM_CONST(7552)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_1                        _MK_ENUM_CONST(7553)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_2                        _MK_ENUM_CONST(7554)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_3                        _MK_ENUM_CONST(7555)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_4                        _MK_ENUM_CONST(7556)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIPLLDBGCLK_5                        _MK_ENUM_CONST(7557)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_USB2_HSIC_TRK_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(7560)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_UTMIP_PLL_PAD_MACRO_OBS_VCOCLK                 _MK_ENUM_CONST(7561)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CORE_DEV_FUNC_AND_FTM_CLK_OUT                     _MK_ENUM_CONST(7562)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CORE_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(7563)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_FALCON_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(7564)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_XUSB_HS_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(7808)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_INT_XUSB_SS_FUNC_AND_FTM_CLK_OUT                       _MK_ENUM_CONST(7809)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_120M_CLK_T_OBS_OUT                        _MK_ENUM_CONST(7810)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_CLK480M_HSIC_FUNC_AND_FTM_CLK_OUT                 _MK_ENUM_CONST(7811)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_ANALOG_PAD_AND_PTO_SRC_SEL_XUSB_FS_FUNC_AND_FTM_CLK_OUT                   _MK_ENUM_CONST(7812)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_RANGE                      13:13
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CLK_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT                 _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_RANGE                 10:10
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_RANGE                  9:9
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_RANGE                 3:0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0                 _MK_ADDR_CONST(0x30c8)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SCR                     0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x80ffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x80ffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_RANGE                  31:31
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_RANGE                       23:0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_INTMASK_0
#define CLK_RST_CONTROLLER_INTMASK_0                    _MK_ADDR_CONST(0x30cc)
#define CLK_RST_CONTROLLER_INTMASK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_INTMASK_0_SCR                        0
#define CLK_RST_CONTROLLER_INTMASK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_INTMASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_FIELD                  _MK_FIELD_CONST(0xfffff, CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SHIFT)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_RANGE                  19:0
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_INTMASK_0_CAR_INTMASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 12496 [0x30d0]

// Register CLK_RST_CONTROLLER_EMC_MISC_0
#define CLK_RST_CONTROLLER_EMC_MISC_0                   _MK_ADDR_CONST(0x30d4)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_EMC_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_EMC_MISC_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_EMC_MISC_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_MISC_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_RANGE                     1:1
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_INIT_ENUM                 DIV_BY_2
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DIV_BY_1                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_MCHUB_CLK_RATIO_DIV_BY_2                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_RANGE                      0:0
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_INIT_ENUM                  SIDE_A
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_A                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_MISC_0_EMCHUB_CLK_SEL_SIDE_B                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0                   _MK_ADDR_CONST(0x30d8)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SCR                       0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_RANGE                     1:1
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_RANGE                      0:0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0_NAFLL_ADC_RDACK_OVERRIDE_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 65536 [0x10000]

// Reserved address 131072 [0x20000]

// Reserved address 196608 [0x30000]

// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0                       _MK_ADDR_CONST(0x40000)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_RESET_MASK                    _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_READ_MASK                     _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_WRITE_MASK                    _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0_SWR_PEX_USB_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0                   _MK_ADDR_CONST(0x40004)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_RESET_MASK                        _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_READ_MASK                         _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0_SET_SWR_PEX_USB_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0                   _MK_ADDR_CONST(0x40008)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_READ_MASK                         _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x3f8081)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L5_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_RANGE                 20:20
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L4_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_RANGE                 19:19
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L3_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_RANGE                 18:18
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L2_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_RANGE                 17:17
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L1_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_RANGE                 16:16
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_L0_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT                       _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_RANGE                       15:15
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL1_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT                       _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_RANGE                       7:7
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_PLL0_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0_CLR_SWR_PEX_USB_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0                       _MK_ADDR_CONST(0x4000c)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_0_SWR_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0                   _MK_ADDR_CONST(0x40010)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0_SET_SWR_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0                   _MK_ADDR_CONST(0x40014)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0_CLR_SWR_UPHY_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PCIE_0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0                       _MK_ADDR_CONST(0x40018)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_RESET_VAL                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIEXCLK_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_RANGE                     1:1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_AFI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_0_SWR_PCIE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0                   _MK_ADDR_CONST(0x4001c)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_RESET_VAL                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIEXCLK_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_RANGE                     1:1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_AFI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0_SET_SWR_PCIE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0                   _MK_ADDR_CONST(0x40020)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_RANGE                        2:2
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIEXCLK_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_RANGE                     1:1
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_AFI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0_CLR_SWR_PCIE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0                   _MK_ADDR_CONST(0x41000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_RESET_VAL                         _MK_MASK_CONST(0xf8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_RANGE                     7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX4_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX3_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX2_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_RANGE                     4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX1_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIERX0_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE2_IOBIST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_AFI_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0_CLK_ENB_PCIE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0                       _MK_ADDR_CONST(0x41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_RESET_VAL                     _MK_MASK_CONST(0xf8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_RANGE                     7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX4_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX3_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX2_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_RANGE                     4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX1_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIERX0_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE2_IOBIST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_AFI_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0_SET_CLK_ENB_PCIE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0                       _MK_ADDR_CONST(0x41008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_RESET_VAL                     _MK_MASK_CONST(0xf8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_RANGE                     7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX4_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX3_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX2_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_RANGE                     4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX1_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIERX0_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE2_IOBIST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_AFI_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0_CLR_CLK_ENB_PCIE_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0                   _MK_ADDR_CONST(0x42000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_RANGE                    7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_RANGE                    6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_RANGE                    5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_RANGE                    4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_RANGE                    3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIERX0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_RANGE                       2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE2_IOBIST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_RANGE                        1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_AFI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0_BOND_OUT_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0                       _MK_ADDR_CONST(0x43000)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_VAL                     _MK_MASK_CONST(0x5c00)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_MASK                    _MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x23010021)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x3fff41ff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_READ_MASK                     _MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WRITE_MASK                    _MK_MASK_CONST(0xfffffdff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_RANGE                        31:30
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_FIELD                        _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_RANGE                        29:24
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT                   _MK_MASK_CONST(0x23)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_RANGE                     23:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_RANGE                  15:15
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_RANGE                  14:14
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT                  _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_RANGE                  13:13
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_RANGE                     12:12
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT                       _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_RANGE                       11:11
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_RANGE                  10:10
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_RANGE                     8:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT                        _MK_MASK_CONST(0x21)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)


// Register CLK_RST_CONTROLLER_PLLE_MISC1_0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0                 _MK_ADDR_CONST(0x43004)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_RESET_VAL                       _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_RANGE                 7:5
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_TEST_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_RANGE                    4:4
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_SDM_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_RANGE                   3:3
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_RANGE                    2:2
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_DITHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SSC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC1_0_PLLE_EN_SDM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_BASE_0
#define CLK_RST_CONTROLLER_PLLE_BASE_0                  _MK_ADDR_CONST(0x43008)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_VAL                        _MK_MASK_CONST(0xe007d02)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_RANGE                 30:30
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_RANGE                     28:24
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT                   _MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_RANGE                       23:16
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_23_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT                        _MK_MASK_CONST(0x7d)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_BASE1_0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0                 _MK_ADDR_CONST(0x4300c)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_RESET_VAL                       _MK_MASK_CONST(0xa000000)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_RESET_MASK                      _MK_MASK_CONST(0x1f000000)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_READ_MASK                       _MK_MASK_CONST(0x1f000000)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_WRITE_MASK                      _MK_MASK_CONST(0x1f000000)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_RANGE                        28:24
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_DEFAULT                      _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_BASE1_0_PLLE_PDIVB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_MISC_0
#define CLK_RST_CONTROLLER_PLLE_MISC_0                  _MK_ADDR_CONST(0x43010)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x6200)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffff7fff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x4000)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffff7fff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffff67ff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_RANGE                    14:14
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_SWCTL_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_RANGE                   13:13
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_OFF                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_IDDQ_OVERRIDE_VALUE_ON                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_RANGE                      12:12
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_FREQLOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_RANGE                  11:11
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT                       _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_RANGE                   9:9
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_RANGE                   8:8
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_RANGE                   7:6
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_RANGE                  5:4
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG14V_CTRL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_RANGE                  3:2
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_VREG10V_CTRL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_BG_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_RANGE                  0:0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0                      _MK_ADDR_CONST(0x43014)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_DIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_RANGE                      15:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0_PLLE_SDM_SSC_STEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0                      _MK_ADDR_CONST(0x43018)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0_PLLE_SDM_SSC_MIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_AUX_0
#define CLK_RST_CONTROLLER_PLLE_AUX_0                   _MK_ADDR_CONST(0x4301c)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLE_AUX_0_RESET_VAL                         _MK_MASK_CONST(0x6002070)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_RESET_MASK                        _MK_MASK_CONST(0x9fffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x81000008)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x81000058)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_READ_MASK                         _MK_MASK_CONST(0x9fffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_WRITE_MASK                        _MK_MASK_CONST(0x93ffffff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SW_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_INIT_ENUM                     SKIP
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_SKIP                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SEQ_INCLUDE_INCLUDE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SEL_PLLREFE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_RANGE                      27:26
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_INIT_ENUM                  SEQ_ON
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_OFF                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_ON                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_STATE_SEQ_BUSY                   _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SHIFT                        _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_RANGE                        25:25
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_INIT_ENUM                    SEQ_ON
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SEQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_START_STATE_SEQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_RANGE                     24:24
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SEQ_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_RANGE                 23:16
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_RANGE                       15:8
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_DEFAULT                     _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_LOCK_DLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SHIFT                        _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_RANGE                        7:7
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_TEST_FAST_PT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_RANGE                       6:6
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_SS_SWCTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_RANGE                   5:5
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CONFIG_SWCTL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_ENABLE_SWCTL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SW_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_USE_LOCKDET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_RANGE                        2:2
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_INIT_ENUM                    OSC_DIV
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_REF_SRC_OSC_DIV                      _MK_ENUM_CONST(0)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML1_OEN_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX_0_PLLE_CML0_OEN_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_SATA_PLL_CFG0_0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0                      _MK_ADDR_CONST(0x43020)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SCR                  0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x6003803)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xff01fff7)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x1000004)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1000005)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xff01fff7)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xf300fff7)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_RANGE                      31:28
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SHIFT                 _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_RANGE                 27:26
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_INIT_ENUM                     SEQ_ON
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SEQ_OFF                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SEQ_ON                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_STATE_SEQ_BUSY                      _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_RANGE                   25:25
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_INIT_ENUM                       SEQ_ON
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SEQ_OFF                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_START_STATE_SEQ_ON                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_RANGE                        24:24
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RANGE                  16:16
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_SHIFT                        _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_RANGE                        15:15
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_SHIFT                       _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_RANGE                       14:14
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_RCAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_RANGE                 13:13
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_RANGE                  12:11
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_DEFAULT                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_SLEEP_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_RANGE                      10:10
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_CAL_VALID_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_RANGE                  9:9
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_RANGE                        8:8
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_REQ_PLL_CAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_SHIFT                 _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_RANGE                 7:7
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_PADPLL_PD_INPUT_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_RANGE                   6:6
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_LANE_PD_INPUT_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_RANGE                     5:5
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_RESET_INPUT_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_RANGE                      4:4
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_SEQ_IN_SWCTL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_RANGE                        2:2
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_SW_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_USE_LOCKDET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_RANGE                       1:1
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_RANGE                        0:0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG0_0_SATA_PADPLL_RESET_SWCTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_SATA_PLL_CFG1_0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0                      _MK_ADDR_CONST(0x43024)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x11400)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_RANGE                       31:24
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_RESET_DLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_RANGE                      23:16
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_RANGE                        15:8
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_DEFAULT                      _MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_PADPLL_PU_POST_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_RANGE                        7:0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SATA_PLL_CFG1_0_SATA_LANE_IDDQ2_PADPLL_IDDQ_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PCIE_PLL_CFG_0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0                       _MK_ADDR_CONST(0x43028)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x600000c)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xf00003c)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_READ_MASK                     _MK_MASK_CONST(0xf00003c)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x300003c)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SHIFT                  _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_RANGE                  27:26
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_INIT_ENUM                      SEQ_ON
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SEQ_OFF                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SEQ_ON                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_STATE_SEQ_BUSY                       _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SHIFT                    _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_RANGE                    25:25
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_INIT_ENUM                        SEQ_ON
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SEQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_START_STATE_SEQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_SHIFT                 _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_RANGE                 24:24
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_ENABLE_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_RANGE                      5:5
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_RESET_INPUT_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_RANGE                       4:4
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_SEQ_IN_SWCTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_RANGE                 3:3
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_OVERRIDE_VALUE_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_RANGE                  2:2
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PCIE_PLL_CFG_0_PCIE_XCLK_ENABLE_SWCTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0                    _MK_ADDR_CONST(0x4302c)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_SCR                        0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0x600380d)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xff01ff7f)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x1000040)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x1000045)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xff01ff7f)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xf300ff7f)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_RANGE                  31:28
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RCAL_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SHIFT                     _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_RANGE                     27:26
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_INIT_ENUM                 SEQ_ON
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SEQ_OFF                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SEQ_ON                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_STATE_SEQ_BUSY                  _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SHIFT                       _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_RANGE                       25:25
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_INIT_ENUM                   SEQ_ON
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SEQ_OFF                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_START_STATE_SEQ_ON                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_RANGE                    24:24
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RANGE                      16:16
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_RANGE                    15:15
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_RANGE                   14:14
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_RCAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_RANGE                     13:13
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_RANGE                      12:11
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_DEFAULT                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_SLEEP_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_RANGE                  10:10
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_CAL_VALID_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_RANGE                      9:9
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_RANGE                    8:8
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_REQ_PLL_CAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_RANGE                    6:6
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_SW_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_USE_LOCKDET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_RANGE                 5:5
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_RESET_INPUT_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_RANGE                  4:4
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_SEQ_IN_SWCTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_RANGE                     3:3
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_OVERRIDE_VALUE_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_RANGE                      2:2
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_CLK_ENABLE_SWCTL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_RANGE                   1:1
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_OVERRIDE_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_RANGE                    0:0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0_XUSBIO_PADPLL_RESET_SWCTL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)


// Register CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0                    _MK_ADDR_CONST(0x43030)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_SCR                        0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000014)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0xe0ffffff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_READ_MASK                  _MK_MASK_CONST(0xe0ffffff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0xe0ffffff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_RANGE                 31:31
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_MASTER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_RANGE                        30:29
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_SLEEP_LOCAL_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_RANGE                 23:16
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_RESET2_PADPLL_IDDQ_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_RANGE                 15:8
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_IDDQ2_PADPLL_RESET_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_RANGE                    7:0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_DEFAULT                  _MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0_XUSBIO_PADPLL_PU_POST_DLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLE_AUX1_0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0                  _MK_ADDR_CONST(0x43034)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_RESET_VAL                        _MK_MASK_CONST(0x105)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_INTRESET_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SHIFT)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_DEFAULT                  _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLE_AUX1_0_PLLE_ENABLE_DLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0                    _MK_ADDR_CONST(0x44000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_INIT_ENUM                     PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_PLLREFE_OUT                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0_IPFS_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0                   _MK_ADDR_CONST(0x50000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_RESET_VAL                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_AON_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_VE_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0_CLK_ENB_PLLC_OUT_ISP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0                       _MK_ADDR_CONST(0x50004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_RESET_VAL                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_AON_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_VE_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0_SET_CLK_ENB_PLLC_OUT_ISP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0                       _MK_ADDR_CONST(0x50008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_RANGE                        2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_AON_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_RANGE                 1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_VE_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0_CLR_CLK_ENB_PLLC_OUT_ISP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLC_BASE_0
#define CLK_RST_CONTROLLER_PLLC_BASE_0                  _MK_ADDR_CONST(0x5000c)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_FREQ_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0                        _MK_ADDR_CONST(0x50010)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_RESET_VAL                      _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_RESET_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_READ_MASK                      _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_PLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_DIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_2_0_PLLC_FLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0                        _MK_ADDR_CONST(0x50014)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_RESET_VAL                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_RESET_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_READ_MASK                      _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_VREG10V_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_LDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_DEFAULT                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_3_0_PLLC_PLL_LD_TOL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0                        _MK_ADDR_CONST(0x50018)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_RESET_VAL                      _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_RESET_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_READ_MASK                      _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_WRITE_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_RESET_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SW_DEFAULT                        _MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_EXT_FRU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_0_0_PLLC_LOOP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0                        _MK_ADDR_CONST(0x5001c)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_RESET_VAL                      _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_RESET_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_READ_MASK                      _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_WRITE_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_RANGE                  19:16
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_EXT_SUBINT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_1_0_PLLC_DIVN_FRAC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0                        _MK_ADDR_CONST(0x50020)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_RESET_VAL                      _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_SEL_IREF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SHIFT                       _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SHIFT                       _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SHIFT                       _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_KP_STEP_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC_MISC_4_0_PLLC_FRAC_STEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0                   _MK_ADDR_CONST(0x51000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_RANGE                       2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_AON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_RANGE                        1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_VE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0_BOND_OUT_PLLC_OUT_ISP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLM_BASE_0
#define CLK_RST_CONTROLLER_PLLM_BASE_0                  _MK_ADDR_CONST(0x60000)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe1f0ffff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_RANGE                     31:31
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASSPLL_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SHIFT                     _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_RANGE                     26:26
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_FREQ_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        _MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 393220 [0x60004]

// Register CLK_RST_CONTROLLER_PLLM_MISC1_0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0                 _MK_ADDR_CONST(0x60008)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_FIELD                        _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_RANGE                        23:0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC1_0_PLLM_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLM_MISC2_0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0                 _MK_ADDR_CONST(0x6000c)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_RESET_VAL                       _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_RESET_MASK                      _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_READ_MASK                       _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_RANGE                 17:16
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG14V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SHIFT                 _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_RANGE                 15:14
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VREG10V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_RANGE                     13:13
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_RANGE                      12:12
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_VCO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SHIFT                        _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_RANGE                        11:11
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_SYNC_MUX_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_RANGE                   10:10
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_RANGE                  9:8
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_PTS_FO                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_RANGE                 5:5
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_RANGE                    4:4
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_EN_LCKDET_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_RANGE                        3:3
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_LOCK_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_RANGE                  2:1
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KCP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_MISC2_0_PLLM_KVCO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMB_BASE_0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0                 _MK_ADDR_CONST(0x60010)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_RESET_MASK                      _MK_MASK_CONST(0x4df0ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_READ_MASK                       _MK_MASK_CONST(0x4df0ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0x41f0ffff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SHIFT                   _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_RANGE                   26:26
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_FREQ_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_DEFAULT                      _MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_BASE_0_PLLMB_DIVM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0                        _MK_ADDR_CONST(0x60014)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_RESET_VAL                      _MK_MASK_CONST(0x1000000)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_RESET_MASK                     _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_READ_MASK                      _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_LOCK_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SHIFT                       _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_RANGE                       25:25
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_RANGE                  24:24
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_EN_LCKDET_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_FIELD                      _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_RANGE                      23:0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_MISC1_0_PLLMB_SETUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLM_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0                        _MK_ADDR_CONST(0x60018)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_READ_MASK                      _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SDM_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_SSC_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_RANGE                  29:29
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_RANGE                   28:28
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_EN_DITHER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SHIFT                        _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_RANGE                        25:23
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CFG_0_PLLM_SDM_TEST_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0                      _MK_ADDR_CONST(0x6001c)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0_PLLM_SDM_SSC_MIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0                      _MK_ADDR_CONST(0x60020)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_RANGE                      31:16
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_SSC_STEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0_PLLM_SDM_DIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0                       _MK_ADDR_CONST(0x60024)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_READ_MASK                     _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SDM_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_SSC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_EN_DITHER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG_0_PLLMB_SDM_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0                     _MK_ADDR_CONST(0x60028)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0_PLLMB_SDM_SSC_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0                     _MK_ADDR_CONST(0x6002c)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_SSC_STEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0_PLLMB_SDM_DIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0                   _MK_ADDR_CONST(0x70000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_RESET_VAL                         _MK_MASK_CONST(0x6fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_RESET_MASK                        _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_READ_MASK                         _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_WRITE_MASK                        _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_DIRECTDC_PIPE_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SHIFT                    _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_CAR_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_SOR_SAFE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_UPHY_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SHIFT                    _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_AUDIO_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_RANGE                   23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_BOOT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SHIFT                        _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_DISPLAY_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_RANGE                  21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_RANGE                  20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTBB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_RANGE                 19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_RANGE                 18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCAB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_RANGE                 17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_RANGE                 16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTCBB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_RANGE                  15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_RANGE                  14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTLB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_RANGE                  11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_RANGE                  10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_GRTTB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_ISP_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_RANGE                    8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC0_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_RANGE                    7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_MC1_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_RANGE                  5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVDEC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_NVENC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_VIC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_XUSB_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0_CLK_ENB_PLLP_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0                       _MK_ADDR_CONST(0x70004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_RESET_VAL                     _MK_MASK_CONST(0x6fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_RESET_MASK                    _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_READ_MASK                     _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_DIRECTDC_PIPE_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SHIFT                    _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_CAR_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_SOR_SAFE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_UPHY_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SHIFT                    _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_AUDIO_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_RANGE                   23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_BOOT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SHIFT                        _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_DISPLAY_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_RANGE                  21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_RANGE                  20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTBB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_RANGE                 19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_RANGE                 18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCAB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_RANGE                 17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_RANGE                 16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTCBB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_RANGE                  15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_RANGE                  14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTLB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_RANGE                  11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_RANGE                  10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_GRTTB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_ISP_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_RANGE                    8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC0_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_RANGE                    7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_MC1_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_RANGE                  5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVDEC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_NVENC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_VIC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_XUSB_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0_SET_CLK_ENB_PLLP_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0                       _MK_ADDR_CONST(0x70008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x6fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_READ_MASK                     _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffcfbd)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_RANGE                       30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_DIRECTDC_PIPE_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SHIFT                    _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_RANGE                    29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_CAR_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_SOR_SAFE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_RANGE                   27:27
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_UPHY_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SHIFT                    _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_AUDIO_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_RANGE                   23:23
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_BOOT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SHIFT                        _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_RANGE                        22:22
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_DISPLAY_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_RANGE                  21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_RANGE                  20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTBB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_RANGE                 19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_RANGE                 18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCAB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_RANGE                 17:17
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBA_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_RANGE                 16:16
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTCBB_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_RANGE                  15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_RANGE                  14:14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTLB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_RANGE                  11:11
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTA_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_RANGE                  10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_GRTTB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_RANGE                    9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_ISP_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_RANGE                    8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC0_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_RANGE                    7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_MC1_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_RANGE                  5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVDEC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_NVENC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_RANGE                    3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_VIC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_XUSB_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0_CLR_CLK_ENB_PLLP_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_BASE_0
#define CLK_RST_CONTROLLER_PLLP_BASE_0                  _MK_ADDR_CONST(0x7000c)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x115408)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xf9f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        _MK_MASK_CONST(0xf9f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xf1f3fcff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        _MK_MASK_CONST(0x55)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLP_OUTA_0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0x70010)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        _MK_MASK_CONST(0xb)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       _MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        _MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       _MK_MASK_CONST(0xff0b)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_RANGE                     15:8
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_RANGE                   3:3
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_DIV_BYP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_CLKEN_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RANGE                      0:0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_INIT_ENUM                  RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_MISC_0
#define CLK_RST_CONTROLLER_PLLP_MISC_0                  _MK_ADDR_CONST(0x70014)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x40000)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc6001f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc6001f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc6000f)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FO                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_VCO                     _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_RANGE                     18:18
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_EN_LCKDET_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_RANGE                 17:17
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_RANGE                      4:4
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_FREQLOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_RANGE                  3:3
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_IDDQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_RANGE                  2:2
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KVCO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_KCP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLP_RESHIFT_0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0                       _MK_ADDR_CONST(0x70018)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_RESET_VAL                     _MK_MASK_CONST(0x53)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_RANGE                 9:2
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_DEFAULT                       _MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RATIO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_CLKEN_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RANGE                  0:0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_INIT_ENUM                      RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RESET_ENABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_RESHIFT_0_PLLP_OUT0_RSTN_RESET_DISABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_OUTC_0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0                  _MK_ADDR_CONST(0x7001c)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_RESET_VAL                        _MK_MASK_CONST(0x30000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x2080000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xff080000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_RANGE                    31:24
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_RANGE                  19:19
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_RANGE                  18:18
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_RANGE                    17:17
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_CLKEN_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_INIT_ENUM                 RESET_DISABLE
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTC_0_PLLP_OUT5_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLP_MISC1_0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0                 _MK_ADDR_CONST(0x70020)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_FIELD                        _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_RANGE                        23:0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC1_0_PLLP_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLP_MISC2_0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0                 _MK_ADDR_CONST(0x70024)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_RESET_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_READ_MASK                       _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_WRITE_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_RANGE                 14:13
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG14V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SHIFT                 _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_RANGE                 12:11
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_VREG10V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_RANGE                        10:10
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLP_MISC2_0_PLLP_BG_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0                   _MK_ADDR_CONST(0x71000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_RESET_MASK                        _MK_MASK_CONST(0x3fffcfbf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_READ_MASK                         _MK_MASK_CONST(0x3fffcfbf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffcfbf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_RANGE                   29:29
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_CAR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_RANGE                   28:28
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_SOR_SAFE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_RANGE                  27:27
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_UPHY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SHIFT                   _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_RANGE                   26:26
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_RANGE                 25:25
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_AUDIO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_RANGE                    24:24
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SHIFT                  _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_RANGE                  23:23
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_BOOT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SHIFT                       _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_RANGE                       22:22
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_DISPLAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_RANGE                 21:21
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_RANGE                 20:20
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTBB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_SHIFT                        _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_RANGE                        19:19
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_RANGE                        18:18
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_SHIFT                        _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_RANGE                        17:17
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_RANGE                        16:16
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTCBB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_SHIFT                 _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_RANGE                 15:15
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_SHIFT                 _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_RANGE                 14:14
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTLB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_SHIFT                 _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_RANGE                 11:11
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_SHIFT                 _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_RANGE                 10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_GRTTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_RANGE                   9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_ISP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_RANGE                   8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_RANGE                   7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_MC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_RANGE                 5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVDEC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_RANGE                 4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_NVENC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_RANGE                   3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_VIC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_RANGE                  2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_XUSB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_PLL_REF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0_BOND_OUT_PLLP_OUT_CPU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_BASE_0
#define CLK_RST_CONTROLLER_PLLA_BASE_0                  _MK_ADDR_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x803003)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe1f0ffff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_FREQLOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        _MK_MASK_CONST(0x30)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_OUT_0
#define CLK_RST_CONTROLLER_PLLA_OUT_0                   _MK_ADDR_CONST(0x80004)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        _MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         _MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0x4000ff03)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLA_MISC_0_0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0                        _MK_ADDR_CONST(0x80008)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_RESET_VAL                      _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_RESET_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_READ_MASK                      _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_WRITE_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_RESET_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_EXT_FRU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_0_0_PLLA_LOOP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_MISC_1_0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0                        _MK_ADDR_CONST(0x8000c)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_RESET_VAL                      _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_RESET_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_READ_MASK                      _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_WRITE_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_RANGE                  19:16
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_EXT_SUBINT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_1_0_PLLA_DIVN_FRAC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_MISC_2_0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0                        _MK_ADDR_CONST(0x80010)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_RESET_VAL                      _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_RESET_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_READ_MASK                      _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_PLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_DIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_2_0_PLLA_FLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_MISC_3_0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0                        _MK_ADDR_CONST(0x80014)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_RESET_VAL                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_RESET_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x2000)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0xffff00)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_READ_MASK                      _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_VREG10V_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_LDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_DEFAULT                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_3_0_PLLA_PLL_LD_TOL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA_MISC_4_0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0                        _MK_ADDR_CONST(0x80018)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_RESET_VAL                      _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_SEL_IREF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SHIFT                       _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SHIFT                       _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SHIFT                       _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_KP_STEP_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA_MISC_4_0_PLLA_FRAC_STEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 589824 [0x90000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0                   _MK_ADDR_CONST(0xa0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0_CLK_ENB_PLLD_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0                       _MK_ADDR_CONST(0xa0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0_SET_CLK_ENB_PLLD_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0                       _MK_ADDR_CONST(0xa0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0_CLR_CLK_ENB_PLLD_OUT_CPU_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLD_BASE_0
#define CLK_RST_CONTROLLER_PLLD_BASE_0                  _MK_ADDR_CONST(0xa000c)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x423e01)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xefffffff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_RANGE                       27:27
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_INIT_ENUM                   PLL_D
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_PLL_D                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_DSIA_CLK_SRC_PLL_D1                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_CSI_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_RANGE                 25:21
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_DEFAULT                       _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_RANGE                 20:16
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_DEFAULT                       _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVPA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        _MK_MASK_CONST(0x3e)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 655376 [0xa0010]

// Register CLK_RST_CONTROLLER_PLLD_MISC_0
#define CLK_RST_CONTROLLER_PLLD_MISC_0                  _MK_ADDR_CONST(0xa0014)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x40000)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       _MK_MASK_CONST(0x7de0003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        _MK_MASK_CONST(0x7de0003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0x7d60003)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   26:25
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FO                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_RANGE                   24:23
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KCP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SHIFT                  _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_RANGE                  22:22
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_KVCO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_RANGE                  20:20
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_IDDQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_RANGE                      19:19
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FREQLOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_RANGE                     18:18
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_EN_LCKDET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_RANGE                 17:17
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_SEL_DIVBY2A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD_MISC1_0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0                 _MK_ADDR_CONST(0xa0018)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_FIELD                        _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_RANGE                        23:0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLD_MISC1_0_PLLD_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)


// Register CLK_RST_CONTROLLER_PLLD_MISC2_0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0                 _MK_ADDR_CONST(0xa001c)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_RESET_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_READ_MASK                       _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_WRITE_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_RANGE                 14:13
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG14V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SHIFT                 _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_RANGE                 12:11
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_VREG10V_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_RANGE                        10:10
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_MISC2_0_PLLD_BG_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0                        _MK_ADDR_CONST(0xa0020)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_READ_MASK                      _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SDM_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_SSC_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_RANGE                  29:29
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_RANGE                   28:28
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_EN_DITHER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SHIFT                        _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_RANGE                        25:23
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CFG_0_PLLD_SDM_TEST_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0                      _MK_ADDR_CONST(0xa0024)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_RANGE                       31:16
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0_PLLD_SDM_SSC_MIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0                      _MK_ADDR_CONST(0xa0028)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_RANGE                      31:16
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_SSC_STEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0_PLLD_SDM_DIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0                   _MK_ADDR_CONST(0xa1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0_BOND_OUT_PLLD_OUT_CPU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 720896 [0xb0000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0                   _MK_ADDR_CONST(0xc0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0_CLK_ENB_I2S2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0                       _MK_ADDR_CONST(0xc0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0_SET_CLK_ENB_I2S2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0                       _MK_ADDR_CONST(0xc0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0_CLR_CLK_ENB_I2S2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0                   _MK_ADDR_CONST(0xc1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    _MK_ADDR_CONST(0xc2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0                        _MK_ADDR_CONST(0xc2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0                   _MK_ADDR_CONST(0xd0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0_CLK_ENB_I2S3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0                       _MK_ADDR_CONST(0xd0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0_SET_CLK_ENB_I2S3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0                       _MK_ADDR_CONST(0xd0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0_CLR_CLK_ENB_I2S3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0                   _MK_ADDR_CONST(0xd1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0_BOND_OUT_I2S3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0                    _MK_ADDR_CONST(0xd2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_RESET_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_READ_MASK                  _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_WRITE_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0_I2S3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0                        _MK_ADDR_CONST(0xd2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0                  _MK_ADDR_CONST(0xe0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_RESET_VAL                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DOUBLER_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0_CLK_ENB_SPDIF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0                      _MK_ADDR_CONST(0xe0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_RESET_VAL                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DOUBLER_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0_SET_CLK_ENB_SPDIF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0                      _MK_ADDR_CONST(0xe0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DOUBLER_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0_CLR_CLK_ENB_SPDIF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0                  _MK_ADDR_CONST(0xe1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DOUBLER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0                       _MK_ADDR_CONST(0xe2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_VAL                     _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIF_OUT_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0                        _MK_ADDR_CONST(0xe2004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_INIT_ENUM                     PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIF_IN_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0                    _MK_ADDR_CONST(0xe3000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0_CLK_SPARE_REG_SPDIF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 983040 [0xf0000]

// Reserved address 983044 [0xf0004]

// Reserved address 1048576 [0x100000]

// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0                       _MK_ADDR_CONST(0x110000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0_SWR_SPI3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0                   _MK_ADDR_CONST(0x110004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0_SET_SWR_SPI3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0                   _MK_ADDR_CONST(0x110008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0_CLR_SWR_SPI3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0                   _MK_ADDR_CONST(0x111000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0_CLK_ENB_SPI3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0                       _MK_ADDR_CONST(0x111004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0_SET_CLK_ENB_SPI3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0                       _MK_ADDR_CONST(0x111008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0_CLR_CLK_ENB_SPI3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0                   _MK_ADDR_CONST(0x112000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0_BOND_OUT_SPI3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0                    _MK_ADDR_CONST(0x113000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 1126404 [0x113004]

// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0                       _MK_ADDR_CONST(0x120000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0_SWR_I2C1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0                   _MK_ADDR_CONST(0x120004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0_SET_SWR_I2C1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0                   _MK_ADDR_CONST(0x120008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0_CLR_SWR_I2C1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0                   _MK_ADDR_CONST(0x121000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0_CLK_ENB_I2C1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0                       _MK_ADDR_CONST(0x121004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0_SET_CLK_ENB_I2C1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0                       _MK_ADDR_CONST(0x121008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0_CLR_CLK_ENB_I2C1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0                   _MK_ADDR_CONST(0x122000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    _MK_ADDR_CONST(0x123000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0                       _MK_ADDR_CONST(0x130000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_0_SWR_I2C5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0                   _MK_ADDR_CONST(0x130004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0_SET_SWR_I2C5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0                   _MK_ADDR_CONST(0x130008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0_CLR_SWR_I2C5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0                   _MK_ADDR_CONST(0x131000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0_CLK_ENB_I2C5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0                       _MK_ADDR_CONST(0x131004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0_SET_CLK_ENB_I2C5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0                       _MK_ADDR_CONST(0x131008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0_CLR_CLK_ENB_I2C5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0                   _MK_ADDR_CONST(0x132000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0_BOND_OUT_I2C5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0                    _MK_ADDR_CONST(0x133000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0_I2C5_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 1257476 [0x133004]

// Reserved address 1257480 [0x133008]

// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0                       _MK_ADDR_CONST(0x140000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0_SWR_SPI1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0                   _MK_ADDR_CONST(0x140004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0_SET_SWR_SPI1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0                   _MK_ADDR_CONST(0x140008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0_CLR_SWR_SPI1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0                   _MK_ADDR_CONST(0x141000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0_CLK_ENB_SPI1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0                       _MK_ADDR_CONST(0x141004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0_SET_CLK_ENB_SPI1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0                       _MK_ADDR_CONST(0x141008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0_CLR_CLK_ENB_SPI1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0                   _MK_ADDR_CONST(0x142000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    _MK_ADDR_CONST(0x143000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 1376256 [0x150000]

// Reserved address 1441792 [0x160000]

// Register CLK_RST_CONTROLLER_RST_DEV_ISP_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0                        _MK_ADDR_CONST(0x170000)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_0_SWR_ISP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0                    _MK_ADDR_CONST(0x170004)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0_SET_SWR_ISP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0                    _MK_ADDR_CONST(0x170008)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0_CLR_SWR_ISP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0                    _MK_ADDR_CONST(0x171000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0_CLK_ENB_ISP_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0                        _MK_ADDR_CONST(0x171004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0_SET_CLK_ENB_ISP_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0                        _MK_ADDR_CONST(0x171008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0_CLR_CLK_ENB_ISP_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0                    _MK_ADDR_CONST(0x172000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0_BOND_OUT_ISP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0                     _MK_ADDR_CONST(0x173000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_DFLL_ISP                        _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0_ISP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x173004)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0_SUPER_ISP_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0                      _MK_ADDR_CONST(0x174000)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_ISP_0_CLK_SPARE_REG_ISP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0                 _MK_ADDR_CONST(0x180000)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_0_SWR_VI_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0                     _MK_ADDR_CONST(0x180004)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_SET_0_SET_SWR_VI_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0                     _MK_ADDR_CONST(0x180008)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0_CLR_SWR_VI_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0                    _MK_ADDR_CONST(0x18000c)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0_SWR_TSCTNVI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0                        _MK_ADDR_CONST(0x180010)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0_SET_SWR_TSCTNVI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0                        _MK_ADDR_CONST(0x180014)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0_CLR_SWR_TSCTNVI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0                     _MK_ADDR_CONST(0x181000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0_CLK_ENB_VI_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0                 _MK_ADDR_CONST(0x181004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0_SET_CLK_ENB_VI_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0                 _MK_ADDR_CONST(0x181008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0_CLR_CLK_ENB_VI_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0                     _MK_ADDR_CONST(0x182000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0_BOND_OUT_VI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      _MK_ADDR_CONST(0x183000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   _MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    _MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   _MK_MASK_CONST(0xe30000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DFLL_VI                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 1585156 [0x183004]

// Register CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0                       _MK_ADDR_CONST(0x183008)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SCR                   0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_RESET_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_READ_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_WRITE_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_ENB_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0_SUPER_VI_DIV_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0                     _MK_ADDR_CONST(0x190000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0_SWR_SDMMC1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0                 _MK_ADDR_CONST(0x190004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0_SET_SWR_SDMMC1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0                 _MK_ADDR_CONST(0x190008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0_CLR_SWR_SDMMC1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0                 _MK_ADDR_CONST(0x191000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0_CLK_ENB_SDMMC1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0                     _MK_ADDR_CONST(0x191004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0_SET_CLK_ENB_SDMMC1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0                     _MK_ADDR_CONST(0x191008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0_CLR_CLK_ENB_SDMMC1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0                 _MK_ADDR_CONST(0x192000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0_BOND_OUT_SDMMC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0                  _MK_ADDR_CONST(0x193000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLC4_MUXED                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_M                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0                     _MK_ADDR_CONST(0x1a0000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0_SWR_SDMMC2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0                 _MK_ADDR_CONST(0x1a0004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0_SET_SWR_SDMMC2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0                 _MK_ADDR_CONST(0x1a0008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0_CLR_SWR_SDMMC2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0                 _MK_ADDR_CONST(0x1a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0_CLK_ENB_SDMMC2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0                     _MK_ADDR_CONST(0x1a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0_SET_CLK_ENB_SDMMC2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0                     _MK_ADDR_CONST(0x1a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0_CLR_CLK_ENB_SDMMC2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0                 _MK_ADDR_CONST(0x1a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0_BOND_OUT_SDMMC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0                  _MK_ADDR_CONST(0x1a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_CLK_M                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 1716228 [0x1a3004]

// Reserved address 1716232 [0x1a3008]

// Reserved address 1716236 [0x1a300c]

// Reserved address 1716240 [0x1a3010]

// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0                     _MK_ADDR_CONST(0x1b0000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0_SWR_SDMMC4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0                 _MK_ADDR_CONST(0x1b0004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0_SET_SWR_SDMMC4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0                 _MK_ADDR_CONST(0x1b0008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0_CLR_SWR_SDMMC4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0                 _MK_ADDR_CONST(0x1b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0_CLK_ENB_SDMMC4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0                     _MK_ADDR_CONST(0x1b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0_SET_CLK_ENB_SDMMC4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0                     _MK_ADDR_CONST(0x1b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0_CLR_CLK_ENB_SDMMC4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0                 _MK_ADDR_CONST(0x1b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0_BOND_OUT_SDMMC4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0                  _MK_ADDR_CONST(0x1b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_MASK                       _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_READ_MASK                        _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WRITE_MASK                       _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT2_LJ                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT0_LJ                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT2                        _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT1                        _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_OUT1_LJ                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_CLK_M                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC4_VCO                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SHIFT                  _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_RANGE                  26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INVERT_DCD_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0                      _MK_ADDR_CONST(0x1b3004)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT0_SHAPER_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_N1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_P1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_ACTIVE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_SW_BYPASS_BYPASS                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DF_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_DR_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0                      _MK_ADDR_CONST(0x1b3008)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT1_SHAPER_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_N1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_P1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_ACTIVE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_SW_BYPASS_BYPASS                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DF_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_DR_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0                      _MK_ADDR_CONST(0x1b300c)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_ENABLE_SDMMC4_PLLC4_OUT2_SHAPER_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_N1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_P1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_ACTIVE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_SW_BYPASS_BYPASS                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DF_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_DR_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0                 _MK_ADDR_CONST(0x1b3010)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_ENABLE_SDMMC4_DIV_CLK_SHAPER_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_RANGE                  11:11
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_RANGE                  10:10
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_RANGE                  9:9
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_RANGE                  8:8
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                    7:7
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                        DEFAULT_SETTING
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                      6:6
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                  ACTIVE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_RANGE                     5:5
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DF_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                     4:3
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_RANGE                     2:2
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_DR_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                     1:0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0_SDMMC4_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 1781780 [0x1b3014]

// Reserved address 1781784 [0x1b3018]

// Reserved address 1781788 [0x1b301c]

// Reserved address 1781792 [0x1b3020]

// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0                      _MK_ADDR_CONST(0x1c0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0                  _MK_ADDR_CONST(0x1c0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0_SET_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0                  _MK_ADDR_CONST(0x1c0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0_CLR_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0                  _MK_ADDR_CONST(0x1c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0_CLK_ENB_UARTA_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0                      _MK_ADDR_CONST(0x1c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0_SET_CLK_ENB_UARTA_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0                      _MK_ADDR_CONST(0x1c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0_CLR_CLK_ENB_UARTA_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0                  _MK_ADDR_CONST(0x1c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   _MK_ADDR_CONST(0x1c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLC4_MUXED                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0                      _MK_ADDR_CONST(0x1d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0                  _MK_ADDR_CONST(0x1d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0_SET_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0                  _MK_ADDR_CONST(0x1d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0_CLR_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0                  _MK_ADDR_CONST(0x1d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0_CLK_ENB_UARTB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0                      _MK_ADDR_CONST(0x1d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0_SET_CLK_ENB_UARTB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0                      _MK_ADDR_CONST(0x1d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0_CLR_CLK_ENB_UARTB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0                  _MK_ADDR_CONST(0x1d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   _MK_ADDR_CONST(0x1d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0                     _MK_ADDR_CONST(0x1e0000)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_0_SWR_HOST1X_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0                 _MK_ADDR_CONST(0x1e0004)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0_SET_SWR_HOST1X_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0                 _MK_ADDR_CONST(0x1e0008)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0_CLR_SWR_HOST1X_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0                 _MK_ADDR_CONST(0x1e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0_CLK_ENB_HOST1X_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0                     _MK_ADDR_CONST(0x1e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0_SET_CLK_ENB_HOST1X_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0                     _MK_ADDR_CONST(0x1e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0_CLR_CLK_ENB_HOST1X_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0                 _MK_ADDR_CONST(0x1e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  _MK_ADDR_CONST(0x1e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLREFE_OUT                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC2_OUT0                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_CLK_M                     _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 1978372 [0x1e3004]

// Reserved address 1978376 [0x1e3008]

// Reserved address 1978380 [0x1e300c]

// Reserved address 1978384 [0x1e3010]

// Reserved address 1978388 [0x1e3014]

// Reserved address 2031616 [0x1f0000]

// Register CLK_RST_CONTROLLER_RST_DEV_EMC_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0                        _MK_ADDR_CONST(0x200000)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_MEM_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_0_SWR_EMC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0                    _MK_ADDR_CONST(0x200004)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_MEM_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0_SET_SWR_EMC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0                    _MK_ADDR_CONST(0x200008)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_MEM_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0_CLR_SWR_EMC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0                    _MK_ADDR_CONST(0x201000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_RESET_VAL                  _MK_MASK_CONST(0x3c0678)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_RESET_MASK                         _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_READ_MASK                  _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_WRITE_MASK                         _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_RANGE                      21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CFPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_RANGE                      20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CEPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_RANGE                      19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CDPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_RANGE                      18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CCPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MCHUBSA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC1_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_IOBIST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_LATENCY_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_BBC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CPU_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_RANGE                      4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CBPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_RANGE                      3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MC_CAPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DLL_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_MEM_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0_CLK_ENB_EMC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0                        _MK_ADDR_CONST(0x201004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x3c0678)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_READ_MASK                      _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_RANGE                      21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CFPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_RANGE                      20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CEPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_RANGE                      19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CDPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_RANGE                      18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CCPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MCHUBSA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC1_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_IOBIST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_LATENCY_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_RANGE                      4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CBPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_RANGE                      3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MC_CAPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_MEM_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0_SET_CLK_ENB_EMC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0                        _MK_ADDR_CONST(0x201008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x3c0678)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_RANGE                      21:21
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CFPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_RANGE                      20:20
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CEPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_RANGE                      19:19
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CDPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_RANGE                      18:18
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CCPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_RANGE                      10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MCHUBSA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC1_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_IOBIST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_RANGE                  7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_LATENCY_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                       6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                       5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_RANGE                      4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CBPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_RANGE                      3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MC_CAPA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                      2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_MEM_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0_CLR_CLK_ENB_EMC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0                    _MK_ADDR_CONST(0x202000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_RESET_MASK                         _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_READ_MASK                  _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_WRITE_MASK                         _MK_MASK_CONST(0x3c07ff)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_RANGE                     21:21
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CFPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_RANGE                     20:20
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CEPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_RANGE                     19:19
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CDPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_RANGE                     18:18
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CCPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_RANGE                     10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MCHUBSA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SHIFT                 _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_RANGE                 9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_RANGE                  8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_IOBIST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SHIFT                 _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_RANGE                 7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_LATENCY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_RANGE                      6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_RANGE                      5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_RANGE                     4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CBPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_RANGE                     3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MC_CAPA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_RANGE                     2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_MEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0_BOND_OUT_EMC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     _MK_ADDR_CONST(0x203000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   _MK_MASK_CONST(0x60100000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_UD                      _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLMB_UD                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLMB_OUT0                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_UD                      _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_RANGE                      27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SHIFT                        _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_RANGE                        26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_INVERT_DCD_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SHIFT                    _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_RANGE                    25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_RANGE                   20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_PLLC_OUT_FOR_EMC_EN_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_MC_EMC_SAME_FREQ_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SHIFT                       _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_RANGE                       15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_CLK_DIV2_EN_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0                     _MK_ADDR_CONST(0x203004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_RESET_VAL                   _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0                 _MK_ADDR_CONST(0x203008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_RESET_VAL                       _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_RESET_MASK                      _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_READ_MASK                       _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_WRITE_MASK                      _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                        _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                      _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_RANGE                      11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                 _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0                    _MK_ADDR_CONST(0x20300c)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SCR                        0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                        _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                        11:11
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                        10:10
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                        _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                        9:9
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                        8:8
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                  7:7
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                      DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                    6:6
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                        ACTIVE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                   5:5
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                   4:3
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                   2:2
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                   1:0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0                       _MK_ADDR_CONST(0x203010)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                  31:31
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                        _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0                        _MK_ADDR_CONST(0x203014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_RESET_VAL                      _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_RESET_MASK                     _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_READ_MASK                      _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_WRITE_MASK                     _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                  CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                    _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0                      _MK_ADDR_CONST(0x204000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMC_0_CLK_SPARE_REG_EMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 2162688 [0x210000]

// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0                 _MK_ADDR_CONST(0x220000)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0_SWR_EXTPERIPH4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0                     _MK_ADDR_CONST(0x220004)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0_SET_SWR_EXTPERIPH4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0                     _MK_ADDR_CONST(0x220008)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0_CLR_SWR_EXTPERIPH4_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0                     _MK_ADDR_CONST(0x221000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0_CLK_ENB_EXTPERIPH4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0                 _MK_ADDR_CONST(0x221004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0_SET_CLK_ENB_EXTPERIPH4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0                 _MK_ADDR_CONST(0x221008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0_CLR_CLK_ENB_EXTPERIPH4_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0                     _MK_ADDR_CONST(0x222000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0_BOND_OUT_EXTPERIPH4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0                      _MK_ADDR_CONST(0x223000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0_EXTPERIPH4_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 2240516 [0x223004]

// Reserved address 2240520 [0x223008]

// Register CLK_RST_CONTROLLER_RST_DEV_SPI4_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0                       _MK_ADDR_CONST(0x230000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_0_SWR_SPI4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0                   _MK_ADDR_CONST(0x230004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0_SET_SWR_SPI4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0                   _MK_ADDR_CONST(0x230008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0_CLR_SWR_SPI4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0                   _MK_ADDR_CONST(0x231000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0_CLK_ENB_SPI4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0                       _MK_ADDR_CONST(0x231004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0_SET_CLK_ENB_SPI4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0                       _MK_ADDR_CONST(0x231008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0_CLR_CLK_ENB_SPI4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0                   _MK_ADDR_CONST(0x232000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0_BOND_OUT_SPI4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0                    _MK_ADDR_CONST(0x233000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0_SPI4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0                       _MK_ADDR_CONST(0x240000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0_SWR_I2C3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0                   _MK_ADDR_CONST(0x240004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0_SET_SWR_I2C3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0                   _MK_ADDR_CONST(0x240008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0_CLR_SWR_I2C3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0                   _MK_ADDR_CONST(0x241000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0_CLK_ENB_I2C3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0                       _MK_ADDR_CONST(0x241004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0_SET_CLK_ENB_I2C3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0                       _MK_ADDR_CONST(0x241008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0_CLR_CLK_ENB_I2C3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0                   _MK_ADDR_CONST(0x242000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0_BOND_OUT_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                    _MK_ADDR_CONST(0x243000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0                     _MK_ADDR_CONST(0x250000)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0_SWR_SDMMC3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0                 _MK_ADDR_CONST(0x250004)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0_SET_SWR_SDMMC3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0                 _MK_ADDR_CONST(0x250008)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0_CLR_SWR_SDMMC3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0                 _MK_ADDR_CONST(0x251000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0_CLK_ENB_SDMMC3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0                     _MK_ADDR_CONST(0x251004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0_SET_CLK_ENB_SDMMC3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0                     _MK_ADDR_CONST(0x251008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0_CLR_CLK_ENB_SDMMC3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0                 _MK_ADDR_CONST(0x252000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0_BOND_OUT_SDMMC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0                  _MK_ADDR_CONST(0x253000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLC4_MUXED                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_M                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0                      _MK_ADDR_CONST(0x260000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_0_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0                  _MK_ADDR_CONST(0x260004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0_SET_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0                  _MK_ADDR_CONST(0x260008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0_CLR_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0                  _MK_ADDR_CONST(0x261000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0_CLK_ENB_UARTD_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0                      _MK_ADDR_CONST(0x261004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0_SET_CLK_ENB_UARTD_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0                      _MK_ADDR_CONST(0x261008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0_CLR_CLK_ENB_UARTD_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0                  _MK_ADDR_CONST(0x262000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0_BOND_OUT_UARTD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0                   _MK_ADDR_CONST(0x263000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 2502660 [0x263004]

// Reserved address 2502664 [0x263008]

// Reserved address 2555904 [0x270000]

// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0                      _MK_ADDR_CONST(0x280000)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_0_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0                  _MK_ADDR_CONST(0x280004)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0_SET_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0                  _MK_ADDR_CONST(0x280008)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0_CLR_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0                  _MK_ADDR_CONST(0x281000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0_CLK_ENB_CSITE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0                      _MK_ADDR_CONST(0x281004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0_SET_CLK_ENB_CSITE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0                      _MK_ADDR_CONST(0x281008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0_CLR_CLK_ENB_CSITE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0                  _MK_ADDR_CONST(0x282000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0_BOND_OUT_CSITE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0                   _MK_ADDR_CONST(0x283000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLREFE_OUT1                        _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_S                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC4_MUXED                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0                   _MK_ADDR_CONST(0x290000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0_CLK_ENB_I2S1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0                       _MK_ADDR_CONST(0x290004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0_SET_CLK_ENB_I2S1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0                       _MK_ADDR_CONST(0x290008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0_CLR_CLK_ENB_I2S1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0                   _MK_ADDR_CONST(0x291000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    _MK_ADDR_CONST(0x292000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0                        _MK_ADDR_CONST(0x292004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_DTV_0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0                        _MK_ADDR_CONST(0x2a0000)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_0_SWR_DTV_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0                    _MK_ADDR_CONST(0x2a0004)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0_SET_SWR_DTV_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0                    _MK_ADDR_CONST(0x2a0008)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0_CLR_SWR_DTV_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0                    _MK_ADDR_CONST(0x2a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0_CLK_ENB_DTV_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0                        _MK_ADDR_CONST(0x2a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0_SET_CLK_ENB_DTV_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0                        _MK_ADDR_CONST(0x2a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0_CLR_CLK_ENB_DTV_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0                    _MK_ADDR_CONST(0x2a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0_BOND_OUT_DTV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0                     _MK_ADDR_CONST(0x2a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_RESET_MASK                  _MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_READ_MASK                   _MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_WRITE_MASK                  _MK_MASK_CONST(0x2000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_RANGE                   25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0_DTV_INV_CLK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 2764804 [0x2a3004]

// Reserved address 2764808 [0x2a3008]

// Reserved address 2764812 [0x2a300c]

// Reserved address 2764816 [0x2a3010]

// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0                       _MK_ADDR_CONST(0x2b0000)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_0_SWR_TSEC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0                   _MK_ADDR_CONST(0x2b0004)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0_SET_SWR_TSEC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0                   _MK_ADDR_CONST(0x2b0008)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0_CLR_SWR_TSEC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0                   _MK_ADDR_CONST(0x2b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0_CLK_ENB_TSEC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0                       _MK_ADDR_CONST(0x2b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0_SET_CLK_ENB_TSEC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0                       _MK_ADDR_CONST(0x2b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0_CLR_CLK_ENB_TSEC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0                   _MK_ADDR_CONST(0x2b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0_BOND_OUT_TSEC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0                    _MK_ADDR_CONST(0x2b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC2_OUT0                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_PLLC3_OUT0                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_DFLL_TSEC                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0_TSEC_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0                     _MK_ADDR_CONST(0x2b3004)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SCR                         0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_RESET_VAL                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_RESET_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_READ_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_WRITE_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0_SUPER_TSEC_DIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0                 _MK_ADDR_CONST(0x2c0000)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_0_SWR_LA_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0                     _MK_ADDR_CONST(0x2c0004)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_SET_0_SET_SWR_LA_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0                     _MK_ADDR_CONST(0x2c0008)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0_CLR_SWR_LA_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DP2_0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0                        _MK_ADDR_CONST(0x2c000c)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_0_SWR_DP2_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0                    _MK_ADDR_CONST(0x2c0010)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0_SET_SWR_DP2_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0                    _MK_ADDR_CONST(0x2c0014)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0_CLR_SWR_DP2_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0                     _MK_ADDR_CONST(0x2c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0_CLK_ENB_LA_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0                 _MK_ADDR_CONST(0x2c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0_SET_CLK_ENB_LA_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0                 _MK_ADDR_CONST(0x2c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0_CLR_CLK_ENB_LA_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0                    _MK_ADDR_CONST(0x2c100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0_CLK_ENB_DP2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0                        _MK_ADDR_CONST(0x2c1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0_SET_CLK_ENB_DP2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0                        _MK_ADDR_CONST(0x2c1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0_CLR_CLK_ENB_DP2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0                     _MK_ADDR_CONST(0x2c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0_BOND_OUT_LA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0                    _MK_ADDR_CONST(0x2c2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0_BOND_OUT_DP2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0                      _MK_ADDR_CONST(0x2c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_VAL                    _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLREFE_OUT1                      _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_S                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_M                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC4_MUXED                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 2895876 [0x2c3004]

// Reserved address 2895880 [0x2c3008]

// Reserved address 2895884 [0x2c300c]

// Reserved address 2895888 [0x2c3010]

// Reserved address 2895892 [0x2c3014]

// Reserved address 2895896 [0x2c3018]

// Reserved address 2895900 [0x2c301c]

// Reserved address 2895904 [0x2c3020]

// Reserved address 2895908 [0x2c3024]

// Reserved address 2895912 [0x2c3028]

// Reserved address 2895916 [0x2c302c]

// Reserved address 2895920 [0x2c3030]

// Reserved address 2895924 [0x2c3034]

// Reserved address 2895928 [0x2c3038]

// Reserved address 2895932 [0x2c303c]

// Reserved address 2895936 [0x2c3040]

// Reserved address 2895940 [0x2c3044]

// Reserved address 2949120 [0x2d0000]

// Reserved address 2949124 [0x2d0004]

// Reserved address 2949128 [0x2d0008]

// Reserved address 2949132 [0x2d000c]

// Reserved address 3014656 [0x2e0000]

// Reserved address 3080192 [0x2f0000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0                   _MK_ADDR_CONST(0x300000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0_CLK_ENB_I2S4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0                       _MK_ADDR_CONST(0x300004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0_SET_CLK_ENB_I2S4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0                       _MK_ADDR_CONST(0x300008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0_CLR_CLK_ENB_I2S4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0                   _MK_ADDR_CONST(0x301000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0_BOND_OUT_I2S4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0                    _MK_ADDR_CONST(0x302000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_RESET_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_READ_MASK                  _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_WRITE_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0_I2S4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0                        _MK_ADDR_CONST(0x302004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0                   _MK_ADDR_CONST(0x310000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0_CLK_ENB_I2S5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0                       _MK_ADDR_CONST(0x310004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0_SET_CLK_ENB_I2S5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0                       _MK_ADDR_CONST(0x310008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0_CLR_CLK_ENB_I2S5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0                   _MK_ADDR_CONST(0x311000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0_BOND_OUT_I2S5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0                    _MK_ADDR_CONST(0x312000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_RESET_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_READ_MASK                  _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_WRITE_MASK                         _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0_I2S5_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0                        _MK_ADDR_CONST(0x312004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0                       _MK_ADDR_CONST(0x320000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0_SWR_I2C4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0                   _MK_ADDR_CONST(0x320004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0_SET_SWR_I2C4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0                   _MK_ADDR_CONST(0x320008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0_CLR_SWR_I2C4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0                   _MK_ADDR_CONST(0x321000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0_CLK_ENB_I2C4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0                       _MK_ADDR_CONST(0x321004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0_SET_CLK_ENB_I2C4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0                       _MK_ADDR_CONST(0x321008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0_CLR_CLK_ENB_I2C4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0                   _MK_ADDR_CONST(0x322000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0_BOND_OUT_I2C4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0                    _MK_ADDR_CONST(0x323000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0                   _MK_ADDR_CONST(0x330000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0_CLK_ENB_AHUB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0                       _MK_ADDR_CONST(0x330004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0_SET_CLK_ENB_AHUB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0                       _MK_ADDR_CONST(0x330008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0_CLR_CLK_ENB_AHUB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0                   _MK_ADDR_CONST(0x331000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0_BOND_OUT_AHUB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0                    _MK_ADDR_CONST(0x332000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_RESET_MASK                         _MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_READ_MASK                  _MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_WRITE_MASK                         _MK_MASK_CONST(0xf01f00ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_CLK_SRC_ALT                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_RANGE                     20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_ENABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_DIS_DISABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_RANGE                    19:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_INIT_ENUM                        SPDIFIN
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_SRC_RATE_I2S6                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0_AHUB_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 3350532 [0x332004]

// Reserved address 3350536 [0x332008]

// Reserved address 3350540 [0x33200c]

// Reserved address 3350544 [0x332010]

// Register CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0                       _MK_ADDR_CONST(0x340000)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0_SWR_HDA2CODEC_2X_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0                   _MK_ADDR_CONST(0x340004)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0_SET_SWR_HDA2CODEC_2X_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0                   _MK_ADDR_CONST(0x340008)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0_CLR_SWR_HDA2CODEC_2X_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0                   _MK_ADDR_CONST(0x341000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0_CLK_ENB_HDA2CODEC_2X_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0                       _MK_ADDR_CONST(0x341004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0_SET_CLK_ENB_HDA2CODEC_2X_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0                       _MK_ADDR_CONST(0x341008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0_CLR_CLK_ENB_HDA2CODEC_2X_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0                   _MK_ADDR_CONST(0x342000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0_BOND_OUT_HDA2CODEC_2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0                    _MK_ADDR_CONST(0x343000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_CLK_S                 _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0_HDA2CODEC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 3473408 [0x350000]

// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0                 _MK_ADDR_CONST(0x360000)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0_SWR_EXTPERIPH1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0                     _MK_ADDR_CONST(0x360004)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0_SET_SWR_EXTPERIPH1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0                     _MK_ADDR_CONST(0x360008)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0_CLR_SWR_EXTPERIPH1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0                     _MK_ADDR_CONST(0x361000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0_CLK_ENB_EXTPERIPH1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0                 _MK_ADDR_CONST(0x361004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0_SET_CLK_ENB_EXTPERIPH1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0                 _MK_ADDR_CONST(0x361008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0_CLR_CLK_ENB_EXTPERIPH1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0                     _MK_ADDR_CONST(0x362000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0_BOND_OUT_EXTPERIPH1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0                      _MK_ADDR_CONST(0x363000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0_EXTPERIPH1_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0                 _MK_ADDR_CONST(0x370000)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0_SWR_EXTPERIPH2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0                     _MK_ADDR_CONST(0x370004)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0_SET_SWR_EXTPERIPH2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0                     _MK_ADDR_CONST(0x370008)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0_CLR_SWR_EXTPERIPH2_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0                     _MK_ADDR_CONST(0x371000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0_CLK_ENB_EXTPERIPH2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0                 _MK_ADDR_CONST(0x371004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0_SET_CLK_ENB_EXTPERIPH2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0                 _MK_ADDR_CONST(0x371008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0_CLR_CLK_ENB_EXTPERIPH2_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0                     _MK_ADDR_CONST(0x372000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0_BOND_OUT_EXTPERIPH2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0                      _MK_ADDR_CONST(0x373000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0_EXTPERIPH2_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0                 _MK_ADDR_CONST(0x380000)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0_SWR_EXTPERIPH3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0                     _MK_ADDR_CONST(0x380004)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0_SET_SWR_EXTPERIPH3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0                     _MK_ADDR_CONST(0x380008)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0_CLR_SWR_EXTPERIPH3_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0                     _MK_ADDR_CONST(0x381000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0_CLK_ENB_EXTPERIPH3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0                 _MK_ADDR_CONST(0x381004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0_SET_CLK_ENB_EXTPERIPH3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0                 _MK_ADDR_CONST(0x381008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0_CLR_CLK_ENB_EXTPERIPH3_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0                     _MK_ADDR_CONST(0x382000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0_BOND_OUT_EXTPERIPH3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0                      _MK_ADDR_CONST(0x383000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0_EXTPERIPH3_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 3682308 [0x383004]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0                       _MK_ADDR_CONST(0x390000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0_CLK_ENB_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0                   _MK_ADDR_CONST(0x390004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0_SET_CLK_ENB_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0                   _MK_ADDR_CONST(0x390008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0_CLR_CLK_ENB_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0                       _MK_ADDR_CONST(0x391000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0_BOND_OUT_I2C_SLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0                        _MK_ADDR_CONST(0x392000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 3743748 [0x392004]

// Reserved address 3743752 [0x392008]

// Reserved address 3743756 [0x39200c]

// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0                       _MK_ADDR_CONST(0x3a0000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_0_SWR_SOR1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0                   _MK_ADDR_CONST(0x3a0004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0_SET_SWR_SOR1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0                   _MK_ADDR_CONST(0x3a0008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0_CLR_SWR_SOR1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0                   _MK_ADDR_CONST(0x3a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0_CLK_ENB_SOR1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0                       _MK_ADDR_CONST(0x3a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0_SET_CLK_ENB_SOR1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0                       _MK_ADDR_CONST(0x3a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0_CLR_CLK_ENB_SOR1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0                   _MK_ADDR_CONST(0x3a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0_BOND_OUT_SOR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0                    _MK_ADDR_CONST(0x3a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_RESET_MASK                         _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_READ_MASK                  _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_WRITE_MASK                         _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD_OUT2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD2_OUT0                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SRC_PLLD3_OUT0                    _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SHIFT                        _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SHIFT                        _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_SEL0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0_SOR1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0                       _MK_ADDR_CONST(0x3b0000)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_HDA2HDMICODEC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_0_SWR_SOR0_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0                   _MK_ADDR_CONST(0x3b0004)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_HDA2HDMICODEC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0_SET_SWR_SOR0_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0                   _MK_ADDR_CONST(0x3b0008)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_RANGE                   1:1
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_HDA2HDMICODEC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0_CLR_SWR_SOR0_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0                      _MK_ADDR_CONST(0x3b000c)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_0_SWR_DPAUX_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0                  _MK_ADDR_CONST(0x3b0010)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0_SET_SWR_DPAUX_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0                  _MK_ADDR_CONST(0x3b0014)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0_CLR_SWR_DPAUX_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0                     _MK_ADDR_CONST(0x3b0018)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0_SWR_DPAUX1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0                 _MK_ADDR_CONST(0x3b001c)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0_SET_SWR_DPAUX1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0                 _MK_ADDR_CONST(0x3b0020)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0_CLR_SWR_DPAUX1_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0                        _MK_ADDR_CONST(0x3b0024)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_0_SWR_CEC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0                    _MK_ADDR_CONST(0x3b0028)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0_SET_SWR_CEC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0                    _MK_ADDR_CONST(0x3b002c)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0_CLR_SWR_CEC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0                   _MK_ADDR_CONST(0x3b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_HDA2HDMICODEC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0_CLK_ENB_SOR0_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0                       _MK_ADDR_CONST(0x3b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_HDA2HDMICODEC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0_SET_CLK_ENB_SOR0_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0                       _MK_ADDR_CONST(0x3b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_RANGE                       1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_HDA2HDMICODEC_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0_CLR_CLK_ENB_SOR0_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0                  _MK_ADDR_CONST(0x3b100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0_CLK_ENB_DPAUX_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0                      _MK_ADDR_CONST(0x3b1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0_SET_CLK_ENB_DPAUX_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0                      _MK_ADDR_CONST(0x3b1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0_CLR_CLK_ENB_DPAUX_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0                 _MK_ADDR_CONST(0x3b1018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0_CLK_ENB_DPAUX1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0                     _MK_ADDR_CONST(0x3b101c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0_SET_CLK_ENB_DPAUX1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0                     _MK_ADDR_CONST(0x3b1020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0_CLR_CLK_ENB_DPAUX1_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0                    _MK_ADDR_CONST(0x3b1024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0_CLK_ENB_CEC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0                        _MK_ADDR_CONST(0x3b1028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0_SET_CLK_ENB_CEC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0                        _MK_ADDR_CONST(0x3b102c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0_CLR_CLK_ENB_CEC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0                   _MK_ADDR_CONST(0x3b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_RANGE                      1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_HDA2HDMICODEC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0_BOND_OUT_SOR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0                  _MK_ADDR_CONST(0x3b2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0_BOND_OUT_DPAUX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0                 _MK_ADDR_CONST(0x3b2008)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0_BOND_OUT_DPAUX1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0                    _MK_ADDR_CONST(0x3b200c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0_BOND_OUT_CEC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0                    _MK_ADDR_CONST(0x3b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_RESET_MASK                         _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_READ_MASK                  _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_WRITE_MASK                         _MK_MASK_CONST(0xe000c0ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD_OUT2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD2_OUT0                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SRC_PLLD3_OUT0                    _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SHIFT                        _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_RANGE                        15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SHIFT                        _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_RANGE                        14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_SEL0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0_SOR0_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0                     _MK_ADDR_CONST(0x3b4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0_CLK_SPARE_REG_SOR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 3883012 [0x3b4004]

// Reserved address 3883016 [0x3b4008]

// Register CLK_RST_CONTROLLER_RST_DEV_SATA_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0                       _MK_ADDR_CONST(0x3c0000)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATACOLD_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_0_SWR_SATA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0                   _MK_ADDR_CONST(0x3c0004)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATACOLD_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0_SET_SWR_SATA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0                   _MK_ADDR_CONST(0x3c0008)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATACOLD_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0_CLR_SWR_SATA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0                   _MK_ADDR_CONST(0x3c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_OOB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0_CLK_ENB_SATA_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0                       _MK_ADDR_CONST(0x3c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_OOB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0_SET_CLK_ENB_SATA_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0                       _MK_ADDR_CONST(0x3c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_OOB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0_CLR_CLK_ENB_SATA_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0                   _MK_ADDR_CONST(0x3c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_RANGE                        2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_OOB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0_BOND_OUT_SATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0                        _MK_ADDR_CONST(0x3c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_RESET_VAL                      _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0_SATA_OOB_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0                    _MK_ADDR_CONST(0x3c3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_RESET_VAL                  _MK_MASK_CONST(0xc1000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_RESET_MASK                         _MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_READ_MASK                  _MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_WRITE_MASK                         _MK_MASK_CONST(0xe10000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_RANGE                     24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_AUX_CLK_ENB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0_SATA_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0                     _MK_ADDR_CONST(0x3c4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_SATA_0_CLK_SPARE_REG_SATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0                        _MK_ADDR_CONST(0x3d0000)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_0_SWR_HDA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0                    _MK_ADDR_CONST(0x3d0004)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0_SET_SWR_HDA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0                    _MK_ADDR_CONST(0x3d0008)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0_CLR_SWR_HDA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0                    _MK_ADDR_CONST(0x3d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0_CLK_ENB_HDA_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0                        _MK_ADDR_CONST(0x3d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0_SET_CLK_ENB_HDA_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0                        _MK_ADDR_CONST(0x3d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0_CLR_CLK_ENB_HDA_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0                    _MK_ADDR_CONST(0x3d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0_BOND_OUT_HDA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0                     _MK_ADDR_CONST(0x3d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_CLK_S                   _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_SRC_CLK_M                   _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0_HDA_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SE_0
#define CLK_RST_CONTROLLER_RST_DEV_SE_0                 _MK_ADDR_CONST(0x3e0000)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_0_SWR_SE_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0                     _MK_ADDR_CONST(0x3e0004)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_SET_0_SET_SWR_SE_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0                     _MK_ADDR_CONST(0x3e0008)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0_CLR_SWR_SE_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0                     _MK_ADDR_CONST(0x3e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0_CLK_ENB_SE_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0                 _MK_ADDR_CONST(0x3e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0_SET_CLK_ENB_SE_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0                 _MK_ADDR_CONST(0x3e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0_CLR_CLK_ENB_SE_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0                     _MK_ADDR_CONST(0x3e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0_BOND_OUT_SE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0                      _MK_ADDR_CONST(0x3e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC2_OUT0                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_PLLC3_OUT0                        _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_DFLL_SE                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE_0_SE_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0                       _MK_ADDR_CONST(0x3e3004)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SCR                   0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_RESET_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_READ_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_WRITE_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_ENB_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0_SUPER_SE_DIV_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 4075528 [0x3e3008]

// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0                     _MK_ADDR_CONST(0x3f0000)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0x190101)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff07)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_RANGE                       31:31
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_BG_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_RANGE                        30:29
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG14V_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_RANGE                        28:27
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_VREG10V_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KCP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_KVCO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                        23:16
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                      _MK_MASK_CONST(0x19)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_RANGE                    7:3
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_RANGE                    2:2
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCK_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_RANGE                   1:1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_RESERVED2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_RANGE                   0:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0_UTMIP_PLL_EN_LCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0                     _MK_ADDR_CONST(0x3f0004)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x180150c0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x80)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xf8000fff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                 _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                 11:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                       _MK_MASK_CONST(0xc0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x80)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                      12:12
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                        _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                        13:13
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                      14:14
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                        _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                        15:15
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                    16:16
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                      17:17
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_FIELD                        _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_RANGE                        26:18
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_DEFAULT_MASK                 _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLL_RSVD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                   31:27
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0                     _MK_ADDR_CONST(0x3f0008)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x41318015)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0x7fffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffc0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_READ_MASK                   _MK_MASK_CONST(0x7fffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0x43ffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                        30:30
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SHIFT                       _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_RANGE                       29:26
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_RANGE                 25:25
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_RANGE                       24:24
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_D_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                    _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                    23:18
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                  _MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                       _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_FIELD                       _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_RANGE                       17:6
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                     _MK_MASK_CONST(0x600)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_RANGE                 5:5
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_RANGE                       4:4
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_C_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_RANGE                 3:3
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_RANGE                       2:2
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_B_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_RANGE                 1:1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_RANGE                       0:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0_UTMIP_FORCE_PD_SAMP_A_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0                     _MK_ADDR_CONST(0x3f000c)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SHIFT                 _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_RANGE                 24:24
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SHIFT                     _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_RANGE                     25:25
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0_UTMIP_PLL_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0                      _MK_ADDR_CONST(0x3f0010)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SCR                  0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x600000f)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x8f0000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x1000040)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1000046)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x8f0000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x30000ff)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_RANGE                   31:31
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_RANGE                      27:26
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_INIT_ENUM                  SEQ_ON
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_OFF                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_ON                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_STATE_SEQ_BUSY                   _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SHIFT                        _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_RANGE                        25:25
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_INIT_ENUM                    SEQ_ON
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SEQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_START_STATE_SEQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_RANGE                     24:24
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SHIFT                        _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_RANGE                        7:7
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_PD_INCLUDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_RANGE                    6:6
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SW_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_USE_LOCKDET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_RANGE                  5:5
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_RESET_INPUT_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_RANGE                   4:4
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_SEQ_IN_SWCTL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_RANGE                      3:3
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_OVERRIDE_VALUE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_RANGE                       2:2
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_CLK_ENABLE_SWCTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_RANGE                    1:1
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_OVERRIDE_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_RANGE                     0:0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0_UTMIPLL_IDDQ_SWCTL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0                      _MK_ADDR_CONST(0x3f0014)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SCR                  0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x8012280f)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xff123fff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SHIFT                 _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_RANGE                 31:24
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_DEFAULT                       _MK_MASK_CONST(0x80)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SHIFT                       _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_RANGE                       20:20
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_CLK_SWITCH_SWCTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_RANGE                      17:17
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_USE_SWITCH_DETECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SHIFT                       _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_RANGE                       13:10
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_DEFAULT                     _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_IDDQ2_ENABLE_DLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_FIELD                       _MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SHIFT)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_RANGE                       9:0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0_UTMIPLL_LOCK_DLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0                        _MK_ADDR_CONST(0x400000)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_0_SWR_APE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0                    _MK_ADDR_CONST(0x400004)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_SET_0_SET_SWR_APE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0                    _MK_ADDR_CONST(0x400008)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0_CLR_SWR_APE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0                    _MK_ADDR_CONST(0x401000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0_CLK_ENB_APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0                        _MK_ADDR_CONST(0x401004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0_SET_CLK_ENB_APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0                        _MK_ADDR_CONST(0x401008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0_CLR_CLK_ENB_APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0                        _MK_ADDR_CONST(0x40100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0_CLK_ENB_APB2APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0                    _MK_ADDR_CONST(0x401010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0_SET_CLK_ENB_APB2APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0                    _MK_ADDR_CONST(0x401014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0_CLR_CLK_ENB_APB2APE_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0                   _MK_ADDR_CONST(0x401018)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0_CLK_ENB_IQC1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0                       _MK_ADDR_CONST(0x40101c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0_SET_CLK_ENB_IQC1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0                       _MK_ADDR_CONST(0x401020)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0_CLR_CLK_ENB_IQC1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0                   _MK_ADDR_CONST(0x401024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0_CLK_ENB_IQC2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0                       _MK_ADDR_CONST(0x401028)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0_SET_CLK_ENB_IQC2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0                       _MK_ADDR_CONST(0x40102c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0_CLR_CLK_ENB_IQC2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0                    _MK_ADDR_CONST(0x402000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0_BOND_OUT_APE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0                        _MK_ADDR_CONST(0x402004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0_BOND_OUT_APB2APE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0                   _MK_ADDR_CONST(0x402008)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0_BOND_OUT_IQC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0                   _MK_ADDR_CONST(0x40200c)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0_BOND_OUT_IQC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0                 _MK_ADDR_CONST(0x403000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SCR                     0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_RESET_VAL                       _MK_MASK_CONST(0x700000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_RESET_MASK                      _MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_READ_MASK                       _MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_WRITE_MASK                      _MK_MASK_CONST(0x20f00000)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_RANGE                      29:29
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SPDIF_1X_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_RANGE                 23:20
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0_SYNC_CLK_SPDIF_DELCLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0                       _MK_ADDR_CONST(0x403004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_SPDIFIN                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_APE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0                     _MK_ADDR_CONST(0x403008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLA1_OUT1                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_APE_0_APE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD2_BASE_0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0                 _MK_ADDR_CONST(0x410000)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x42802)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_READ_MASK                       _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_FREQLOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_REF_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_LOCK_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SHIFT                        _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_DEFAULT                      _MK_MASK_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_NDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_BASE_0_PLLD2_MDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD2_MISC_0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0                 _MK_ADDR_CONST(0x410004)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_RESET_VAL                       _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_RESET_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_READ_MASK                       _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_WRITE_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_EN_LCKDET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KCP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_KVCO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLD2_MISC_0_PLLD2_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)


// Register CLK_RST_CONTROLLER_PLLD2_MISC1_0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0                        _MK_ADDR_CONST(0x410008)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_RESET_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_READ_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_WRITE_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SHIFT                       _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG14V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SHIFT                       _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_VREG10V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_MISC1_0_PLLD2_BG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0                       _MK_ADDR_CONST(0x41000c)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SDM_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_SSC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_EN_DITHER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CFG_0_PLLD2_SDM_TEST_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0                     _MK_ADDR_CONST(0x410010)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0_PLLD2_SDM_SSC_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0                     _MK_ADDR_CONST(0x410014)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_SSC_STEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0_PLLD2_SDM_DIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0                        _MK_ADDR_CONST(0x420000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0_CLK_ENB_PLLREFE_OUT_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0                    _MK_ADDR_CONST(0x420004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0_SET_CLK_ENB_PLLREFE_OUT_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0                    _MK_ADDR_CONST(0x420008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0_CLR_CLK_ENB_PLLREFE_OUT_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLREFE_BASE_0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0                       _MK_ADDR_CONST(0x42000c)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_RESET_VAL                     _MK_MASK_CONST(0x34104)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_RESET_MASK                    _MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_READ_MASK                     _MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_WRITE_MASK                    _MK_MASK_CONST(0xfc1fffff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_BYPASS_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SHIFT                  _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_RANGE                 29:29
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_INIT_ENUM                     REF_ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_REF_ENABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_REF_DIS_REF_DISABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_RANGE                     28:27
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KCP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SHIFT                    _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_RANGE                    26:26
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_KVCO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_RANGE                    20:16
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_DEFAULT                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_DEFAULT                  _MK_MASK_CONST(0x41)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_DEFAULT                  _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_BASE_0_PLLREFE_DIVM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLREFE_MISC_0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0                       _MK_ADDR_CONST(0x420010)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_RESET_VAL                     _MK_MASK_CONST(0x41000000)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_WRITE_MASK                    _MK_MASK_CONST(0xe7ffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_RANGE                   31:31
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SEL_CLKIN_PEX_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_EN_LCKDET_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_FREQLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SHIFT                     _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_RANGE                     26:25
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_FO                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_PTS_VCO                       _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_RANGE                    24:24
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_IDDQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_FIELD                   _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_RANGE                   23:0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC_0_PLLREFE_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLREFE_OUT_0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0                        _MK_ADDR_CONST(0x420014)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_RESET_VAL                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_RESET_MASK                     _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_READ_MASK                      _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_WRITE_MASK                     _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_DIV_BYP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_RANGE                       15:8
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RATIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_CLKEN_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RANGE                        0:0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_INIT_ENUM                    RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RESET_ENABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLREFE_OUT_0_PLLREFE_OUT1_RSTN_RESET_DISABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLREFE_MISC1_0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0                      _MK_ADDR_CONST(0x420018)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_RESET_MASK                   _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_READ_MASK                    _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_WRITE_MASK                   _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_RANGE                   14:13
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG14V_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_RANGE                   12:11
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_VREG10V_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_RANGE                  10:10
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLREFE_MISC1_0_PLLREFE_BG_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0                        _MK_ADDR_CONST(0x421000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_PLL_REF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0_BOND_OUT_PLLREFE_OUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_BASE_0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0                 _MK_ADDR_CONST(0x430000)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_READ_MASK                       _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_FREQ_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SHIFT                        _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_DEFAULT                      _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_BASE_0_PLLC2_DIVM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0                       _MK_ADDR_CONST(0x430004)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_RESET_VAL                     _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_RESET_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_READ_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_WRITE_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SHIFT                     _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_RESET_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SW_DEFAULT                      _MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_EXT_FRU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_PTS_FO                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_0_0_PLLC2_LOOP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0                       _MK_ADDR_CONST(0x430008)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_RESET_VAL                     _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_RESET_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_READ_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_WRITE_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_OFF                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_IDDQ_ON                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_EXT_SUBINT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_1_0_PLLC2_DIVN_FRAC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0                       _MK_ADDR_CONST(0x43000c)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_RESET_VAL                     _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_RESET_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_READ_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_PLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_DIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_2_0_PLLC2_FLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0                       _MK_ADDR_CONST(0x430010)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_RESET_VAL                     _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_RESET_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_READ_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_VREG10V_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_LDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_DEFAULT                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_3_0_PLLC2_PLL_LD_TOL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC2_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0                       _MK_ADDR_CONST(0x430014)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_RESET_VAL                     _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_SEL_IREF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SHIFT                     _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_KP_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC2_MISC_4_0_PLLC2_FRAC_STEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_BASE_0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0                 _MK_ADDR_CONST(0x440000)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_READ_MASK                       _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_FREQ_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SHIFT                        _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_DEFAULT                      _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_BASE_0_PLLC3_DIVM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_0_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0                       _MK_ADDR_CONST(0x440004)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_RESET_VAL                     _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_RESET_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_READ_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_WRITE_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SHIFT                     _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_RESET_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SW_DEFAULT                      _MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_EXT_FRU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_PTS_FO                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_0_0_PLLC3_LOOP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_1_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0                       _MK_ADDR_CONST(0x440008)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_RESET_VAL                     _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_RESET_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_READ_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_WRITE_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_OFF                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_IDDQ_ON                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_EXT_SUBINT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_1_0_PLLC3_DIVN_FRAC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_2_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0                       _MK_ADDR_CONST(0x44000c)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_RESET_VAL                     _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_RESET_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_READ_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_PLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_DIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_2_0_PLLC3_FLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_3_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0                       _MK_ADDR_CONST(0x440010)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_RESET_VAL                     _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_RESET_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_READ_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_VREG10V_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_LDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_DEFAULT                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_3_0_PLLC3_PLL_LD_TOL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC3_MISC_4_0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0                       _MK_ADDR_CONST(0x440014)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_RESET_VAL                     _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_SEL_IREF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SHIFT                     _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_KP_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC3_MISC_4_0_PLLC3_FRAC_STEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDP_BASE_0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0                 _MK_ADDR_CONST(0x450000)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x41401)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x181c00)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xf8ff00)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_READ_MASK                       _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_FREQLOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_REF_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_LOCK_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SHIFT                        _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SW_DEFAULT                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_DEFAULT                      _MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SW_DEFAULT                   _MK_MASK_CONST(0x1c)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_NDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_BASE_0_PLLDP_MDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDP_MISC_0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0                 _MK_ADDR_CONST(0x450004)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_RESET_VAL                       _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_RESET_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_READ_MASK                       _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_WRITE_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_EN_LCKDET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KCP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_KVCO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLDP_MISC_0_PLLDP_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)


// Register CLK_RST_CONTROLLER_PLLDP_MISC1_0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0                        _MK_ADDR_CONST(0x450008)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_RESET_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_READ_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_WRITE_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SHIFT                       _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG14V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SHIFT                       _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_VREG10V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_MISC1_0_PLLDP_BG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0                       _MK_ADDR_CONST(0x45000c)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SDM_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_SSC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_EN_DITHER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CFG_0_PLLDP_SDM_TEST_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0                     _MK_ADDR_CONST(0x450010)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0xf400f0da)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SW_DEFAULT                        _MK_MASK_CONST(0xf400)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SW_DEFAULT                        _MK_MASK_CONST(0xf0da)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0_PLLDP_SDM_SSC_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)


// Register CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0                     _MK_ADDR_CONST(0x450014)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x2004f400)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SW_DEFAULT                       _MK_MASK_CONST(0x2004)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_SSC_STEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SW_DEFAULT                    _MK_MASK_CONST(0xf400)
#define CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0_PLLDP_SDM_DIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0                  _MK_ADDR_CONST(0x460000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0_CLK_ENB_PLLC4_OUT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0                      _MK_ADDR_CONST(0x460004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0_SET_CLK_ENB_PLLC4_OUT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0                      _MK_ADDR_CONST(0x460008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0_CLR_CLK_ENB_PLLC4_OUT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLC4_BASE_0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0                 _MK_ADDR_CONST(0x46000c)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_RESET_VAL                       _MK_MASK_CONST(0xc2302)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe7ffffff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_FREQLOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_REF_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_LOCK_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SHIFT                        _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_RANGE                 17:16
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_DEFAULT                      _MK_MASK_CONST(0x23)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_BASE_0_PLLC4_DIVM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC4_MISC_0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0                 _MK_ADDR_CONST(0x460010)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_RESET_VAL                       _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_RESET_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_READ_MASK                       _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_WRITE_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_EN_LCKDET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KCP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_KVCO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC_0_PLLC4_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC4_MISC1_0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0                        _MK_ADDR_CONST(0x460014)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_RESET_MASK                     _MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_READ_MASK                      _MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_WRITE_MASK                     _MK_MASK_CONST(0x1ff80)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_RANGE                    16:15
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_OUT1                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_OUT2                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_CLK_SEL_PLLC4_VCO_DIV2                   _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SHIFT                       _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG14V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SHIFT                       _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_VREG10V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_BG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_RANGE                 9:9
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_RANGE                       8:8
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_STOP_SYNCMUX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_RANGE                   7:7
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_MISC1_0_PLLC4_SYNCMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0                       _MK_ADDR_CONST(0x460018)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SDM_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_SSC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_EN_DITHER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CFG_0_PLLC4_SDM_TEST_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0                     _MK_ADDR_CONST(0x46001c)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0_PLLC4_SDM_SSC_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0                     _MK_ADDR_CONST(0x460020)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_SSC_STEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0_PLLC4_SDM_DIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 4587556 [0x460024]

// Reserved address 4587560 [0x460028]

// Reserved address 4587564 [0x46002c]

// Reserved address 4587568 [0x460030]

// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0                  _MK_ADDR_CONST(0x461000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0_BOND_OUT_PLLC4_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0                       _MK_ADDR_CONST(0x470000)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_RESET_VAL                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_SS_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_PADCTL_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_DEV_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_0_SWR_XUSB_HOST_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0                   _MK_ADDR_CONST(0x470004)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_RESET_VAL                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_SS_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_PADCTL_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_DEV_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0_SET_SWR_XUSB_HOST_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0                   _MK_ADDR_CONST(0x470008)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_RESET_VAL                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_SS_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_PADCTL_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_DEV_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0_CLR_SWR_XUSB_HOST_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0                   _MK_ADDR_CONST(0x471000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SS_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEV_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0_CLK_ENB_XUSB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0                       _MK_ADDR_CONST(0x471004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SS_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEV_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0_SET_CLK_ENB_XUSB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0                       _MK_ADDR_CONST(0x471008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SS_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_RANGE                   2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEV_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0_CLR_CLK_ENB_XUSB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0                   _MK_ADDR_CONST(0x472000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_RANGE                    3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_RANGE                  2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_HOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0_BOND_OUT_XUSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0                  _MK_ADDR_CONST(0x473000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_CLK_M                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_SRC_PLLREFE_OUT                       _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0_XUSB_CORE_HOST_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0                     _MK_ADDR_CONST(0x473004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_CLK_M                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_SRC_PLLREFE_OUT                     _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0_XUSB_FALCON_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0                 _MK_ADDR_CONST(0x473008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_CLK_M                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_FO_48M                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_SRC_HSIC_480                        _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0_XUSB_FS_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0                   _MK_ADDR_CONST(0x47300c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_CLK_M                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_SRC_PLLREFE_OUT                 _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0_XUSB_CORE_DEV_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0                 _MK_ADDR_CONST(0x473010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_RESET_VAL                       _MK_MASK_CONST(0x4000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_RESET_MASK                      _MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x60000006)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_READ_MASK                       _MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_WRITE_MASK                      _MK_MASK_CONST(0xe70000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_CLK_M                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_PLLREFE_OUT                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_CLK_S                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_SRC_HSIC_480                        _MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_RANGE                     26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_HSICP_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_RANGE                 25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_HS_CLK_BYPASS_SWITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SHIFT                 _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_RANGE                 24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_BYPASS_SWITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0_XUSB_SS_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)


// Register CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0                     _MK_ADDR_CONST(0x474000)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0_CLK_SPARE_REG_XUSB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 4718592 [0x480000]

// Reserved address 4784128 [0x490000]

// Reserved address 4849664 [0x4a0000]

// Register CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0                  _MK_ADDR_CONST(0x4b0000)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0_SWR_DSIPADCTL_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0                      _MK_ADDR_CONST(0x4b0004)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0_SET_SWR_DSIPADCTL_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0                      _MK_ADDR_CONST(0x4b0008)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0_CLR_SWR_DSIPADCTL_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSI_0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0                        _MK_ADDR_CONST(0x4b000c)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_0_SWR_DSI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0                    _MK_ADDR_CONST(0x4b0010)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0_SET_SWR_DSI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0                    _MK_ADDR_CONST(0x4b0014)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0_CLR_SWR_DSI_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0                   _MK_ADDR_CONST(0x4b0018)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0_SWR_MIPI_CAL_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0                       _MK_ADDR_CONST(0x4b001c)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0_SET_SWR_MIPI_CAL_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0                       _MK_ADDR_CONST(0x4b0020)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0_CLR_SWR_MIPI_CAL_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0                    _MK_ADDR_CONST(0x4b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSIA_LP_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0_CLK_ENB_DSI_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0                        _MK_ADDR_CONST(0x4b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSIA_LP_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0_SET_CLK_ENB_DSI_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0                        _MK_ADDR_CONST(0x4b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSIA_LP_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0_CLR_CLK_ENB_DSI_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0                       _MK_ADDR_CONST(0x4b100c)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0_CLK_ENB_MIPI_CAL_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0                   _MK_ADDR_CONST(0x4b1010)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0_SET_CLK_ENB_MIPI_CAL_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0                   _MK_ADDR_CONST(0x4b1014)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0_CLR_CLK_ENB_MIPI_CAL_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0                    _MK_ADDR_CONST(0x4b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSIA_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0_BOND_OUT_DSI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0                       _MK_ADDR_CONST(0x4b2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0_BOND_OUT_MIPI_CAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0                 _MK_ADDR_CONST(0x4b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0_DSIA_LP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIB_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0                       _MK_ADDR_CONST(0x4c0000)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_0_SWR_DSIB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0                   _MK_ADDR_CONST(0x4c0004)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0_SET_SWR_DSIB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0                   _MK_ADDR_CONST(0x4c0008)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0_CLR_SWR_DSIB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0                   _MK_ADDR_CONST(0x4c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0_CLK_ENB_DSIB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0                       _MK_ADDR_CONST(0x4c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0_SET_CLK_ENB_DSIB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0                       _MK_ADDR_CONST(0x4c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0_CLR_CLK_ENB_DSIB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0                   _MK_ADDR_CONST(0x4c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_LP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0_BOND_OUT_DSIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0                 _MK_ADDR_CONST(0x4c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0_DSIB_LP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0                    _MK_ADDR_CONST(0x4d0000)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0_SWR_ENTROPY_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0                        _MK_ADDR_CONST(0x4d0004)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0_SET_SWR_ENTROPY_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0                        _MK_ADDR_CONST(0x4d0008)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0_CLR_SWR_ENTROPY_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0                        _MK_ADDR_CONST(0x4d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0_CLK_ENB_ENTROPY_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0                    _MK_ADDR_CONST(0x4d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0_SET_CLK_ENB_ENTROPY_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0                    _MK_ADDR_CONST(0x4d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0_CLR_CLK_ENB_ENTROPY_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0                        _MK_ADDR_CONST(0x4d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0_BOND_OUT_ENTROPY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0                 _MK_ADDR_CONST(0x4d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_RESET_MASK                      _MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_READ_MASK                       _MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_WRITE_MASK                      _MK_MASK_CONST(0xf00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_RANGE                  28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_RESERVED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0_ENTROPY_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0                       _MK_ADDR_CONST(0x4e0000)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_0_SWR_DVFS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0                   _MK_ADDR_CONST(0x4e0004)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0_SET_SWR_DVFS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0                   _MK_ADDR_CONST(0x4e0008)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0_CLR_SWR_DVFS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0                   _MK_ADDR_CONST(0x4e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0_CLK_ENB_DVFS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0                       _MK_ADDR_CONST(0x4e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0_SET_CLK_ENB_DVFS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0                       _MK_ADDR_CONST(0x4e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0_CLR_CLK_ENB_DVFS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0                   _MK_ADDR_CONST(0x4e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0_BOND_OUT_DVFS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0                        _MK_ADDR_CONST(0x4e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_RESET_VAL                      _MK_MASK_CONST(0xf0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_RESET_MASK                     _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_READ_MASK                      _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_WRITE_MASK                     _MK_MASK_CONST(0xf00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_INIT_ENUM                     OSC_DIV
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_SRC_OSC_DIV                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_RANGE                    28:28
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0_DVFS_REF_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 5177344 [0x4f0000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0                  _MK_ADDR_CONST(0x500000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0_CLK_ENB_DMIC1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0                      _MK_ADDR_CONST(0x500004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0_SET_CLK_ENB_DMIC1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0                      _MK_ADDR_CONST(0x500008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0_CLR_CLK_ENB_DMIC1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0                  _MK_ADDR_CONST(0x501000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0_BOND_OUT_DMIC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0                   _MK_ADDR_CONST(0x502000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0_DMIC1_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0                       _MK_ADDR_CONST(0x503000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0                  _MK_ADDR_CONST(0x510000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0_CLK_ENB_DMIC2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0                      _MK_ADDR_CONST(0x510004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0_SET_CLK_ENB_DMIC2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0                      _MK_ADDR_CONST(0x510008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0_CLR_CLK_ENB_DMIC2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0                  _MK_ADDR_CONST(0x511000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0_BOND_OUT_DMIC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0                   _MK_ADDR_CONST(0x512000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0_DMIC2_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0                       _MK_ADDR_CONST(0x513000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0                   _MK_ADDR_CONST(0x520000)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0_SWR_AUD_MCLK_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0                       _MK_ADDR_CONST(0x520004)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0_SET_SWR_AUD_MCLK_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0                       _MK_ADDR_CONST(0x520008)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0_CLR_SWR_AUD_MCLK_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0                       _MK_ADDR_CONST(0x521000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0_CLK_ENB_AUD_MCLK_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0                   _MK_ADDR_CONST(0x521004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0_SET_CLK_ENB_AUD_MCLK_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0                   _MK_ADDR_CONST(0x521008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0_CLR_CLK_ENB_AUD_MCLK_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0                       _MK_ADDR_CONST(0x522000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0_BOND_OUT_AUD_MCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0                        _MK_ADDR_CONST(0x523000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0_AUD_MCLK_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0                       _MK_ADDR_CONST(0x530000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0_SWR_I2C6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0                   _MK_ADDR_CONST(0x530004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0_SET_SWR_I2C6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0                   _MK_ADDR_CONST(0x530008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0_CLR_SWR_I2C6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0                   _MK_ADDR_CONST(0x531000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0_CLK_ENB_I2C6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0                       _MK_ADDR_CONST(0x531004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0_SET_CLK_ENB_I2C6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0                       _MK_ADDR_CONST(0x531008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0_CLR_CLK_ENB_I2C6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0                   _MK_ADDR_CONST(0x532000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0_BOND_OUT_I2C6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0                    _MK_ADDR_CONST(0x533000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 5505024 [0x540000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0                      _MK_ADDR_CONST(0x550000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0                  _MK_ADDR_CONST(0x550004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0                  _MK_ADDR_CONST(0x550008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0                      _MK_ADDR_CONST(0x551000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0_BOND_OUT_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0                       _MK_ADDR_CONST(0x552000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_INIT_ENUM                   PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0                        _MK_ADDR_CONST(0x560000)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_0_SWR_VIC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0                    _MK_ADDR_CONST(0x560004)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0_SET_SWR_VIC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0                    _MK_ADDR_CONST(0x560008)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0_CLR_SWR_VIC_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0                    _MK_ADDR_CONST(0x561000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0_CLK_ENB_VIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0                        _MK_ADDR_CONST(0x561004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0_SET_CLK_ENB_VIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0                        _MK_ADDR_CONST(0x561008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0_CLR_CLK_ENB_VIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0                    _MK_ADDR_CONST(0x562000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0_BOND_OUT_VIC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0                     _MK_ADDR_CONST(0x563000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_RESET_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_READ_MASK                   _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_WRITE_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC2_OUT0                      _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_PLLC3_OUT0                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_SRC_DFLL_VIC                        _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_RANGE                      15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_IDLE_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0_VIC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x563004)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0_SUPER_VIC_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0                      _MK_ADDR_CONST(0x564000)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_RANGE                      7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_VIC_0_CLK_SPARE_REG_VIC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 5652484 [0x564004]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0                        _MK_ADDR_CONST(0x570000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0                    _MK_ADDR_CONST(0x570004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0_SET_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0                    _MK_ADDR_CONST(0x570008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0_CLR_CLK_ENB_SDMMC_LEGACY_TM_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0                        _MK_ADDR_CONST(0x571000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0_BOND_OUT_SDMMC_LEGACY_TM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0                 _MK_ADDR_CONST(0x572000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x42)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_INIT_ENUM                       PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x42)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0_SDMMC_LEGACY_TM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0                      _MK_ADDR_CONST(0x580000)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_0_SWR_NVDEC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0                  _MK_ADDR_CONST(0x580004)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0_SET_SWR_NVDEC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0                  _MK_ADDR_CONST(0x580008)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0_CLR_SWR_NVDEC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0                  _MK_ADDR_CONST(0x581000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0_CLK_ENB_NVDEC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0                      _MK_ADDR_CONST(0x581004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0_SET_CLK_ENB_NVDEC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0                      _MK_ADDR_CONST(0x581008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0_CLR_CLK_ENB_NVDEC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0                  _MK_ADDR_CONST(0x582000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0_BOND_OUT_NVDEC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0                   _MK_ADDR_CONST(0x583000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC2_OUT0                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_PLLC3_OUT0                  _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_DFLL_NVDEC                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0_NVDEC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0                    _MK_ADDR_CONST(0x583004)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_RESET_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_READ_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_WRITE_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0_SUPER_NVDEC_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0                    _MK_ADDR_CONST(0x584000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0_CLK_SPARE_REG_NVDEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0                      _MK_ADDR_CONST(0x590000)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_0_SWR_NVJPG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0                  _MK_ADDR_CONST(0x590004)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0_SET_SWR_NVJPG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0                  _MK_ADDR_CONST(0x590008)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0_CLR_SWR_NVJPG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0                  _MK_ADDR_CONST(0x591000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0_CLK_ENB_NVJPG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0                      _MK_ADDR_CONST(0x591004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0_SET_CLK_ENB_NVJPG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0                      _MK_ADDR_CONST(0x591008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0_CLR_CLK_ENB_NVJPG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0                  _MK_ADDR_CONST(0x592000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0_BOND_OUT_NVJPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0                   _MK_ADDR_CONST(0x593000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC2_OUT0                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_PLLC3_OUT0                  _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_DFLL_NVJPG                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0_NVJPG_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0                    _MK_ADDR_CONST(0x593004)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_RESET_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_READ_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_WRITE_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0_SUPER_NVJPG_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0                      _MK_ADDR_CONST(0x5a0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_0_SWR_NVENC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0                  _MK_ADDR_CONST(0x5a0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0_SET_SWR_NVENC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0                  _MK_ADDR_CONST(0x5a0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0_CLR_SWR_NVENC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0                  _MK_ADDR_CONST(0x5a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0_CLK_ENB_NVENC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0                      _MK_ADDR_CONST(0x5a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0_SET_CLK_ENB_NVENC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0                      _MK_ADDR_CONST(0x5a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0_CLR_CLK_ENB_NVENC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0                  _MK_ADDR_CONST(0x5a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0_BOND_OUT_NVENC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0                   _MK_ADDR_CONST(0x5a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC2_OUT0                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_PLLC3_OUT0                  _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_DFLL_NVENC                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0_NVENC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0                    _MK_ADDR_CONST(0x5a3004)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_RESET_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_READ_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_WRITE_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0_SUPER_NVENC_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0                    _MK_ADDR_CONST(0x5a4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0_CLK_SPARE_REG_NVENC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_BASE_0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0                 _MK_ADDR_CONST(0x5b0000)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_READ_MASK                       _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_RANGE                   27:27
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_FREQ_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SHIFT                        _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_RANGE                        26:26
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_RANGE                        24:20
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SHIFT                        _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_RANGE                        17:10
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_DEFAULT                      _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_BASE_0_PLLA1_DIVM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_OUT1_0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0                 _MK_ADDR_CONST(0x5b0004)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_RESET_VAL                       _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_RESET_MASK                      _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_READ_MASK                       _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff03)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_RANGE                        16:16
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_DIV_BYP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RATIO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_RANGE                  1:1
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_CLKEN_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_INIT_ENUM                       RESET_ENABLE
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RESET_ENABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_OUT1_0_PLLA1_OUT1_RSTN_RESET_DISABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_0_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0                       _MK_ADDR_CONST(0x5b0008)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_RESET_VAL                     _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_RESET_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x80000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xffff0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_READ_MASK                     _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_WRITE_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SHIFT                     _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_RANGE                     30:30
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_RESET_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_RANGE                   19:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SW_DEFAULT                      _MK_MASK_CONST(0x8000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_EXT_FRU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_RANGE                       3:3
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_PTS_FO                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_RANGE                 1:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_0_0_PLLA1_LOOP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_1_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0                       _MK_ADDR_CONST(0x5b000c)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_RESET_VAL                     _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_RESET_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_READ_MASK                     _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_WRITE_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_OFF                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_IDDQ_ON                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_RANGE                        19:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_EXT_SUBINT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_1_0_PLLA1_DIVN_FRAC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_2_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0                       _MK_ADDR_CONST(0x5b0010)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_RESET_VAL                     _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_RESET_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0xf00)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_READ_MASK                     _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_RANGE                        31:24
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_RANGE                  23:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_PLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SW_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_LD_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0xff)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_RANGE                   4:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_DIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_RANGE                  2:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_DEFAULT                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_2_0_PLLA1_FLL_FRUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_3_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0                       _MK_ADDR_CONST(0x5b0014)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_RESET_VAL                     _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_RESET_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_READ_MASK                     _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_RANGE                      25:24
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_VREG10V_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_RANGE                     23:8
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_RANGE                      5:4
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_LDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_DEFAULT                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_3_0_PLLA1_PLL_LD_TOL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLA1_MISC_4_0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0                       _MK_ADDR_CONST(0x5b0018)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_RESET_VAL                     _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_SEL_IREF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SHIFT                     _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_RANGE                     27:25
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_RANGE                     24:22
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_RANGE                     21:19
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_KP_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_RANGE                   18:16
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLA1_MISC_4_0_PLLA1_FRAC_STEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0                       _MK_ADDR_CONST(0x5c0000)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_0_SWR_QSPI_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0                   _MK_ADDR_CONST(0x5c0004)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0_SET_SWR_QSPI_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0                   _MK_ADDR_CONST(0x5c0008)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0_CLR_SWR_QSPI_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0                   _MK_ADDR_CONST(0x5c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0_CLK_ENB_QSPI_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0                       _MK_ADDR_CONST(0x5c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0_SET_CLK_ENB_QSPI_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0                       _MK_ADDR_CONST(0x5c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0_CLR_CLK_ENB_QSPI_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0                   _MK_ADDR_CONST(0x5c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0_BOND_OUT_QSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0                    _MK_ADDR_CONST(0x5c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_RESET_MASK                         _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_READ_MASK                  _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_WRITE_MASK                         _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_PLLC4_MUXED                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_RANGE                    8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIV2_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0_QSPI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0                     _MK_ADDR_CONST(0x5d0000)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0_SWR_VI_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0                 _MK_ADDR_CONST(0x5d0004)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0_SET_SWR_VI_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0                 _MK_ADDR_CONST(0x5d0008)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0_CLR_SWR_VI_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0                 _MK_ADDR_CONST(0x5d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0_CLK_ENB_VI_I2C_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0                     _MK_ADDR_CONST(0x5d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0_SET_CLK_ENB_VI_I2C_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0                     _MK_ADDR_CONST(0x5d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0_CLR_CLK_ENB_VI_I2C_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0                 _MK_ADDR_CONST(0x5d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0_BOND_OUT_VI_I2C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0                  _MK_ADDR_CONST(0x5d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_RESET_MASK                       _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_WRITE_MASK                       _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_RANGE                 15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0_VI_I2C_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0                  _MK_ADDR_CONST(0x5e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_USB2_TRK_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0_CLK_ENB_HSIC_TRK_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0                      _MK_ADDR_CONST(0x5e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_USB2_TRK_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0_SET_CLK_ENB_HSIC_TRK_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0                      _MK_ADDR_CONST(0x5e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_USB2_TRK_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_RANGE                   0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0_CLR_CLK_ENB_HSIC_TRK_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0                  _MK_ADDR_CONST(0x5e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_USB2_TRK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_RANGE                  0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0_BOND_OUT_HSIC_TRK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0                   _MK_ADDR_CONST(0x5e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0_USB2_HSIC_TRK_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xff)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0                     _MK_ADDR_CONST(0x5f0000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_RESET_VAL                   _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_RESET_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_READ_MASK                   _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_RANGE                  8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_CE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0_PEX_USB_PAD_RX_BYP_REFCLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0                   _MK_ADDR_CONST(0x5f0004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_RESET_VAL                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_WRITE_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_CE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0_PEX_USB_PAD_PLL0_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0                   _MK_ADDR_CONST(0x5f0008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_RESET_VAL                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_WRITE_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_RANGE                        8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_CE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0_PEX_USB_PAD_PLL1_MGMT_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0                   _MK_ADDR_CONST(0x600000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0_CLK_ENB_MAUD_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0                       _MK_ADDR_CONST(0x600004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0_SET_CLK_ENB_MAUD_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0                       _MK_ADDR_CONST(0x600008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0_CLR_CLK_ENB_MAUD_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0                   _MK_ADDR_CONST(0x601000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0_BOND_OUT_MAUD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0                    _MK_ADDR_CONST(0x602000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0_MAUD_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0                      _MK_ADDR_CONST(0x610000)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_0_SWR_TSECB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0                  _MK_ADDR_CONST(0x610004)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0_SET_SWR_TSECB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0                  _MK_ADDR_CONST(0x610008)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0_CLR_SWR_TSECB_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0                  _MK_ADDR_CONST(0x611000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0_CLK_ENB_TSECB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0                      _MK_ADDR_CONST(0x611004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0_SET_CLK_ENB_TSECB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0                      _MK_ADDR_CONST(0x611008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0_CLR_CLK_ENB_TSECB_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0                  _MK_ADDR_CONST(0x612000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0_BOND_OUT_TSECB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0                   _MK_ADDR_CONST(0x613000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC2_OUT0                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_PLLC3_OUT0                  _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_DFLL_TSECB                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0_TSECB_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0                    _MK_ADDR_CONST(0x613004)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SCR                        0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_RESET_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_READ_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_WRITE_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0_SUPER_TSECB_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0                       _MK_ADDR_CONST(0x620000)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_RESET_VAL                     _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_RESET_MASK                    _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_READ_MASK                     _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_WRITE_MASK                    _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPNEON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPSCU_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPWDT_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPDBG_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPPERIPH_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSPINTF_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_0_SWR_ADSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0                   _MK_ADDR_CONST(0x620004)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_RESET_VAL                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPNEON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPSCU_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPWDT_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPDBG_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPPERIPH_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSPINTF_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0_SET_SWR_ADSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0                   _MK_ADDR_CONST(0x620008)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_RANGE                        6:6
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPNEON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_RANGE                 5:5
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPSCU_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_RANGE                 4:4
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPWDT_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_RANGE                 3:3
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPDBG_RST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_RANGE                      2:2
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPPERIPH_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSPINTF_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0_CLR_SWR_ADSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0                   _MK_ADDR_CONST(0x621000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_RESET_MASK                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_READ_MASK                         _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_WRITE_MASK                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSPNEON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0_CLK_ENB_ADSP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0                       _MK_ADDR_CONST(0x621004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_RESET_MASK                    _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_READ_MASK                     _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSPNEON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0_SET_CLK_ENB_ADSP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0                       _MK_ADDR_CONST(0x621008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_READ_MASK                     _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSPNEON_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0_CLR_CLK_ENB_ADSP_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0                   _MK_ADDR_CONST(0x622000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_RESET_MASK                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_READ_MASK                         _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_WRITE_MASK                        _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSPNEON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0_BOND_OUT_ADSP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x623000)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SCR                      0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10004444)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xfc00ffff)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_RANGE                 31:28
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_STDBY                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_IDLE                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_RUN                   _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_IRQ                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_ADSP_STATE_FIQ                   _MK_ENUM_CONST(8)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_RANGE                      27:27
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_RANGE                      26:26
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AUTO_AWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_RANGE                 15:12
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA1_OUT0                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA1_OUT_LJ                  _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_FIQ_SOURCE_PLLA_OUT_LJ                   _MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_RANGE                 11:8
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA1_OUT0                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA1_OUT_LJ                  _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IRQ_SOURCE_PLLA_OUT_LJ                   _MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_RANGE                 7:4
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA1_OUT0                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA1_OUT_LJ                  _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_RUN_SOURCE_PLLA_OUT_LJ                   _MK_ENUM_CONST(15)

#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_RANGE                        3:0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA1_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLP_OUT0                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT0                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_CLK_M                        _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA1_OUT_LJ                 _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0_AWAKEUP_IDLE_SOURCE_PLLA_OUT_LJ                  _MK_ENUM_CONST(15)


// Register CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0                 _MK_ADDR_CONST(0x623004)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SCR                     0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x96ffffff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_RANGE                   28:28
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_INVERT_DCD_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SHIFT                   _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_RANGE                   26:26
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_FIQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_RANGE                   25:25
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIS_FROM_IRQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_RANGE                  23:16
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_ACLK_CLK_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0_SUPER_ADIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 6488064 [0x630000]

// Reserved address 6553600 [0x640000]

// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0                       _MK_ADDR_CONST(0x650000)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_RESET_VAL                     _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_RESET_MASK                    _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_READ_MASK                     _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_WRITE_MASK                    _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_IOBIST_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_CLK_CTL_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L1_TX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_0_SWR_MPHY_L0_TX_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0                   _MK_ADDR_CONST(0x650004)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_RESET_VAL                         _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_RESET_MASK                        _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_READ_MASK                         _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_IOBIST_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_CLK_CTL_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L1_TX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0_SET_SWR_MPHY_L0_TX_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0                   _MK_ADDR_CONST(0x650008)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_READ_MASK                         _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x20010303)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_RANGE                     29:29
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_IOBIST_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_RANGE                    16:16
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_CLK_CTL_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_RANGE                      9:9
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_RANGE                      8:8
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L1_TX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_RX_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0_CLR_SWR_MPHY_L0_TX_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0                   _MK_ADDR_CONST(0x651000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_RESET_MASK                        _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_READ_MASK                         _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_WRITE_MASK                        _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0                       _MK_ADDR_CONST(0x651004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_RESET_MASK                    _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_READ_MASK                     _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_WRITE_MASK                    _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0_SET_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0                       _MK_ADDR_CONST(0x651008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_RESET_MASK                    _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_READ_MASK                     _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_RANGE                 31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_CORE_PLL_FIXED_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_RANGE                    30:30
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_TX_1MHZ_REF_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_RANGE                 29:29
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_IOBIST_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_RANGE                      15:15
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L1_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_ANA_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_RANGE                 4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_LS_3XBIT_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_RANGE                     3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_TX_SYMB_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_LS_BIT_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0_CLR_CLK_ENB_MPHY_L0_RX_SYMB_ENABLE                    _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0                   _MK_ADDR_CONST(0x652000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_RESET_MASK                        _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_READ_MASK                         _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_WRITE_MASK                        _MK_MASK_CONST(0xe000809b)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_RANGE                        31:31
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_CORE_PLL_FIXED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_RANGE                   30:30
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_TX_1MHZ_REF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_RANGE                        29:29
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_RANGE                     15:15
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L1_RX_ANA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_ANA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_RANGE                        4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_LS_3XBIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_RANGE                    3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_TX_SYMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_LS_BIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_RANGE                    0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0_BOND_OUT_MPHY_L0_RX_SYMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0                     _MK_ADDR_CONST(0x653000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_RESET_VAL                   _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0_MPHY_CORE_PLL_FIXED_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0                        _MK_ADDR_CONST(0x653004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_RESET_VAL                      _MK_MASK_CONST(0x4a)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x4a)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0_MPHY_TX_1MHZ_REF_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0                     _MK_ADDR_CONST(0x653008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0_MPHY_IOBIST_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0                      _MK_ADDR_CONST(0x65300c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_RESET_VAL                    _MK_MASK_CONST(0x26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0_MPHY_L0_RX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0                      _MK_ADDR_CONST(0x653010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_RESET_VAL                    _MK_MASK_CONST(0x76)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x76)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0_MPHY_L0_TX_LS_SYMB_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0                      _MK_ADDR_CONST(0x654000)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_RANGE                     0:0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_MPHY_MISC_0_MPHY_FORCE_LS_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0                     _MK_ADDR_CONST(0x655000)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0_CLK_SPARE_REG_MPHY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_BASE_0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0                      _MK_ADDR_CONST(0x660000)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_RESET_VAL                    _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_RESET_MASK                   _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_READ_MASK                    _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_WRITE_MASK                   _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_INIT_ENUM                   REF_ENABLE
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_FREQ_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SHIFT                  _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_RANGE                  24:20
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_RANGE                  17:10
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_DEFAULT                        _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_RANGE                  7:0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_DEFAULT                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_BASE_0_PLLNVCSI_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0                    _MK_ADDR_CONST(0x660004)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_RESET_VAL                  _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_RESET_MASK                         _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_READ_MASK                  _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_WRITE_MASK                         _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SHIFT                       _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_RANGE                       30:30
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_RESET_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_RANGE                     19:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_EXT_FRU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_RANGE                 3:3
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_RANGE                   1:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0_PLLNVCSI_LOOP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0                    _MK_ADDR_CONST(0x660008)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_RESET_VAL                  _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_RESET_MASK                         _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_READ_MASK                  _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_WRITE_MASK                         _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_RANGE                  19:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_EXT_SUBINT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0_PLLNVCSI_DIVN_FRAC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0                    _MK_ADDR_CONST(0x66000c)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_RESET_VAL                  _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_RESET_MASK                         _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_READ_MASK                  _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_RANGE                  31:24
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_RANGE                    23:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_PLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_RANGE                  15:8
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_LD_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_RANGE                     4:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_DIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_RANGE                    2:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_DEFAULT                  _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0_PLLNVCSI_FLL_FRUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0                    _MK_ADDR_CONST(0x660010)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_RESET_VAL                  _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_RESET_MASK                         _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_READ_MASK                  _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_WRITE_MASK                         _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_RANGE                        25:24
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_VREG10V_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_RANGE                       23:8
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_RANGE                        5:4
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_LDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_RANGE                  3:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_DEFAULT                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0_PLLNVCSI_PLL_LD_TOL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0                    _MK_ADDR_CONST(0x660014)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_RESET_VAL                  _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_RESET_MASK                         _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_READ_MASK                  _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_WRITE_MASK                         _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_SEL_IREF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SHIFT                       _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_RANGE                       27:25
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SHIFT                       _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_RANGE                       24:22
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SHIFT                       _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_RANGE                       21:19
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_KP_STEP_TIMER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_RANGE                     18:16
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0_PLLNVCSI_FRAC_STEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0                    _MK_ADDR_CONST(0x670000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_RESET_VAL                  _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_RESET_MASK                         _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_READ_MASK                  _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_WRITE_MASK                         _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_BYPASS_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_REF_ENABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_REF_DIS_REF_DISABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_FREQ_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_LOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_DEFAULT                    _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_DEFAULT                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0_PLLDISPHUB_DIVM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0                  _MK_ADDR_CONST(0x670004)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_RESET_VAL                        _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_RESET_MASK                       _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_READ_MASK                        _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_WRITE_MASK                       _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_RESET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_EXT_FRU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_PTS_FO                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0_PLLDISPHUB_LOOP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0                  _MK_ADDR_CONST(0x670008)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_RESET_VAL                        _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_RESET_MASK                       _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_READ_MASK                        _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_WRITE_MASK                       _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_IDDQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_EXT_SUBINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0_PLLDISPHUB_DIVN_FRAC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0                  _MK_ADDR_CONST(0x67000c)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_RESET_VAL                        _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_RESET_MASK                       _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_READ_MASK                        _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_PLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0_PLLDISPHUB_FLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0                  _MK_ADDR_CONST(0x670010)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_RESET_VAL                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_READ_MASK                        _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_VREG10V_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_LDIV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_DEFAULT                    _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0_PLLDISPHUB_PLL_LD_TOL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0                  _MK_ADDR_CONST(0x670014)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SCR                      0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_RESET_VAL                        _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_RESET_MASK                       _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_READ_MASK                        _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_WRITE_MASK                       _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_SEL_IREF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_KP_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0_PLLDISPHUB_FRAC_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_BASE_0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0                 _MK_ADDR_CONST(0x680000)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_RESET_VAL                       _MK_MASK_CONST(0x41401)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_RESET_MASK                      _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_READ_MASK                       _MK_MASK_CONST(0xfffdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_WRITE_MASK                      _MK_MASK_CONST(0xe7fdffff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_RANGE                      31:31
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_BYPASS_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_RANGE                      30:30
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_RANGE                     29:29
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_INIT_ENUM                 REF_ENABLE
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_REF_ENABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_DIS_REF_DISABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_RANGE                    28:28
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_FREQLOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_RANGE                        27:27
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_REF_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_RANGE                       24:24
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_LOCK_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SHIFT                        _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_RANGE                        23:19
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SHIFT                        _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_RANGE                        18:18
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_OFF                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_IDDQ_ON                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_RANGE                 16:16
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_PTS_FO                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_RANGE                        15:8
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_DEFAULT                      _MK_MASK_CONST(0x14)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_NDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_RANGE                        7:0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_BASE_0_PLLD3_MDIV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_MISC_0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0                 _MK_ADDR_CONST(0x680004)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SCR                     0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_RESET_VAL                       _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_RESET_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_READ_MASK                       _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_WRITE_MASK                      _MK_MASK_CONST(0x47ffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_EN_LCKDET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SHIFT                 _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_RANGE                 26:25
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KCP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_RANGE                        24:24
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_KVCO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_FIELD                       _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_RANGE                       23:0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC_0_PLLD3_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_MISC1_0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0                        _MK_ADDR_CONST(0x680008)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_RESET_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_READ_MASK                      _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_WRITE_MASK                     _MK_MASK_CONST(0x7c00)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SHIFT                       _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_RANGE                       14:13
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG14V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SHIFT                       _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_RANGE                       12:11
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_VREG10V_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_RANGE                      10:10
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_MISC1_0_PLLD3_BG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0                       _MK_ADDR_CONST(0x68000c)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SDM_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_SSC_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_RANGE                        29:29
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_RANGE                 28:28
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_EN_DITHER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_RANGE                      25:23
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CFG_0_PLLD3_SDM_TEST_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0                     _MK_ADDR_CONST(0x680010)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_RANGE                     31:16
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0_PLLD3_SDM_SSC_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0                     _MK_ADDR_CONST(0x680014)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_RANGE                    31:16
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_SSC_STEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0_PLLD3_SDM_DIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0                        _MK_ADDR_CONST(0x690000)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SCR                    0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_RESET_VAL                      _MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_RESET_MASK                     _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_READ_MASK                      _MK_MASK_CONST(0xedf0ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_WRITE_MASK                     _MK_MASK_CONST(0xe1f0ffff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_RANGE                 31:31
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_BYPASSPLL_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_REF_ENABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_REF_DIS_REF_DISABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_RANGE                      27:27
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_LOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SHIFT                 _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_RANGE                 26:26
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_FREQ_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_DEFAULT                    _MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_DEFAULT                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_BASE_0_PLLMSB_DIVM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0                       _MK_ADDR_CONST(0x690004)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_FIELD                    _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_RANGE                    23:0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC1_0_PLLMSB_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_MISC2_0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0                       _MK_ADDR_CONST(0x690008)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_RESET_VAL                     _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_RESET_MASK                    _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_READ_MASK                     _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff3f)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_RANGE                     17:16
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG14V_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_RANGE                     15:14
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VREG10V_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_RANGE                 13:13
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_OVERRIDE_SYNCMUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_RANGE                  12:12
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_VCO_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_RANGE                    11:11
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_SYNC_MUX_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_RANGE                       10:10
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_ENABLE_SW_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_RANGE                      9:8
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_PTS_FO                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_RANGE                     5:5
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_RANGE                        4:4
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_EN_LCKDET_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_RANGE                    3:3
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_LOCK_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_RANGE                      2:1
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KCP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_MISC2_0_PLLMSB_KVCO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSBB_BASE_0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0                       _MK_ADDR_CONST(0x69000c)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SCR                   0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_RESET_VAL                     _MK_MASK_CONST(0x2a02)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_RESET_MASK                    _MK_MASK_CONST(0x4df0ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_READ_MASK                     _MK_MASK_CONST(0x4df0ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_WRITE_MASK                    _MK_MASK_CONST(0x41f0ffff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SHIFT                  _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SHIFT                       _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_RANGE                       26:26
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_FREQ_LOCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_RANGE                    24:20
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_DEFAULT                  _MK_MASK_CONST(0x2a)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_RANGE                    7:0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_DEFAULT                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_BASE_0_PLLMSBB_DIVM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSBB_MISC1_0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0                      _MK_ADDR_CONST(0x690010)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_RESET_VAL                    _MK_MASK_CONST(0x1000000)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_RESET_MASK                   _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_READ_MASK                    _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_WRITE_MASK                   _MK_MASK_CONST(0x7ffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_RANGE                  26:26
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_LOCK_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_RANGE                   25:25
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_RANGE                      24:24
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_EN_LCKDET_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_FIELD                  _MK_FIELD_CONST(0xffffff, CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_RANGE                  23:0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_DEFAULT_MASK                   _MK_MASK_CONST(0xffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_MISC1_0_PLLMSBB_SETUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0                      _MK_ADDR_CONST(0x690014)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_RESET_VAL                    _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_READ_MASK                    _MK_MASK_CONST(0xfb800000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_RANGE                  31:31
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SDM_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SHIFT                  _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_RANGE                  30:30
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_SSC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_RANGE                      29:29
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_RANGE                       28:28
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_EN_DITHER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_RANGE                       27:27
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_RANGE                    25:23
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0_PLLMSB_SDM_TEST_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0                    _MK_ADDR_CONST(0x690018)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_RANGE                   31:16
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_RANGE                   15:0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0_PLLMSB_SDM_SSC_MIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0                    _MK_ADDR_CONST(0x69001c)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_FIELD                  _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_RANGE                  31:16
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_SSC_STEP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0_PLLMSB_SDM_DIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0                     _MK_ADDR_CONST(0x690020)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_RESET_VAL                   _MK_MASK_CONST(0x10000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_RESET_MASK                  _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_READ_MASK                   _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_WRITE_MASK                  _MK_MASK_CONST(0xf8000000)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SDM_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_RANGE                        30:30
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_SSC_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SHIFT                    _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_RANGE                    29:29
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SHIFT                     _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_RANGE                     28:28
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_EN_DITHER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_RANGE                     27:27
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0_PLLMSBB_SDM_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0                   _MK_ADDR_CONST(0x690024)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_RANGE                 31:16
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_RANGE                 15:0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0_PLLMSBB_SDM_SSC_MIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0                   _MK_ADDR_CONST(0x690028)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_FIELD                        _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_RANGE                        31:16
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_SSC_STEP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SHIFT)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_RANGE                     15:0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0_PLLMSBB_SDM_DIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0                    _MK_ADDR_CONST(0x6a0000)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_RESET_VAL                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_RESET_MASK                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_READ_MASK                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_WRITE_MASK                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_JTAG2AXI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_INIT_ENUM                   ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0_SWR_GPCDMA_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0                        _MK_ADDR_CONST(0x6a0004)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_RESET_VAL                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_RESET_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_READ_MASK                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_JTAG2AXI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0_SET_SWR_GPCDMA_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0                        _MK_ADDR_CONST(0x6a0008)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_READ_MASK                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_JTAG2AXI_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_RANGE                       1:1
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0_CLR_SWR_GPCDMA_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0                        _MK_ADDR_CONST(0x6a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0_CLK_ENB_AXI_CBB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0                    _MK_ADDR_CONST(0x6a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0_SET_CLK_ENB_AXI_CBB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0                    _MK_ADDR_CONST(0x6a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0_CLR_CLK_ENB_AXI_CBB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0                        _MK_ADDR_CONST(0x6a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0_BOND_OUT_AXI_CBB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0                 _MK_ADDR_CONST(0x6a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_DFLL_AXI_CBB                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLREFE_OUT                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLC2_OUT0                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_PLLC4_MUXED                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_CLK_M                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_SRC_CLK_S                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0_AXI_CBB_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0                   _MK_ADDR_CONST(0x6a3004)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_RESET_MASK                        _MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_READ_MASK                         _MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0xc000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_RANGE                   30:30
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_OVRD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0_SUPER_AXI_CBB_DIV_SW_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0                   _MK_ADDR_CONST(0x6a3008)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0_SUPER_AXI_CBB_DIV_HW_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0                  _MK_ADDR_CONST(0x6b0000)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SCR                      0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_RESET_MASK                       _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_READ_MASK                        _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_WRITE_MASK                       _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CENTRAL_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x6c0000)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_AON_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0                     _MK_ADDR_CONST(0x6d0000)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SCR                         0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_RESET_VAL                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_RESET_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_READ_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_WRITE_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_PCIE_DIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0                   _MK_ADDR_CONST(0x6e0000)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_RESET_MASK                        _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_READ_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_WRITE_MASK                        _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_ENB_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_CCPLEX_DIV_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x6f0000)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_GPU_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x700000)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_APE_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0                     _MK_ADDR_CONST(0x710000)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SCR                         0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_RESET_VAL                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_RESET_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_READ_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_WRITE_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_BPMP_DIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0                      _MK_ADDR_CONST(0x720000)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SCR                  0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_RESET_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_WRITE_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_RANGE                 15:8
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_SCE_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0                        _MK_ADDR_CONST(0x730000)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_WRITE_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_1_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0                        _MK_ADDR_CONST(0x740000)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_WRITE_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_2_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0                        _MK_ADDR_CONST(0x750000)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_WRITE_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_3_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0                        _MK_ADDR_CONST(0x760000)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_WRITE_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_4_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0                        _MK_ADDR_CONST(0x770000)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SCR                    0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_WRITE_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_RANGE                  31:31
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_ENB_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_RANGE                     15:8
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_RANGE                      7:0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0_SUPER_AXI2APB_5_DIV_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0                   _MK_ADDR_CONST(0x780000)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SCR                       0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_RESET_MASK                        _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_READ_MASK                         _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_WRITE_MASK                        _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_ENB_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_RANGE                   15:8
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_RANGE                    7:0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0_SUPER_AXI_CBB_HOST1X_DIV_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 7929856 [0x790000]

// Reserved address 7995392 [0x7a0000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0                  _MK_ADDR_CONST(0x7b0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0_CLK_ENB_DMIC3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0                      _MK_ADDR_CONST(0x7b0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0_SET_CLK_ENB_DMIC3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0                      _MK_ADDR_CONST(0x7b0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0_CLR_CLK_ENB_DMIC3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0                  _MK_ADDR_CONST(0x7b1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0_BOND_OUT_DMIC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0                   _MK_ADDR_CONST(0x7b2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0_DMIC3_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0                       _MK_ADDR_CONST(0x7b3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0                  _MK_ADDR_CONST(0x7c0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0_CLK_ENB_DMIC4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0                      _MK_ADDR_CONST(0x7c0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0_SET_CLK_ENB_DMIC4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0                      _MK_ADDR_CONST(0x7c0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0_CLR_CLK_ENB_DMIC4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0                  _MK_ADDR_CONST(0x7c1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0_BOND_OUT_DMIC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0                   _MK_ADDR_CONST(0x7c2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0_DMIC4_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0                       _MK_ADDR_CONST(0x7c3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0                  _MK_ADDR_CONST(0x7d0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0_CLK_ENB_DSPK1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0                      _MK_ADDR_CONST(0x7d0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0_SET_CLK_ENB_DSPK1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0                      _MK_ADDR_CONST(0x7d0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0_CLR_CLK_ENB_DSPK1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0                  _MK_ADDR_CONST(0x7d1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0_BOND_OUT_DSPK1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0                   _MK_ADDR_CONST(0x7d2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0_DSPK1_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0                       _MK_ADDR_CONST(0x7d3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0                  _MK_ADDR_CONST(0x7e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0_CLK_ENB_DSPK2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0                      _MK_ADDR_CONST(0x7e0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0_SET_CLK_ENB_DSPK2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0                      _MK_ADDR_CONST(0x7e0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0_CLR_CLK_ENB_DSPK2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0                  _MK_ADDR_CONST(0x7e1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0_BOND_OUT_DSPK2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0                   _MK_ADDR_CONST(0x7e2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_INIT_ENUM                   PLLA_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLA1_OUT1                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_SYNC_CLK                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0_DSPK2_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0                       _MK_ADDR_CONST(0x7e3000)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SCR                   0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_RANGE                    4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S2                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S3                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S4                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S5                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_PLLA_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0_SYNC_CLK_RATE_I2S6                    _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0                   _MK_ADDR_CONST(0x7f0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0_CLK_ENB_I2S6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0                       _MK_ADDR_CONST(0x7f0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0_SET_CLK_ENB_I2S6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0                       _MK_ADDR_CONST(0x7f0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0_CLR_CLK_ENB_I2S6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0                   _MK_ADDR_CONST(0x7f1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0_BOND_OUT_I2S6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0                    _MK_ADDR_CONST(0x7f2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLA1_OUT1                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_SYNC_CLK                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_SRC_CLK_M                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0_I2S6_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0                        _MK_ADDR_CONST(0x7f2004)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SCR                    0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_RANGE                     4:4
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S3                     _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S4                     _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S5                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0_SYNC_CLK_RATE_I2S6                     _MK_ENUM_CONST(7)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0                 _MK_ADDR_CONST(0x800000)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SCR                     0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_RESET_VAL                       _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_MISC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0                     _MK_ADDR_CONST(0x800004)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_RESET_VAL                   _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_MISC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0_SET_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0                     _MK_ADDR_CONST(0x800008)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_RANGE                   9:9
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_MISC_RST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_RANGE                  8:8
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP5_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_RANGE                  7:7
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP4_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP3_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_RANGE                  5:5
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_WGRP0_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_RANGE                  2:2
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD2_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD1_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0_CLR_SWR_NVDISPLAY0_HEAD0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0                     _MK_ADDR_CONST(0x801000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_P0_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DISP_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAY_DSC_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0_CLK_ENB_NVDISPLAYHUB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0                 _MK_ADDR_CONST(0x801004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_P0_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DISP_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAY_DSC_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0_SET_CLK_ENB_NVDISPLAYHUB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0                 _MK_ADDR_CONST(0x801008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_P0_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DISP_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAY_DSC_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_RANGE                  3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0_CLR_CLK_ENB_NVDISPLAYHUB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0                     _MK_ADDR_CONST(0x802000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_RANGE                 3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAYHUB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_RANGE                        2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DSC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_DISP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0_BOND_OUT_NVDISPLAY_P0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0                    _MK_ADDR_CONST(0x803000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_RESET_VAL                  _MK_MASK_CONST(0xa0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_RESET_MASK                         _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_READ_MASK                  _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_WRITE_MASK                         _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD_OUT1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD2_OUT0                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD3_OUT0                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_CLK_M                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_SRC_PLLD_OUT2                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_P0_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_RANGE                   8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0_NVDISPLAY_DSC_CLK_DIV2_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0                  _MK_ADDR_CONST(0x804000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_RESET_VAL                        _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_RESET_MASK                       _MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_READ_MASK                        _MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_WRITE_MASK                       _MK_MASK_CONST(0xff0000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_RANGE                     31:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x40)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P0_CLK                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P1_CLK                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_NVDISPLAY_P2_CLK                  _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_SOR_SAFE_CLK                      _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_DFLLDISP_DIV                      _MK_ENUM_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_PLLDISPHUB_DIV                    _MK_ENUM_CONST(32)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_SRC_CLK_M                     _MK_ENUM_CONST(64)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0_NVDISPLAY_DISP_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0                    _MK_ADDR_CONST(0x805000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_PLLDISPHUB                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_DFLLDISP                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0_NVDISPLAYHUB_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0                     _MK_ADDR_CONST(0x805004)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_RESET_VAL                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_RESET_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_READ_MASK                   _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_WRITE_MASK                  _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0_SUPER_NVDISPLAYHUB_DIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0                       _MK_ADDR_CONST(0x806000)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0_CLK_SPARE_REG_NVDISPLAY0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0                     _MK_ADDR_CONST(0x810000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0_CLK_ENB_NVDISPLAY_P1_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0                 _MK_ADDR_CONST(0x810004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0_SET_CLK_ENB_NVDISPLAY_P1_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0                 _MK_ADDR_CONST(0x810008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0_CLR_CLK_ENB_NVDISPLAY_P1_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0                     _MK_ADDR_CONST(0x811000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0_BOND_OUT_NVDISPLAY_P1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0                    _MK_ADDR_CONST(0x812000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD_OUT1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD2_OUT0                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD3_OUT0                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_SRC_PLLD_OUT2                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0_NVDISPLAY_P1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0                     _MK_ADDR_CONST(0x820000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0_CLK_ENB_NVDISPLAY_P2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0                 _MK_ADDR_CONST(0x820004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0_SET_CLK_ENB_NVDISPLAY_P2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0                 _MK_ADDR_CONST(0x820008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0_CLR_CLK_ENB_NVDISPLAY_P2_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0                     _MK_ADDR_CONST(0x821000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SCR                         0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0_BOND_OUT_NVDISPLAY_P2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0                    _MK_ADDR_CONST(0x822000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD_OUT1                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD2_OUT0                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD3_OUT0                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_SRC_PLLD_OUT2                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0_NVDISPLAY_P2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 8585216 [0x830000]

// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0                  _MK_ADDR_CONST(0x840000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0_SWR_GPIO_CTL0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0                      _MK_ADDR_CONST(0x840004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0_SET_SWR_GPIO_CTL0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0                      _MK_ADDR_CONST(0x840008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0_CLR_SWR_GPIO_CTL0_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0                      _MK_ADDR_CONST(0x841000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0_CLK_ENB_GPIO_CTL0_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0                  _MK_ADDR_CONST(0x841004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0_SET_CLK_ENB_GPIO_CTL0_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0                  _MK_ADDR_CONST(0x841008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0_CLR_CLK_ENB_GPIO_CTL0_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0                      _MK_ADDR_CONST(0x842000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0_BOND_OUT_GPIO_CTL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0                       _MK_ADDR_CONST(0x843000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0_GPIO_CTL0_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0                  _MK_ADDR_CONST(0x850000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0_SWR_GPIO_CTL1_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0                      _MK_ADDR_CONST(0x850004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0_SET_SWR_GPIO_CTL1_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0                      _MK_ADDR_CONST(0x850008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0_CLR_SWR_GPIO_CTL1_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0                      _MK_ADDR_CONST(0x851000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0_CLK_ENB_GPIO_CTL1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0                  _MK_ADDR_CONST(0x851004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0_SET_CLK_ENB_GPIO_CTL1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0                  _MK_ADDR_CONST(0x851008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0_CLR_CLK_ENB_GPIO_CTL1_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0                      _MK_ADDR_CONST(0x852000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0_BOND_OUT_GPIO_CTL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0                       _MK_ADDR_CONST(0x853000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0_GPIO_CTL1_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0                  _MK_ADDR_CONST(0x860000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0_SWR_GPIO_CTL2_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0                      _MK_ADDR_CONST(0x860004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0_SET_SWR_GPIO_CTL2_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0                      _MK_ADDR_CONST(0x860008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0_CLR_SWR_GPIO_CTL2_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0                      _MK_ADDR_CONST(0x861000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0_CLK_ENB_GPIO_CTL2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0                  _MK_ADDR_CONST(0x861004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0_SET_CLK_ENB_GPIO_CTL2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0                  _MK_ADDR_CONST(0x861008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0_CLR_CLK_ENB_GPIO_CTL2_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0                      _MK_ADDR_CONST(0x862000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0_BOND_OUT_GPIO_CTL2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0                       _MK_ADDR_CONST(0x863000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0_GPIO_CTL2_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0                  _MK_ADDR_CONST(0x870000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0_SWR_GPIO_CTL3_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0                      _MK_ADDR_CONST(0x870004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0_SET_SWR_GPIO_CTL3_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0                      _MK_ADDR_CONST(0x870008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0_CLR_SWR_GPIO_CTL3_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0                      _MK_ADDR_CONST(0x871000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0_CLK_ENB_GPIO_CTL3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0                  _MK_ADDR_CONST(0x871004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0_SET_CLK_ENB_GPIO_CTL3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0                  _MK_ADDR_CONST(0x871008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0_CLR_CLK_ENB_GPIO_CTL3_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0                      _MK_ADDR_CONST(0x872000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0_BOND_OUT_GPIO_CTL3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0                       _MK_ADDR_CONST(0x873000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0_GPIO_CTL3_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0                  _MK_ADDR_CONST(0x880000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0_SWR_GPIO_CTL4_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0                      _MK_ADDR_CONST(0x880004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0_SET_SWR_GPIO_CTL4_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0                      _MK_ADDR_CONST(0x880008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0_CLR_SWR_GPIO_CTL4_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0                      _MK_ADDR_CONST(0x881000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0_CLK_ENB_GPIO_CTL4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0                  _MK_ADDR_CONST(0x881004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0_SET_CLK_ENB_GPIO_CTL4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0                  _MK_ADDR_CONST(0x881008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0_CLR_CLK_ENB_GPIO_CTL4_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0                      _MK_ADDR_CONST(0x882000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0_BOND_OUT_GPIO_CTL4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0                       _MK_ADDR_CONST(0x883000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0_GPIO_CTL4_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0                       _MK_ADDR_CONST(0x890000)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_0_SWR_TACH_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0                   _MK_ADDR_CONST(0x890004)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0_SET_SWR_TACH_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0                   _MK_ADDR_CONST(0x890008)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0_CLR_SWR_TACH_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0                   _MK_ADDR_CONST(0x891000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0_CLK_ENB_TACH_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0                       _MK_ADDR_CONST(0x891004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0_SET_CLK_ENB_TACH_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0                       _MK_ADDR_CONST(0x891008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0_CLR_CLK_ENB_TACH_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0                   _MK_ADDR_CONST(0x892000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0_BOND_OUT_TACH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0                    _MK_ADDR_CONST(0x893000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_RESET_VAL                  _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_CLK_M                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0_TACH_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0                       _MK_ADDR_CONST(0x8a0000)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_0_SWR_EQOS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0                   _MK_ADDR_CONST(0x8a0004)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0_SET_SWR_EQOS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0                   _MK_ADDR_CONST(0x8a0008)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0_CLR_SWR_EQOS_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0                   _MK_ADDR_CONST(0x8a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0_CLK_ENB_EQOS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0                       _MK_ADDR_CONST(0x8a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0_SET_CLK_ENB_EQOS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0                       _MK_ADDR_CONST(0x8a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0_CLR_CLK_ENB_EQOS_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0                   _MK_ADDR_CONST(0x8a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0_BOND_OUT_EQOS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0                    _MK_ADDR_CONST(0x8a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_RESET_VAL                  _MK_MASK_CONST(0x800)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_RESET_MASK                         _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_READ_MASK                  _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_WRITE_MASK                         _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_RANGE                 15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0_EQOS_AXI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0                        _MK_ADDR_CONST(0x8a3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_RESET_VAL                      _MK_MASK_CONST(0x3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_RESET_MASK                     _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_READ_MASK                      _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_WRITE_MASK                     _MK_MASK_CONST(0xff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_RANGE                 15:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x30)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0_EQOS_PTP_REF_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0                     _MK_ADDR_CONST(0x8a3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_RESET_VAL                   _MK_MASK_CONST(0x800)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_RESET_MASK                  _MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_READ_MASK                   _MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff00)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_RANGE                   16:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0_EQOS_TX_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0                        _MK_ADDR_CONST(0x8b0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0_CLK_ENB_EQOS_RX_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0                    _MK_ADDR_CONST(0x8b0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0_SET_CLK_ENB_EQOS_RX_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0                    _MK_ADDR_CONST(0x8b0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0_CLR_CLK_ENB_EQOS_RX_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0                        _MK_ADDR_CONST(0x8b1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0_BOND_OUT_EQOS_RX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0                      _MK_ADDR_CONST(0x8c0000)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_0_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0                  _MK_ADDR_CONST(0x8c0004)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0_SET_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0                  _MK_ADDR_CONST(0x8c0008)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0_CLR_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0                  _MK_ADDR_CONST(0x8c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_RESET_VAL                        _MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_RESET_MASK                       _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_READ_MASK                        _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_WRITE_MASK                       _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MCHUBSB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SHIFT                        _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC3_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_IOBIST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMCSB_LATENCY_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_BBC_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_INIT_ENUM                 ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MC_CPU_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DLL_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_MEM_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0_CLK_ENB_EMC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0                      _MK_ADDR_CONST(0x8c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_RESET_VAL                    _MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_RESET_MASK                   _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_READ_MASK                    _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MCHUBSB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SHIFT                        _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC3_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_IOBIST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMCSB_LATENCY_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_BBC_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MC_CPU_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DLL_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_MEM_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0_SET_CLK_ENB_EMC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0                      _MK_ADDR_CONST(0x8c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x660)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_READ_MASK                    _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_RANGE                    10:10
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MCHUBSB_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SHIFT                        _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_RANGE                        9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC3_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_RANGE                       8:8
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_IOBIST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_RANGE                      7:7
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMCSB_LATENCY_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_RANGE                     6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_BBC_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_RANGE                     5:5
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MC_CPU_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DLL_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_MEM_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0_CLR_CLK_ENB_EMC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0                  _MK_ADDR_CONST(0x8c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_RESET_MASK                       _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_READ_MASK                        _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_WRITE_MASK                       _MK_MASK_CONST(0x7e7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_RANGE                   10:10
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MCHUBSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SHIFT                       _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_RANGE                       9:9
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_RANGE                      8:8
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_IOBIST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_RANGE                     7:7
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMCSB_LATENCY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_RANGE                    6:6
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_BBC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_RANGE                    5:5
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MC_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_RANGE                   2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DLL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0_BOND_OUT_EMC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0                   _MK_ADDR_CONST(0x8c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_RESET_VAL                         _MK_MASK_CONST(0x60100000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_RESET_MASK                        _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_READ_MASK                         _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_WRITE_MASK                        _MK_MASK_CONST(0xee1180ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_RANGE                      31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_DEFAULT                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_INIT_ENUM                  CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLM_OUT0                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLP_OUT0                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_CLK_M                      _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLM_UD                    _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLMB_UD                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLMB_OUT0                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_SRC_PLLP_UD                    _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_RANGE                    27:27
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_FORCE_CC_TRIGGER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_RANGE                      26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_INVERT_DCD_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_RANGE                  25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_USE_32KHZ_AS_CLK_M_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_RANGE                 20:20
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_PLLC_OUT_FOR_EMC_EN_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_MC_EMC_SAME_FREQ_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_RANGE                     15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_CLK_DIV2_EN_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_RANGE                  7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0                   _MK_ADDR_CONST(0x8c3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_RESET_VAL                         _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0_EMC_LATENCY_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0                       _MK_ADDR_CONST(0x8c3008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_RESET_VAL                     _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_RESET_MASK                    _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_READ_MASK                     _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_WRITE_MASK                    _MK_MASK_CONST(0xe0000cff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLM_UD                       _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLMB_UD                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLMB_OUT0                    _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_SRC_PLLP_UD                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_RANGE                    11:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PLLM_VCOA                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_PLLM_VCOB                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_DDLL_CLK_SEL_EMC_DLL_SWITCH_OUT                       _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0_EMC_DLL_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0                  _MK_ADDR_CONST(0x8c300c)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_RANGE                      31:31
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_ENABLE_EMC_DIV_SHAPER_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_RANGE                      11:11
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_RANGE                      10:10
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_N1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_RANGE                      9:9
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_RANGE                      8:8
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_P1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT                        _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_RANGE                        7:7
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                    DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_TRIM_SELECT_SW_PROG                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_RANGE                  6:6
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                      ACTIVE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_ACTIVE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_SW_BYPASS_BYPASS                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_RANGE                 5:5
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DF_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_RANGE                 4:3
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_RANGE                 2:2
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_DR_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_RANGE                 1:0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0_EMC_DIV_CLK_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0                     _MK_ADDR_CONST(0x8c3010)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SCR                         0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0xc00)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_RANGE                        31:31
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_ENABLE_EMC_PLLC_SHAPER_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_RANGE                    11:11
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_RANGE                    10:10
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_N1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_RANGE                    9:9
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_RANGE                    8:8
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_P1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_RANGE                      7:7
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_INIT_ENUM                  DEFAULT_SETTING
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_DEFAULT_SETTING                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_TRIM_SELECT_SW_PROG                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_RANGE                        6:6
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_INIT_ENUM                    ACTIVE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_ACTIVE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_SW_BYPASS_BYPASS                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT                       _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_RANGE                       5:5
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DF_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_RANGE                       4:3
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_FALL_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_RANGE                       2:2
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_DR_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_RANGE                       1:0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0_EMC_PLLC_SHAPER_CTRL_RISE_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0                      _MK_ADDR_CONST(0x8c3014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_RESET_VAL                    _MK_MASK_CONST(0x60000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_RESET_MASK                   _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_READ_MASK                    _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_WRITE_MASK                   _MK_MASK_CONST(0xe40000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT                    _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_RANGE                    31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_INIT_ENUM                        CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_OUT0                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLC_OUT0                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_OUT0                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_CLK_M                    _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLM_UD                  _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_UD                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLMB_OUT0                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_SRC_PLLP_UD                  _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT                    _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_RANGE                    26:26
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_SAFE_INVERT_DCD_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0_EMC_2X_SAFE_CLK_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0                     _MK_ADDR_CONST(0x8c4000)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0_CLK_SPARE_REG_EMCB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0                        _MK_ADDR_CONST(0x8d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SCR                    0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_AXI_M_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_INIT_ENUM                     ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_0_SWR_UFSHC_LP_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0                    _MK_ADDR_CONST(0x8d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_AXI_M_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0_SET_SWR_UFSHC_LP_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0                    _MK_ADDR_CONST(0x8d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SCR                        0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_AXI_M_RST_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0_CLR_SWR_UFSHC_LP_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0                    _MK_ADDR_CONST(0x8d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_RESET_MASK                         _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_READ_MASK                  _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_WRITE_MASK                         _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSDEV_REF_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0_CLK_ENB_UFSHC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0                        _MK_ADDR_CONST(0x8d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_RESET_MASK                     _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_READ_MASK                      _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSDEV_REF_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0_SET_CLK_ENB_UFSHC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0                        _MK_ADDR_CONST(0x8d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SCR                    0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_READ_MASK                      _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_RANGE                   31:31
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSDEV_REF_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0_CLR_CLK_ENB_UFSHC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0                    _MK_ADDR_CONST(0x8d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_RESET_MASK                         _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_READ_MASK                  _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_WRITE_MASK                         _MK_MASK_CONST(0x80000001)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_RANGE                  31:31
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSDEV_REF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0_BOND_OUT_UFSHC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0                    _MK_ADDR_CONST(0x8d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_CLK_M                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_SRC_PLLREFE_VCOCLK                        _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0_UFSHC_CG_SYS_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0                      _MK_ADDR_CONST(0x8d3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_RESET_VAL                    _MK_MASK_CONST(0xa000003f)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_RESET_MASK                   _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_READ_MASK                    _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_WRITE_MASK                   _MK_MASK_CONST(0xe00001ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_INIT_ENUM                 PLLREFE_VCOCLK
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_CLK_M                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_SRC_PLLREFE_VCOCLK                    _MK_ENUM_CONST(5)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_RANGE                 8:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0_UFSDEV_REF_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0                      _MK_ADDR_CONST(0x8e0000)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_0_SWR_NVCSI_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0                  _MK_ADDR_CONST(0x8e0004)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0_SET_SWR_NVCSI_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0                  _MK_ADDR_CONST(0x8e0008)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0_CLR_SWR_NVCSI_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0                  _MK_ADDR_CONST(0x8e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSI_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0_CLK_ENB_NVCSILP_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0                      _MK_ADDR_CONST(0x8e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSI_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0_SET_CLK_ENB_NVCSILP_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0                      _MK_ADDR_CONST(0x8e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSI_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_RANGE                    1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0_CLR_CLK_ENB_NVCSILP_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0                  _MK_ADDR_CONST(0x8e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_RANGE                   1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSILP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0_BOND_OUT_NVCSI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0                   _MK_ADDR_CONST(0x8e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_RESET_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_WRITE_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_PLLNVCSI_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_SRC_CLK_M                       _MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_SHIFT                 _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_RANGE                 15:15
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_SHIFT                 _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_RANGE                 14:14
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_RANGE                 13:13
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_RANGE                  12:12
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_EF_DIFF_MUX_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_RANGE                  11:11
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_CD_DIFF_MUX_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_RANGE                  10:10
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_AB_DIFF_MUX_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_RANGE                      9:8
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_INIT_ENUM                  CSI_AB_PAD_CLOCKOUT
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_AB_PAD_CLOCKOUT                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_CD_PAD_CLOCKOUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_CSI_EF_PAD_CLOCKOUT                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_CSI_PADOUT_SRC_PLLD_SLOWCLK_PLL                   _MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0_NVCSI_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0                 _MK_ADDR_CONST(0x8e3004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(4)

#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0_NVCSILP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0                       _MK_ADDR_CONST(0x8f0000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0_SWR_I2C7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0                   _MK_ADDR_CONST(0x8f0004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0_SET_SWR_I2C7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0                   _MK_ADDR_CONST(0x8f0008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0_CLR_SWR_I2C7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0                   _MK_ADDR_CONST(0x8f1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0_CLK_ENB_I2C7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0                       _MK_ADDR_CONST(0x8f1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0_SET_CLK_ENB_I2C7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0                       _MK_ADDR_CONST(0x8f1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0_CLR_CLK_ENB_I2C7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0                   _MK_ADDR_CONST(0x8f2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0_BOND_OUT_I2C7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0                    _MK_ADDR_CONST(0x8f3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_RESET_VAL                  _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_CLK_M                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0                       _MK_ADDR_CONST(0x900000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_0_SWR_I2C9_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0                   _MK_ADDR_CONST(0x900004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0_SET_SWR_I2C9_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0                   _MK_ADDR_CONST(0x900008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0_CLR_SWR_I2C9_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0                   _MK_ADDR_CONST(0x901000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0_CLK_ENB_I2C9_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0                       _MK_ADDR_CONST(0x901004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0_SET_CLK_ENB_I2C9_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0                       _MK_ADDR_CONST(0x901008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0_CLR_CLK_ENB_I2C9_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0                   _MK_ADDR_CONST(0x902000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0_BOND_OUT_I2C9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0                    _MK_ADDR_CONST(0x903000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_RESET_VAL                  _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_CLK_M                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0_I2C9_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 9502720 [0x910000]

// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0                      _MK_ADDR_CONST(0x920000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_0_SWR_I2C12_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0                  _MK_ADDR_CONST(0x920004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0_SET_SWR_I2C12_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0                  _MK_ADDR_CONST(0x920008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0_CLR_SWR_I2C12_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0                  _MK_ADDR_CONST(0x921000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0_CLK_ENB_I2C12_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0                      _MK_ADDR_CONST(0x921004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0_SET_CLK_ENB_I2C12_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0                      _MK_ADDR_CONST(0x921008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0_CLR_CLK_ENB_I2C12_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0                  _MK_ADDR_CONST(0x922000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0_BOND_OUT_I2C12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0                   _MK_ADDR_CONST(0x923000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_RESET_VAL                         _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_RESET_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_WRITE_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0_I2C12_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0                      _MK_ADDR_CONST(0x930000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_0_SWR_I2C13_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0                  _MK_ADDR_CONST(0x930004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0_SET_SWR_I2C13_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0                  _MK_ADDR_CONST(0x930008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0_CLR_SWR_I2C13_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0                  _MK_ADDR_CONST(0x931000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0_CLK_ENB_I2C13_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0                      _MK_ADDR_CONST(0x931004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0_SET_CLK_ENB_I2C13_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0                      _MK_ADDR_CONST(0x931008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0_CLR_CLK_ENB_I2C13_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0                  _MK_ADDR_CONST(0x932000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0_BOND_OUT_I2C13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0                   _MK_ADDR_CONST(0x933000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_RESET_VAL                         _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_RESET_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_WRITE_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0_I2C13_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0                      _MK_ADDR_CONST(0x940000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_0_SWR_I2C14_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0                  _MK_ADDR_CONST(0x940004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0_SET_SWR_I2C14_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0                  _MK_ADDR_CONST(0x940008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0_CLR_SWR_I2C14_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0                  _MK_ADDR_CONST(0x941000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0_CLK_ENB_I2C14_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0                      _MK_ADDR_CONST(0x941004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0_SET_CLK_ENB_I2C14_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0                      _MK_ADDR_CONST(0x941008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0_CLR_CLK_ENB_I2C14_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0                  _MK_ADDR_CONST(0x942000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0_BOND_OUT_I2C14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0                   _MK_ADDR_CONST(0x943000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_RESET_VAL                         _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_RESET_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_WRITE_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0_I2C14_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0                       _MK_ADDR_CONST(0x950000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_0_SWR_PWM1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0                   _MK_ADDR_CONST(0x950004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0_SET_SWR_PWM1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0                   _MK_ADDR_CONST(0x950008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0_CLR_SWR_PWM1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0                   _MK_ADDR_CONST(0x951000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0_CLK_ENB_PWM1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0                       _MK_ADDR_CONST(0x951004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0_SET_CLK_ENB_PWM1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0                       _MK_ADDR_CONST(0x951008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0_CLR_CLK_ENB_PWM1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0                   _MK_ADDR_CONST(0x952000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0_BOND_OUT_PWM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0                    _MK_ADDR_CONST(0x953000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0_PWM1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 9777156 [0x953004]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0                       _MK_ADDR_CONST(0x960000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_0_SWR_PWM2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0                   _MK_ADDR_CONST(0x960004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0_SET_SWR_PWM2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0                   _MK_ADDR_CONST(0x960008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0_CLR_SWR_PWM2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0                   _MK_ADDR_CONST(0x961000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0_CLK_ENB_PWM2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0                       _MK_ADDR_CONST(0x961004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0_SET_CLK_ENB_PWM2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0                       _MK_ADDR_CONST(0x961008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0_CLR_CLK_ENB_PWM2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0                   _MK_ADDR_CONST(0x962000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0_BOND_OUT_PWM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0                    _MK_ADDR_CONST(0x963000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0_PWM2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 9842692 [0x963004]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0                       _MK_ADDR_CONST(0x970000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_0_SWR_PWM3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0                   _MK_ADDR_CONST(0x970004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0_SET_SWR_PWM3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0                   _MK_ADDR_CONST(0x970008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0_CLR_SWR_PWM3_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0                   _MK_ADDR_CONST(0x971000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0_CLK_ENB_PWM3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0                       _MK_ADDR_CONST(0x971004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0_SET_CLK_ENB_PWM3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0                       _MK_ADDR_CONST(0x971008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0_CLR_CLK_ENB_PWM3_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0                   _MK_ADDR_CONST(0x972000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0_BOND_OUT_PWM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0                    _MK_ADDR_CONST(0x973000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0_PWM3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 9908228 [0x973004]

// Reserved address 9961472 [0x980000]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0                       _MK_ADDR_CONST(0x990000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_0_SWR_PWM5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0                   _MK_ADDR_CONST(0x990004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0_SET_SWR_PWM5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0                   _MK_ADDR_CONST(0x990008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0_CLR_SWR_PWM5_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0                   _MK_ADDR_CONST(0x991000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0_CLK_ENB_PWM5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0                       _MK_ADDR_CONST(0x991004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0_SET_CLK_ENB_PWM5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0                       _MK_ADDR_CONST(0x991008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0_CLR_CLK_ENB_PWM5_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0                   _MK_ADDR_CONST(0x992000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0_BOND_OUT_PWM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0                    _MK_ADDR_CONST(0x993000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0_PWM5_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 10039300 [0x993004]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0                       _MK_ADDR_CONST(0x9a0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_0_SWR_PWM6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0                   _MK_ADDR_CONST(0x9a0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0_SET_SWR_PWM6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0                   _MK_ADDR_CONST(0x9a0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0_CLR_SWR_PWM6_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0                   _MK_ADDR_CONST(0x9a1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0_CLK_ENB_PWM6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0                       _MK_ADDR_CONST(0x9a1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0_SET_CLK_ENB_PWM6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0                       _MK_ADDR_CONST(0x9a1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0_CLR_CLK_ENB_PWM6_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0                   _MK_ADDR_CONST(0x9a2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0_BOND_OUT_PWM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0                    _MK_ADDR_CONST(0x9a3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0_PWM6_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 10104836 [0x9a3004]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0                       _MK_ADDR_CONST(0x9b0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_0_SWR_PWM7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0                   _MK_ADDR_CONST(0x9b0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0_SET_SWR_PWM7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0                   _MK_ADDR_CONST(0x9b0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0_CLR_SWR_PWM7_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0                   _MK_ADDR_CONST(0x9b1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0_CLK_ENB_PWM7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0                       _MK_ADDR_CONST(0x9b1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0_SET_CLK_ENB_PWM7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0                       _MK_ADDR_CONST(0x9b1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0_CLR_CLK_ENB_PWM7_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0                   _MK_ADDR_CONST(0x9b2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0_BOND_OUT_PWM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0                    _MK_ADDR_CONST(0x9b3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0_PWM7_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 10170372 [0x9b3004]

// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0                       _MK_ADDR_CONST(0x9c0000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_0_SWR_PWM8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0                   _MK_ADDR_CONST(0x9c0004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0_SET_SWR_PWM8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0                   _MK_ADDR_CONST(0x9c0008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0_CLR_SWR_PWM8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0                   _MK_ADDR_CONST(0x9c1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0_CLK_ENB_PWM8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0                       _MK_ADDR_CONST(0x9c1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0_SET_CLK_ENB_PWM8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0                       _MK_ADDR_CONST(0x9c1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0_CLR_CLK_ENB_PWM8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0                   _MK_ADDR_CONST(0x9c2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0_BOND_OUT_PWM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0                    _MK_ADDR_CONST(0x9c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SCR                        0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0_PWM8_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 10235908 [0x9c3004]

// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0                      _MK_ADDR_CONST(0x9d0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_0_SWR_UARTE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0                  _MK_ADDR_CONST(0x9d0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0_SET_SWR_UARTE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0                  _MK_ADDR_CONST(0x9d0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0_CLR_SWR_UARTE_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0                  _MK_ADDR_CONST(0x9d1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0_CLK_ENB_UARTE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0                      _MK_ADDR_CONST(0x9d1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0_SET_CLK_ENB_UARTE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0                      _MK_ADDR_CONST(0x9d1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0_CLR_CLK_ENB_UARTE_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0                  _MK_ADDR_CONST(0x9d2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0_BOND_OUT_UARTE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0                   _MK_ADDR_CONST(0x9d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0                      _MK_ADDR_CONST(0x9e0000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0_SWR_UARTF_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0                  _MK_ADDR_CONST(0x9e0004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0_SET_SWR_UARTF_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0                  _MK_ADDR_CONST(0x9e0008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0_CLR_SWR_UARTF_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0                  _MK_ADDR_CONST(0x9e1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0_CLK_ENB_UARTF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0                      _MK_ADDR_CONST(0x9e1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0_SET_CLK_ENB_UARTF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0                      _MK_ADDR_CONST(0x9e1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0_CLR_CLK_ENB_UARTF_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0                  _MK_ADDR_CONST(0x9e2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0_BOND_OUT_UARTF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0                   _MK_ADDR_CONST(0x9e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0                 _MK_ADDR_CONST(0x9f0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0_CLK_ENB_DBGAPB_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0                     _MK_ADDR_CONST(0x9f0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0_SET_CLK_ENB_DBGAPB_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0                     _MK_ADDR_CONST(0x9f0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0_CLR_CLK_ENB_DBGAPB_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0                 _MK_ADDR_CONST(0x9f1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0_BOND_OUT_DBGAPB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0                  _MK_ADDR_CONST(0x9f2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_CLK_S                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_SRC_CLK_M                     _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0_DBGAPB_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0                    _MK_ADDR_CONST(0xa00000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_RESET_VAL                  _MK_MASK_CONST(0x108002)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_RESET_MASK                         _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_READ_MASK                  _MK_MASK_CONST(0xedf3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_WRITE_MASK                         _MK_MASK_CONST(0xe1f3fcff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_BYPASS_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_REF_ENABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_REF_DIS_REF_DISABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_FREQ_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_LOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_DEFAULT                    _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_DEFAULT                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0_PLLBPMPCAM_DIVM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0                  _MK_ADDR_CONST(0xa00004)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_RESET_VAL                        _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_RESET_MASK                       _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_READ_MASK                        _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_WRITE_MASK                       _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_RESET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_EXT_FRU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_PTS_FO                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0_PLLBPMPCAM_LOOP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0                  _MK_ADDR_CONST(0xa00008)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_RESET_VAL                        _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_RESET_MASK                       _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_READ_MASK                        _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_WRITE_MASK                       _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_IDDQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_EXT_SUBINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0_PLLBPMPCAM_DIVN_FRAC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0                  _MK_ADDR_CONST(0xa0000c)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_RESET_VAL                        _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_RESET_MASK                       _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_READ_MASK                        _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_PLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0_PLLBPMPCAM_FLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0                  _MK_ADDR_CONST(0xa00010)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_RESET_VAL                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_READ_MASK                        _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_VREG10V_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_LDIV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_DEFAULT                    _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0_PLLBPMPCAM_PLL_LD_TOL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0                  _MK_ADDR_CONST(0xa00014)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_RESET_VAL                        _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_RESET_MASK                       _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_READ_MASK                        _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_WRITE_MASK                       _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_SEL_IREF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_KP_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0_PLLBPMPCAM_FRAC_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0                     _MK_ADDR_CONST(0xa01000)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SCR                         0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_RANGE                    7:0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0_CLK_SPARE_REG_BPMP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0                       _MK_ADDR_CONST(0xa10000)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_READ_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NIC_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NSYSPORESET_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_NRESET_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_DBGRESETN_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0_SWR_BPMP_PRESETDBGN_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0                   _MK_ADDR_CONST(0xa10004)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_READ_MASK                         _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NIC_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NSYSPORESET_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_RANGE                     2:2
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_NRESET_RST_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_DBGRESETN_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0_SET_SWR_BPMP_PRESETDBGN_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0                   _MK_ADDR_CONST(0xa10008)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_RANGE                        4:4
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NIC_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_RANGE                        3:3
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_NSYSPORESET_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_DBGRESETN_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_RANGE                 0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0_CLR_SWR_BPMP_PRESETDBGN_RST_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0                    _MK_ADDR_CONST(0xa1000c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0_SWR_BPMP_PM_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0                        _MK_ADDR_CONST(0xa10010)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SCR                    BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0_SET_SWR_BPMP_PM_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0                        _MK_ADDR_CONST(0xa10014)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SCR                    BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0_CLR_SWR_BPMP_PM_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0                   _MK_ADDR_CONST(0xa10018)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0_SWR_BPMP_CVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0                       _MK_ADDR_CONST(0xa1001c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0_SET_SWR_BPMP_CVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0                       _MK_ADDR_CONST(0xa10020)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0_CLR_SWR_BPMP_CVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0                   _MK_ADDR_CONST(0xa10024)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0_SWR_BPMP_DMA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0                       _MK_ADDR_CONST(0xa10028)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0_SET_SWR_BPMP_DMA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0                       _MK_ADDR_CONST(0xa1002c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0_CLR_SWR_BPMP_DMA_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0                   _MK_ADDR_CONST(0xa10030)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0_SWR_BPMP_HSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0                       _MK_ADDR_CONST(0xa10034)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0_SET_SWR_BPMP_HSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0                       _MK_ADDR_CONST(0xa10038)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0_CLR_SWR_BPMP_HSP_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0                  _MK_ADDR_CONST(0xa1003c)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0_SWR_TSCTNBPMP_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0                      _MK_ADDR_CONST(0xa10040)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0_SET_SWR_TSCTNBPMP_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0                      _MK_ADDR_CONST(0xa10044)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0_CLR_SWR_TSCTNBPMP_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0                   _MK_ADDR_CONST(0xa10048)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0_SWR_BPMP_TKE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0                       _MK_ADDR_CONST(0xa1004c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0_SET_SWR_BPMP_TKE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0                       _MK_ADDR_CONST(0xa10050)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0_CLR_SWR_BPMP_TKE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0                   _MK_ADDR_CONST(0xa10054)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0_SWR_BPMP_GTE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0                       _MK_ADDR_CONST(0xa10058)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0_SET_SWR_BPMP_GTE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0                       _MK_ADDR_CONST(0xa1005c)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0_CLR_SWR_BPMP_GTE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0                   _MK_ADDR_CONST(0xa11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_RESET_VAL                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_RESET_MASK                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_READ_MASK                         _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_WRITE_MASK                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0_CLK_ENB_BPMP_CPU_NIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0                       _MK_ADDR_CONST(0xa11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_RESET_VAL                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_RESET_MASK                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_READ_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0_SET_CLK_ENB_BPMP_CPU_NIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0                       _MK_ADDR_CONST(0xa11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_READ_MASK                     _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_RANGE                    2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_RANGE                        1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0_CLR_CLK_ENB_BPMP_CPU_NIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0                   _MK_ADDR_CONST(0xa12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_RANGE                       1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_NIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0_BOND_OUT_BPMP_CPU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0                    _MK_ADDR_CONST(0xa13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_RESET_MASK                         _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_READ_MASK                  _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0_BPMP_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NIC_RATE_0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0                      _MK_ADDR_CONST(0xa13004)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SCR                  BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_RESET_VAL                    _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_RESET_MASK                   _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_READ_MASK                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_WRITE_MASK                   _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_RANGE                        4:4
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_RANGE                  1:0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NIC_RATE_0_BPMP_NIC_RATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0                 _MK_ADDR_CONST(0xa13008)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_READ_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_RANGE                   4:0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_DEFAULT                 _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0_BPMP_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0                   _MK_ADDR_CONST(0xa20000)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0_SWR_BPMP_APB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0                       _MK_ADDR_CONST(0xa20004)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0_SET_SWR_BPMP_APB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0                       _MK_ADDR_CONST(0xa20008)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0_CLR_SWR_BPMP_APB_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0                       _MK_ADDR_CONST(0xa21000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0_CLK_ENB_BPMP_APB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0                   _MK_ADDR_CONST(0xa21004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0_SET_CLK_ENB_BPMP_APB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0                   _MK_ADDR_CONST(0xa21008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0_CLR_CLK_ENB_BPMP_APB_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0                       _MK_ADDR_CONST(0xa22000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SCR                   0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0_BOND_OUT_BPMP_APB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0                        _MK_ADDR_CONST(0xa23000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_RESET_MASK                     _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_READ_MASK                      _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_RANGE                      17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0_BPMP_APB_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0                  _MK_ADDR_CONST(0xa30000)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SCR                      BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0_SWR_SOC_THERM_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0                      _MK_ADDR_CONST(0xa30004)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SCR                  BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0_SET_SWR_SOC_THERM_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0                      _MK_ADDR_CONST(0xa30008)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_SCR                  BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0_CLR_SWR_SOC_THERM_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0                      _MK_ADDR_CONST(0xa31000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SCR                  BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0_CLK_ENB_SOC_THERM_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0                  _MK_ADDR_CONST(0xa31004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SCR                      BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0_SET_CLK_ENB_SOC_THERM_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0                  _MK_ADDR_CONST(0xa31008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SCR                      BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0_CLR_CLK_ENB_SOC_THERM_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0                      _MK_ADDR_CONST(0xa32000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0_BOND_OUT_SOC_THERM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0                       _MK_ADDR_CONST(0xa33000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SCR                   BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_INIT_ENUM                   PLLP_OUT0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0_SOC_THERM_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0                     _MK_ADDR_CONST(0xa40000)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_RESET_VAL                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_BPMP_PM_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_0_SWR_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0                 _MK_ADDR_CONST(0xa40004)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_RESET_VAL                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_BPMP_PM_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0_SET_SWR_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0                 _MK_ADDR_CONST(0xa40008)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_RANGE                        1:1
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_BPMP_PM_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0_CLR_SWR_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0                 _MK_ADDR_CONST(0xa41000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0_CLK_ENB_ACTMON_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0                     _MK_ADDR_CONST(0xa41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0_SET_CLK_ENB_ACTMON_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0                     _MK_ADDR_CONST(0xa41008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SCR                         BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0_CLR_CLK_ENB_ACTMON_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0                 _MK_ADDR_CONST(0xa42000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SCR                     0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_RANGE                   0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0_BOND_OUT_ACTMON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0                  _MK_ADDR_CONST(0xa43000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0_ACTMON_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0                        _MK_ADDR_CONST(0xa50000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SCR                    BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0_CLK_ENB_TSENSOR_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0                    _MK_ADDR_CONST(0xa50004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SCR                        BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0_SET_CLK_ENB_TSENSOR_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0                    _MK_ADDR_CONST(0xa50008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SCR                        BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0_CLR_CLK_ENB_TSENSOR_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0                        _MK_ADDR_CONST(0xa51000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0_BOND_OUT_TSENSOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0                 _MK_ADDR_CONST(0xa52000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SCR                     BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_INIT_ENUM                       CLK_S
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0_TSENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0                     _MK_ADDR_CONST(0xa60000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                         BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_DFLL_BPMP                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0_BPMP_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                      _MK_ADDR_CONST(0xa60004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                  BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                       _MK_ADDR_CONST(0xa60008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_BPMP_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                       _MK_ADDR_CONST(0xa6000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_BPMP_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                    _MK_ADDR_CONST(0xa60010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                        BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_BPMP_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0                        _MK_ADDR_CONST(0xa60014)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0_BPMP_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0                 _MK_ADDR_CONST(0xa60018)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0                  _MK_ADDR_CONST(0xa6001c)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0_BPMP_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0                  _MK_ADDR_CONST(0xa60020)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0_BPMP_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0                       _MK_ADDR_CONST(0xa60024)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SCR                   BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0_BPMP_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0                 _MK_ADDR_CONST(0xa60028)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SCR                     BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_RESET_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_READ_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_DFLL_BPMP                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0_BPMP_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0                  _MK_ADDR_CONST(0xa6002c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0_BPMP_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xa60030)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0_BPMP_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xa60034)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SCR                       BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0_BPMP_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xa60038)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                    BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_BPMP                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0_BPMP_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0                 _MK_ADDR_CONST(0xa6003c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_DFLL_BPMP                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0_BPMP_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                  _MK_ADDR_CONST(0xa60040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_BPMP_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0                   _MK_ADDR_CONST(0xa60044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0_BPMP_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0                   _MK_ADDR_CONST(0xa60048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0_BPMP_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0                        _MK_ADDR_CONST(0xa6004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                    BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0_BPMP_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0                    _MK_ADDR_CONST(0xa60050)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0_BPMP_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0                     _MK_ADDR_CONST(0xa60054)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SCR                         BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0_BPMP_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0                      _MK_ADDR_CONST(0xa60058)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0_BPMP_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0                      _MK_ADDR_CONST(0xa6005c)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0_BPMP_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0                   _MK_ADDR_CONST(0xa60060)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0_BPMP_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0                     _MK_ADDR_CONST(0xa60064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SCR                         BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_DFLL_BPMP                       _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0_BPMP_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0                      _MK_ADDR_CONST(0xa60068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_BPMP                 _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0_BPMP_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0                       _MK_ADDR_CONST(0xa6006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0_BPMP_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0                       _MK_ADDR_CONST(0xa60070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                   _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0_BPMP_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0                    _MK_ADDR_CONST(0xa60074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_BPMP                     _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0_BPMP_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0                  _MK_ADDR_CONST(0xa60078)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                       _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_READ_MASK                        _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                       _MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_RANGE                    31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_ACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_RANGE                    30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_RANGE                  2:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0_BPMP_SW_TGT_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0                     _MK_ADDR_CONST(0xa6007c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SCR                         BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_RESET_VAL                   _MK_MASK_CONST(0x1c30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_RESET_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_READ_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_WRITE_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_RANGE                     12:12
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                 _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                 11:11
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                       _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                       9:9
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_RANGE                     8:8
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SHIFT                       _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_RANGE                       7:7
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SHIFT                 _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_RANGE                 6:6
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                 5:5
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_RANGE                     4:4
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_RANGE                     3:3
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_RANGE                  1:1
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_SWDIV_FSM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_RANGE                    0:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0_BPMP_RESET_PLL_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0                       _MK_ADDR_CONST(0xa60080)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SCR                   BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_RESET_VAL                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_RESET_MASK                    _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_READ_MASK                     _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_WRITE_MASK                    _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_RANGE                        31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_RANGE                        30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_RANGE                     29:29
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_RANGE                  11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0_BPMP_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0                  _MK_ADDR_CONST(0xa60084)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_RANGE                  11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0_BPMP_PLL_DLY_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0                 _MK_ADDR_CONST(0xa60088)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_FIELD                        _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_RANGE                        11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_DEFAULT                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0_BPMP_PLL_DLY_PWRUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0                      _MK_ADDR_CONST(0xa6008c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                  BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                    31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_FIELD                        _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_RANGE                        11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_DEFAULT                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0_BPMP_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0                 _MK_ADDR_CONST(0xa60090)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                     BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                 31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_FIELD                     _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_RANGE                     11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0_BPMP_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0                   _MK_ADDR_CONST(0xa60094)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SCR                       BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                         _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                        _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_READ_MASK                         _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                        _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_FIELD                      _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_RANGE                      5:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0_BPMP_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0                  _MK_ADDR_CONST(0xa60098)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SCR                      BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_RANGE                      3:3
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_RANGE                  2:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0_BPMP_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0                    _MK_ADDR_CONST(0xa6009c)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SCR                        BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_RANGE                       31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_RANGE                      30:30
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_RANGE                      7:4
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_RANGE                    3:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0_BPMP_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0                     _MK_ADDR_CONST(0xa600a0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_RESET_MASK                  _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_READ_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_WRITE_MASK                  _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_RANGE                       31:31
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_EN_SEQ_DBG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_FIELD                   _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_RANGE                   11:0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0_BPMP_LAST_SEQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0                    _MK_ADDR_CONST(0xa70000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_RANGE                     7:7
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0_BPMP_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0                   _MK_ADDR_CONST(0xa70004)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_RESET_VAL                         _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_RESET_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_READ_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_WRITE_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0_BPMP_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0                    _MK_ADDR_CONST(0xa70008)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0_BPMP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0                    _MK_ADDR_CONST(0xa7000c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0_BPMP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0                   _MK_ADDR_CONST(0xa70010)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0_BPMP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0                   _MK_ADDR_CONST(0xa70014)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_READ_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0_BPMP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0                    _MK_ADDR_CONST(0xa70018)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SCR                        BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0_BPMP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0                       _MK_ADDR_CONST(0xa7001c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SCR                   BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_RESET_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_READ_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_WRITE_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0_BPMP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0                        _MK_ADDR_CONST(0xa70020)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SCR                    BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0_BPMP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 10944548 [0xa70024]

// Reserved address 10944552 [0xa70028]

// Reserved address 10944556 [0xa7002c]

// Reserved address 10944560 [0xa70030]

// Reserved address 10944564 [0xa70034]

// Reserved address 10944568 [0xa70038]

// Reserved address 10944572 [0xa7003c]

// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0                  _MK_ADDR_CONST(0xa70040)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0_BPMP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0                  _MK_ADDR_CONST(0xa70044)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SCR                      BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0_BPMP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0                   _MK_ADDR_CONST(0xa70048)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SCR                       BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0_BPMP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0                   _MK_ADDR_CONST(0xa7004c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0_BPMP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0                      _MK_ADDR_CONST(0xa70050)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_RESET_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_READ_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0_BPMP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0                 _MK_ADDR_CONST(0xa70054)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_READ_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0_BPMP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0                 _MK_ADDR_CONST(0xa70058)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                    31:31
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                        3:2
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0_BPMP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0                 _MK_ADDR_CONST(0xa7005c)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SCR                     BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_RESET_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_READ_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0_BPMP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 10944608 [0xa70060]

// Reserved address 10944612 [0xa70064]

// Reserved address 10944616 [0xa70068]

// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0                       _MK_ADDR_CONST(0xa7006c)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SCR                   BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0_BPMP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0                      _MK_ADDR_CONST(0xa70070)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SCR                  BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0_BPMP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0                      _MK_ADDR_CONST(0xa70074)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SCR                  BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0_BPMP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 10944632 [0xa70078]

// Reserved address 11010048 [0xa80000]

// Reserved address 11075584 [0xa90000]

// Reserved address 11141120 [0xaa0000]

// Reserved address 11206656 [0xab0000]

// Reserved address 11272192 [0xac0000]

// Reserved address 11337728 [0xad0000]

// Reserved address 11403264 [0xae0000]

// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0                  _MK_ADDR_CONST(0xaf0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SCR                      BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_SOC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_LCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_RANGE                 3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_BCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0_CLK_ENB_SIMON_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0                      _MK_ADDR_CONST(0xaf0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SCR                  BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_READ_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_SOC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_LCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_RANGE                 3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_BCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0_SET_CLK_ENB_SIMON_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0                      _MK_ADDR_CONST(0xaf0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SCR                  BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_SOC_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_RANGE                 2:2
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_LCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_RANGE                 3:3
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_BCPU_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_RANGE                  4:4
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0_CLR_CLK_ENB_SIMON_GPU_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0                  _MK_ADDR_CONST(0xaf1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SCR                      0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_RANGE                 1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_SOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_RANGE                        2:2
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_LCPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_RANGE                        3:3
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_BCPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_RANGE                 4:4
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0_BOND_OUT_SIMON_GPU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0                   _MK_ADDR_CONST(0xaf2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SCR                       BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_RESET_VAL                         _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_JTAG_TCK_IB                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_SRC_CLK_M                       _MK_ENUM_CONST(2)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0_SIMON_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0                    _MK_ADDR_CONST(0xaf8000)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SCR                        0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SHIFT                  _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SHIFT                  _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SHIFT                  _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SHIFT                  _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SHIFT                  _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SHIFT                  _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0                   _MK_ADDR_CONST(0xaf8004)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SCR                       0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_RANGE                     29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SHIFT                     _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_RANGE                     28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_RANGE                     27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SHIFT                   _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_RANGE                   26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SHIFT                 _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_RANGE                 23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SHIFT                 _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_RANGE                 22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SHIFT                 _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_RANGE                 21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_RANGE                 20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SHIFT                 _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_RANGE                 19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_RANGE                 18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SHIFT                 _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_RANGE                 17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_RANGE                 16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SHIFT                 _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_RANGE                 15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SHIFT                 _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_RANGE                 14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SHIFT                 _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_RANGE                 13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SHIFT                 _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_RANGE                 12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SHIFT                 _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_RANGE                 11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SHIFT                 _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_RANGE                 10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SHIFT                 _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_RANGE                 9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_RANGE                 8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SHIFT                 _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_RANGE                 7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SHIFT                 _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_RANGE                 6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SHIFT                 _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_RANGE                 5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_RANGE                 4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SHIFT                 _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_RANGE                 3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_RANGE                 2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_RANGE                 1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_RANGE                 0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SCR_THERM_0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0                     _MK_ADDR_CONST(0xaf8008)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_THERM_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0                      _MK_ADDR_CONST(0xaf800c)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SCR                  0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0                     _MK_ADDR_CONST(0xaf8010)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SCR                         0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0                        _MK_ADDR_CONST(0xb00000)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_NRESET_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0_SWR_AON_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0                    _MK_ADDR_CONST(0xb00004)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_NRESET_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0_SET_SWR_AON_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0                    _MK_ADDR_CONST(0xb00008)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0_CLR_SWR_AON_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0                    _MK_ADDR_CONST(0xb0000c)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SCR                        AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0_SWR_UFSHC_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0                        _MK_ADDR_CONST(0xb00010)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SCR                    AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0_SET_SWR_UFSHC_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0                        _MK_ADDR_CONST(0xb00014)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SCR                    AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0_CLR_SWR_UFSHC_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0                   _MK_ADDR_CONST(0xb00018)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SCR                       AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0_SWR_XUSB_VAUX_AON_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0                       _MK_ADDR_CONST(0xb0001c)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SCR                   AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0_SET_SWR_XUSB_VAUX_AON_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0                       _MK_ADDR_CONST(0xb00020)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SCR                   AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_RANGE                       0:0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0_CLR_SWR_XUSB_VAUX_AON_RST_ENABLE                      _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0                 _MK_ADDR_CONST(0xb00024)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SCR                     AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0_SWR_AON_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0                     _MK_ADDR_CONST(0xb00028)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0_SET_SWR_AON_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0                     _MK_ADDR_CONST(0xb0002c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0_CLR_SWR_AON_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0                       _MK_ADDR_CONST(0xb00030)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_0_SWR_AOPM_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0                   _MK_ADDR_CONST(0xb00034)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0_SET_SWR_AOPM_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0                   _MK_ADDR_CONST(0xb00038)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0_CLR_SWR_AOPM_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0                       _MK_ADDR_CONST(0xb0003c)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_0_SWR_AOVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0                   _MK_ADDR_CONST(0xb00040)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0_SET_SWR_AOVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0                   _MK_ADDR_CONST(0xb00044)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0_CLR_SWR_AOVC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0                    _MK_ADDR_CONST(0xb00048)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0_SWR_AON_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0                        _MK_ADDR_CONST(0xb0004c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0_SET_SWR_AON_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0                        _MK_ADDR_CONST(0xb00050)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0_CLR_SWR_AON_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0                   _MK_ADDR_CONST(0xb00054)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SCR                       AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0_SWR_AON_GPIO_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0                       _MK_ADDR_CONST(0xb00058)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SCR                   AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0_SET_SWR_AON_GPIO_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0                       _MK_ADDR_CONST(0xb0005c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SCR                   AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0_CLR_SWR_AON_GPIO_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0                    _MK_ADDR_CONST(0xb00060)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SCR                        AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0_SWR_AON_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0                        _MK_ADDR_CONST(0xb00064)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SCR                    AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0_SET_SWR_AON_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0                        _MK_ADDR_CONST(0xb00068)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SCR                    AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0_CLR_SWR_AON_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0                    _MK_ADDR_CONST(0xb01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0_CLK_ENB_AON_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0                        _MK_ADDR_CONST(0xb01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0_SET_CLK_ENB_AON_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0                        _MK_ADDR_CONST(0xb01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0_CLR_CLK_ENB_AON_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0                    _MK_ADDR_CONST(0xb02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0_BOND_OUT_AON_CPU_NIC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0                     _MK_ADDR_CONST(0xb03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_RESET_MASK                  _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_READ_MASK                   _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                        _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_NIC_RATE_0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0                       _MK_ADDR_CONST(0xb03004)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_RESET_VAL                     _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_RESET_MASK                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_READ_MASK                     _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_WRITE_MASK                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_RANGE                  4:4
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_RANGE                    1:0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_NIC_RATE_0_AON_NIC_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0                 _MK_ADDR_CONST(0xb03008)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_RANGE                    31:31
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_PG_EMULATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SHIFT)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_RANGE                      7:0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_DEFAULT                    _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0_AON_CPU_SOFTRST_LEGACY_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0                  _MK_ADDR_CONST(0xb0300c)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                        _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_RANGE                     4:0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_DEFAULT                   _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0_AON_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0                       _MK_ADDR_CONST(0xb10000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0_SWR_CAN1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0                   _MK_ADDR_CONST(0xb10004)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0_SET_SWR_CAN1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0                   _MK_ADDR_CONST(0xb10008)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0_CLR_SWR_CAN1_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0                   _MK_ADDR_CONST(0xb11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0_CLK_ENB_CAN1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0                       _MK_ADDR_CONST(0xb11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0_SET_CLK_ENB_CAN1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0                       _MK_ADDR_CONST(0xb11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0_CLR_CLK_ENB_CAN1_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0                   _MK_ADDR_CONST(0xb12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_HOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0_BOND_OUT_CAN1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0                    _MK_ADDR_CONST(0xb13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SCR                        AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0_CAN1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CAN1_CORE_RATE_0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0                     _MK_ADDR_CONST(0xb13004)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SCR                         AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_RESET_VAL                   _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_RESET_MASK                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_READ_MASK                   _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_WRITE_MASK                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_RANGE                      4:4
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_RANGE                        1:0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN1_CORE_RATE_0_CAN1_CORE_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0                       _MK_ADDR_CONST(0xb20000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0_SWR_CAN2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0                   _MK_ADDR_CONST(0xb20004)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0_SET_SWR_CAN2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0                   _MK_ADDR_CONST(0xb20008)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0_CLR_SWR_CAN2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0                   _MK_ADDR_CONST(0xb21000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_RESET_VAL                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_INIT_ENUM                       ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0_CLK_ENB_CAN2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0                       _MK_ADDR_CONST(0xb21004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0_SET_CLK_ENB_CAN2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0                       _MK_ADDR_CONST(0xb21008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SCR                   AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_RANGE                   1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_HOST_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0_CLR_CLK_ENB_CAN2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0                   _MK_ADDR_CONST(0xb22000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SCR                       AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_RANGE                  1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_HOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0_BOND_OUT_CAN2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0                    _MK_ADDR_CONST(0xb23000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SCR                        AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0_CAN2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CAN2_CORE_RATE_0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0                     _MK_ADDR_CONST(0xb23004)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SCR                         AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_RESET_VAL                   _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_RESET_MASK                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_READ_MASK                   _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_WRITE_MASK                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_RANGE                      4:4
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SHIFT)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_RANGE                        1:0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CAN2_CORE_RATE_0_CAN2_CORE_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_APB_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0                    _MK_ADDR_CONST(0xb30000)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_0_SWR_AON_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0                        _MK_ADDR_CONST(0xb30004)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0_SET_SWR_AON_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0                        _MK_ADDR_CONST(0xb30008)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0_CLR_SWR_AON_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0                        _MK_ADDR_CONST(0xb31000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0_CLK_ENB_AON_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0                    _MK_ADDR_CONST(0xb31004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0_SET_CLK_ENB_AON_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0                    _MK_ADDR_CONST(0xb31008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0_CLR_CLK_ENB_AON_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0                        _MK_ADDR_CONST(0xb32000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0_BOND_OUT_AON_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0                 _MK_ADDR_CONST(0xb33000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_RESET_MASK                      _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_READ_MASK                       _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SHIFT                        _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0                      _MK_ADDR_CONST(0xb40000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0                  _MK_ADDR_CONST(0xb40004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0                  _MK_ADDR_CONST(0xb40008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0                  _MK_ADDR_CONST(0xb41000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0                      _MK_ADDR_CONST(0xb41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0                      _MK_ADDR_CONST(0xb41008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SCR                  AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0_CLR_CLK_ENB_UARTC_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0                  _MK_ADDR_CONST(0xb42000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SCR                      AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   _MK_ADDR_CONST(0xb43000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SCR                       AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0                      _MK_ADDR_CONST(0xb50000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0_SWR_UARTG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0                  _MK_ADDR_CONST(0xb50004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0_SET_SWR_UARTG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0                  _MK_ADDR_CONST(0xb50008)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0_CLR_SWR_UARTG_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0                  _MK_ADDR_CONST(0xb51000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0_CLK_ENB_UARTG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0                      _MK_ADDR_CONST(0xb51004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0_SET_CLK_ENB_UARTG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0                      _MK_ADDR_CONST(0xb51008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SCR                  AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0_CLR_CLK_ENB_UARTG_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0                  _MK_ADDR_CONST(0xb52000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SCR                      AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0_BOND_OUT_UARTG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0                   _MK_ADDR_CONST(0xb53000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SCR                       AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_RESET_VAL                         _MK_MASK_CONST(0xe0000002)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_RESET_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_READ_MASK                         _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_WRITE_MASK                        _MK_MASK_CONST(0xe100ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0                  _MK_ADDR_CONST(0xb60000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SCR                      AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0                      _MK_ADDR_CONST(0xb60004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SCR                  AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0_SET_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0                      _MK_ADDR_CONST(0xb60008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SCR                  AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0_CLR_CLK_ENB_AON_UART_FST_MIPI_CAL_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0                  _MK_ADDR_CONST(0xb61000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SCR                      AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0_BOND_OUT_AON_UART_FST_MIPI_CAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0                   _MK_ADDR_CONST(0xb62000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SCR                       AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0_AON_UART_FST_MIPI_CAL_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0                       _MK_ADDR_CONST(0xb70000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0_SWR_I2C2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0                   _MK_ADDR_CONST(0xb70004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0_SET_SWR_I2C2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0                   _MK_ADDR_CONST(0xb70008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0_CLR_SWR_I2C2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0                   _MK_ADDR_CONST(0xb71000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0_CLK_ENB_I2C2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0                       _MK_ADDR_CONST(0xb71004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0_SET_CLK_ENB_I2C2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0                       _MK_ADDR_CONST(0xb71008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SCR                   AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0_CLR_CLK_ENB_I2C2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0                   _MK_ADDR_CONST(0xb72000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SCR                       AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    _MK_ADDR_CONST(0xb73000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SCR                        AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0                       _MK_ADDR_CONST(0xb80000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0_SWR_I2C8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0                   _MK_ADDR_CONST(0xb80004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0_SET_SWR_I2C8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0                   _MK_ADDR_CONST(0xb80008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0_CLR_SWR_I2C8_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0                   _MK_ADDR_CONST(0xb81000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0_CLK_ENB_I2C8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0                       _MK_ADDR_CONST(0xb81004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0_SET_CLK_ENB_I2C8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0                       _MK_ADDR_CONST(0xb81008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SCR                   AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0_CLR_CLK_ENB_I2C8_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0                   _MK_ADDR_CONST(0xb82000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SCR                       AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0_BOND_OUT_I2C8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0                    _MK_ADDR_CONST(0xb83000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SCR                        AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_RESET_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_READ_MASK                  _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_WRITE_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_RANGE                     15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0                      _MK_ADDR_CONST(0xb90000)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0_SWR_I2C10_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0                  _MK_ADDR_CONST(0xb90004)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0_SET_SWR_I2C10_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0                  _MK_ADDR_CONST(0xb90008)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0_CLR_SWR_I2C10_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0                  _MK_ADDR_CONST(0xb91000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0_CLK_ENB_I2C10_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0                      _MK_ADDR_CONST(0xb91004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0_SET_CLK_ENB_I2C10_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0                      _MK_ADDR_CONST(0xb91008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SCR                  AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0_CLR_CLK_ENB_I2C10_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0                  _MK_ADDR_CONST(0xb92000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SCR                      AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0_BOND_OUT_I2C10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0                   _MK_ADDR_CONST(0xb93000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SCR                       AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_RESET_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_WRITE_MASK                        _MK_MASK_CONST(0xe000ffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_RANGE                   15:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0                   _MK_ADDR_CONST(0xba0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SCR                       AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0_CLK_ENB_AON_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0                       _MK_ADDR_CONST(0xba0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SCR                   AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0_SET_CLK_ENB_AON_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0                       _MK_ADDR_CONST(0xba0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SCR                   AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0_CLR_CLK_ENB_AON_I2C_SLOW_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0                   _MK_ADDR_CONST(0xba1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SCR                       AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0_BOND_OUT_AON_I2C_SLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0                    _MK_ADDR_CONST(0xba2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SCR                        AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0                       _MK_ADDR_CONST(0xbb0000)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0_SWR_SPI2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0                   _MK_ADDR_CONST(0xbb0004)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0_SET_SWR_SPI2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0                   _MK_ADDR_CONST(0xbb0008)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0_CLR_SWR_SPI2_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0                   _MK_ADDR_CONST(0xbb1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0_CLK_ENB_SPI2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0                       _MK_ADDR_CONST(0xbb1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0_SET_CLK_ENB_SPI2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0                       _MK_ADDR_CONST(0xbb1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SCR                   AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0_CLR_CLK_ENB_SPI2_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0                   _MK_ADDR_CONST(0xbb2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SCR                       AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0_BOND_OUT_SPI2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0                    _MK_ADDR_CONST(0xbb3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SCR                        AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0                      _MK_ADDR_CONST(0xbc0000)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0_SWR_DMIC5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0                  _MK_ADDR_CONST(0xbc0004)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0_SET_SWR_DMIC5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0                  _MK_ADDR_CONST(0xbc0008)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0_CLR_SWR_DMIC5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0                  _MK_ADDR_CONST(0xbc1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0_CLK_ENB_DMIC5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0                      _MK_ADDR_CONST(0xbc1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0_SET_CLK_ENB_DMIC5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0                      _MK_ADDR_CONST(0xbc1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SCR                  AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0_CLR_CLK_ENB_DMIC5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0                  _MK_ADDR_CONST(0xbc2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SCR                      AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0_BOND_OUT_DMIC5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0                   _MK_ADDR_CONST(0xbc3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SCR                       AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0                      _MK_ADDR_CONST(0xbd0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SCR                  AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0_CLK_ENB_AON_TOUCH_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0                  _MK_ADDR_CONST(0xbd0004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SCR                      AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0_SET_CLK_ENB_AON_TOUCH_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0                  _MK_ADDR_CONST(0xbd0008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SCR                      AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0_CLR_CLK_ENB_AON_TOUCH_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0                      _MK_ADDR_CONST(0xbd1000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SCR                  AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0_BOND_OUT_AON_TOUCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0                       _MK_ADDR_CONST(0xbd2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SCR                   AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0_AON_TOUCH_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_BASE_0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0                        _MK_ADDR_CONST(0xbe0000)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SCR                    AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_RESET_VAL                      _MK_MASK_CONST(0x10108002)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_RESET_MASK                     _MK_MASK_CONST(0xfdf3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_READ_MASK                      _MK_MASK_CONST(0xfdf3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_WRITE_MASK                     _MK_MASK_CONST(0xf1f3fcff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_RANGE                    31:31
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_BYPASS_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_RANGE                    30:30
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_RANGE                   29:29
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_INIT_ENUM                       REF_ENABLE
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_REF_ENABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_REF_DIS_REF_DISABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_RANGE                 27:27
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT                      _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_RANGE                      26:26
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_RANGE                      24:20
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_RANGE                      17:10
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_DEFAULT                    _MK_MASK_CONST(0x20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_RANGE                      7:0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_DEFAULT                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_0_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0                      _MK_ADDR_CONST(0xbe0004)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_RESET_VAL                    _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_RESET_MASK                   _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_READ_MASK                    _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_WRITE_MASK                   _MK_MASK_CONST(0x400ffffb)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SHIFT                   _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_RANGE                   30:30
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_ENABLE                  _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_RANGE                 19:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_EXT_FRU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_RANGE                     3:3
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_PTS_FO                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_RANGE                       1:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_LOOP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_1_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0                      _MK_ADDR_CONST(0xbe0008)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_RESET_VAL                    _MK_MASK_CONST(0x8000000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_RESET_MASK                   _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_READ_MASK                    _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_WRITE_MASK                   _MK_MASK_CONST(0x80fffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SHIFT                    _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_RANGE                    27:27
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_OFF                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_ON                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_RANGE                      19:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_EXT_SUBINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_2_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0                      _MK_ADDR_CONST(0xbe000c)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_RESET_VAL                    _MK_MASK_CONST(0x1f020005)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_RESET_MASK                   _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_READ_MASK                    _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff17)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_RANGE                      31:24
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_RANGE                        23:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_PLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_RANGE                      15:8
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_LD_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_RANGE                 4:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_RANGE                        2:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_DEFAULT                      _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_2_0_PLLAON_FLL_FRUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_3_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0                      _MK_ADDR_CONST(0xbe0010)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_RESET_VAL                    _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_READ_MASK                    _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff3f)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_RANGE                    25:24
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_VREG10V_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_RANGE                   23:8
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_RANGE                    5:4
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_LDIV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_RANGE                      3:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_DEFAULT                    _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_3_0_PLLAON_PLL_LD_TOL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLLAON_MISC_4_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0                      _MK_ADDR_CONST(0xbe0014)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SCR                  AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_RESET_VAL                    _MK_MASK_CONST(0x1c00000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_RESET_MASK                   _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_READ_MASK                    _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_WRITE_MASK                   _MK_MASK_CONST(0x1fffffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_RANGE                        28:28
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SHIFT                   _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_RANGE                   27:25
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_RANGE                   24:22
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_RANGE                   21:19
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_KP_STEP_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_RANGE                 18:16
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_TIMER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SHIFT)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_RANGE                       15:0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_FRAC_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_OSC_CTRL_0
#define CLK_RST_CONTROLLER_OSC_CTRL_0                   _MK_ADDR_CONST(0xbf0000)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SCR                       AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x50000011)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xfffdf3f5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:28
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  _MK_MASK_CONST(0x5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_INIT_ENUM                        OSC38P4
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC13                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC19P2                  _MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC12                    _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC26                    _MK_ENUM_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC16P8                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC38P4                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC48                    _MK_ENUM_CONST(9)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 _MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 27:26
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV1                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV2                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DIV4                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RESERVED                      _MK_ENUM_CONST(3)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 25:18
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_RANGE                      2:2
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_CLK_OK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_M_DIVIDE_0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0                       _MK_ADDR_CONST(0xbf0004)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SCR                   AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_RESET_MASK                    _MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_READ_MASK                     _MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_WRITE_MASK                    _MK_MASK_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_RANGE                   3:2
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_M_DIVIDE_0_CLK_M_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3)


// Register CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0                  _MK_ADDR_CONST(0xbf0008)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SCR                      AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_RESET_VAL                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_RANGE                      1:1
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SHIFT)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_RANGE                  0:0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0_AO_PMC2ALL_OSC_STABLE_OVR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0xbf000c)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SCR                   AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    _MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     _MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    _MK_MASK_CONST(0x8000000f)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        _MK_ADDR_CONST(0xbf0010)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SCR                    AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_MISC_REG0_0
#define CLK_RST_CONTROLLER_MISC_REG0_0                  _MK_ADDR_CONST(0xbf0014)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_MISC_REG0_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_MISC_REG0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_MISC_REG0_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SHIFT)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_RANGE                  0:0
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_MISC_REG0_0_GLOBAL_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0                       _MK_ADDR_CONST(0xc00000)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_0_SWR_PWM4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0                   _MK_ADDR_CONST(0xc00004)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0_SET_SWR_PWM4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0                   _MK_ADDR_CONST(0xc00008)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0_CLR_SWR_PWM4_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0                   _MK_ADDR_CONST(0xc01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0_CLK_ENB_PWM4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0                       _MK_ADDR_CONST(0xc01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0_SET_CLK_ENB_PWM4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0                       _MK_ADDR_CONST(0xc01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SCR                   AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0_CLR_CLK_ENB_PWM4_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0                   _MK_ADDR_CONST(0xc02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SCR                       AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0_BOND_OUT_PWM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0                    _MK_ADDR_CONST(0xc03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SCR                        AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0_PWM4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0                   _MK_ADDR_CONST(0xc10000)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SCR                       AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0_SWR_TSCTNAON_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0                       _MK_ADDR_CONST(0xc10004)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SCR                   AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0_SET_SWR_TSCTNAON_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0                       _MK_ADDR_CONST(0xc10008)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SCR                   AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0_CLR_SWR_TSCTNAON_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0                    _MK_ADDR_CONST(0xc1000c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0_SWR_AON_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0                        _MK_ADDR_CONST(0xc10010)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0_SET_SWR_AON_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0                        _MK_ADDR_CONST(0xc10014)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0_CLR_SWR_AON_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0                    _MK_ADDR_CONST(0xc10018)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0_SWR_AON_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0                        _MK_ADDR_CONST(0xc1001c)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0_SET_SWR_AON_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0                        _MK_ADDR_CONST(0xc10020)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0_CLR_SWR_AON_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0                    _MK_ADDR_CONST(0xc11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SCR                        AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0_CLK_ENB_TSC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0                        _MK_ADDR_CONST(0xc11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SCR                    AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0_SET_CLK_ENB_TSC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0                        _MK_ADDR_CONST(0xc11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SCR                    AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0_CLR_CLK_ENB_TSC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0                    _MK_ADDR_CONST(0xc12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SCR                        AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0_BOND_OUT_TSC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0                     _MK_ADDR_CONST(0xc13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SCR                         AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0_TSC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0                   _MK_ADDR_CONST(0xc13004)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SCR                       AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_RESET_VAL                         _MK_MASK_CONST(0x802702ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_RESET_MASK                        _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_READ_MASK                         _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_WRITE_MASK                        _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_RANGE                        31:31
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_INIT_ENUM                    ENABLE
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_ENB_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_FIELD                   _MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_RANGE                   21:12
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x270)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_FIELD                    _MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_RANGE                    9:0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x2ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0_SUPER_TSC_HS_DIV_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0                  _MK_ADDR_CONST(0xc13008)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SCR                      AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_RESET_VAL                        _MK_MASK_CONST(0x802702ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_RESET_MASK                       _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_READ_MASK                        _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_WRITE_MASK                       _MK_MASK_CONST(0x803ff3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_RANGE                      31:31
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_ENB_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_FIELD                 _MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_RANGE                 21:12
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x270)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_FIELD                  _MK_FIELD_CONST(0x3ff, CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_RANGE                  9:0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x2ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0_SUPER_TSC_OSC_DIV_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0                  _MK_ADDR_CONST(0xc1300c)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SCR                      AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xc0000707)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_INIT_ENUM                     TSC_HS_REF_CLK
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_TSC_HS_REF_CLK                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_TSC_OSC_REF_CLK                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SHIFT                    _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_RANGE                    30:30
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_REF_CLK_SOURCE_OVRD_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SHIFT                 _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_RANGE                 10:10
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_VAL_ENABLE                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_RANGE                      9:9
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_RANGE                        8:8
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_OSC_ADJUST_OVRD_ENABLE                       _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_RANGE                  2:2
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_VAL_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_RANGE                       1:1
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SHIFT)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_RANGE                 0:0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_INIT_ENUM                     DISABLE
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_DISABLE                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0_TSC_HS_ADJUST_OVRD_ENABLE                        _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0                    _MK_ADDR_CONST(0xc20000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SCR                        AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0_CLK_ENB_MSS_ENCRYPT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0                        _MK_ADDR_CONST(0xc20004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SCR                    AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0_SET_CLK_ENB_MSS_ENCRYPT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0                        _MK_ADDR_CONST(0xc20008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SCR                    AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0_CLR_CLK_ENB_MSS_ENCRYPT_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0                    _MK_ADDR_CONST(0xc21000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SCR                        AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0_BOND_OUT_MSS_ENCRYPT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0                     _MK_ADDR_CONST(0xc22000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SCR                         AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0_MSS_ENCRYPT_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0                      _MK_ADDR_CONST(0xc30000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0_AON_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                       _MK_ADDR_CONST(0xc30004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_AON_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xc30008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_AON_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0                   _MK_ADDR_CONST(0xc3000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0_AON_CPU_NIC_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xc30010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_AON_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0                   _MK_ADDR_CONST(0xc30014)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0_AON_CPU_NIC_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                     _MK_ADDR_CONST(0xc30018)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                         AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_AON_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0                        _MK_ADDR_CONST(0xc3001c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0_AON_CPU_NIC_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0                 _MK_ADDR_CONST(0xc30020)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0_AON_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0                  _MK_ADDR_CONST(0xc30024)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0_AON_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xc30028)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0_AON_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0                      _MK_ADDR_CONST(0xc3002c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0_AON_PLL_IDLE_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xc30030)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0_AON_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0                      _MK_ADDR_CONST(0xc30034)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0_AON_PLL_STBY_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xc30038)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0_AON_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0                   _MK_ADDR_CONST(0xc3003c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0_AON_PLL_DORMANT_DEEP_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0                  _MK_ADDR_CONST(0xc30040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_RESET_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_READ_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0_AON_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0                   _MK_ADDR_CONST(0xc30044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0_AON_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0                    _MK_ADDR_CONST(0xc30048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0_AON_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0                       _MK_ADDR_CONST(0xc3004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0_AON_APB_IDLE_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0                    _MK_ADDR_CONST(0xc30050)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0_AON_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0                       _MK_ADDR_CONST(0xc30054)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0_AON_APB_STBY_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0                 _MK_ADDR_CONST(0xc30058)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                     AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0_AON_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0                    _MK_ADDR_CONST(0xc3005c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0_AON_APB_DORMANT_DEEP_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0                  _MK_ADDR_CONST(0xc30060)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0_AON_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   _MK_ADDR_CONST(0xc30064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_AON_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0                    _MK_ADDR_CONST(0xc30068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0_AON_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0                       _MK_ADDR_CONST(0xc3006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0_AON_CPU_NIC_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0                    _MK_ADDR_CONST(0xc30070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0_AON_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0                       _MK_ADDR_CONST(0xc30074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0_AON_CPU_NIC_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0                 _MK_ADDR_CONST(0xc30078)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                     AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0_AON_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0                    _MK_ADDR_CONST(0xc3007c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0_AON_CPU_NIC_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0                     _MK_ADDR_CONST(0xc30080)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0                      _MK_ADDR_CONST(0xc30084)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SCR                  AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0                       _MK_ADDR_CONST(0xc30088)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0                  _MK_ADDR_CONST(0xc3008c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0                       _MK_ADDR_CONST(0xc30090)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0                  _MK_ADDR_CONST(0xc30094)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SCR                      AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0                    _MK_ADDR_CONST(0xc30098)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SCR                        AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0                       _MK_ADDR_CONST(0xc3009c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0                      _MK_ADDR_CONST(0xc300a0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SCR                  AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_pllAON_out                    _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0_AON_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0                       _MK_ADDR_CONST(0xc300a4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SCR                   AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0_AON_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0                        _MK_ADDR_CONST(0xc300a8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0_AON_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0                   _MK_ADDR_CONST(0xc300ac)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0_AON_APB_IDLE_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0                        _MK_ADDR_CONST(0xc300b0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0_AON_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0                   _MK_ADDR_CONST(0xc300b4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_pllAON_out                      _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0_AON_APB_STBY_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0                     _MK_ADDR_CONST(0xc300b8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SCR                         AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_pllAON_out                  _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0_AON_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0                        _MK_ADDR_CONST(0xc300bc)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SCR                    AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_pllAON_out                        _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0_AON_APB_DORMANT_DEEP_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0                   _MK_ADDR_CONST(0xc300c0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SCR                       AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                        _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_READ_MASK                         _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                        _MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_RANGE                      31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_RANGE                      30:30
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_RANGE                    2:0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0                      _MK_ADDR_CONST(0xc300c4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SCR                  AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_RESET_VAL                    _MK_MASK_CONST(0x1c30)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SHIFT                       _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_RANGE                       12:12
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                 _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                 9:9
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_RANGE                       8:8
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_RANGE                 7:7
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_RANGE                       4:4
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_RANGE                       3:3
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_SWDIV_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_RESET_PLL_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0                        _MK_ADDR_CONST(0xc300c8)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SCR                    AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_RESET_VAL                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_READ_MASK                      _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SHIFT                  _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_RANGE                  30:30
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_FIELD                    _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_RANGE                    11:0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_DEFAULT                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0_AON_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0                   _MK_ADDR_CONST(0xc300cc)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                         _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_RANGE                     31:31
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_FIELD                    _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_RANGE                    11:0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_DEFAULT                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0_AON_PLL_DLY_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0                  _MK_ADDR_CONST(0xc300d0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_RANGE                  11:0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0_AON_PLL_DLY_PWRUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0                       _MK_ADDR_CONST(0xc300d4)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                   AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                     _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                      31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_RANGE                  11:0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0_AON_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0                  _MK_ADDR_CONST(0xc300d8)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                      AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_FIELD                       _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_RANGE                       11:0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0_AON_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0                    _MK_ADDR_CONST(0xc300dc)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SCR                        AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_FIELD                        _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_RANGE                        5:0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                      _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0_AON_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0                   _MK_ADDR_CONST(0xc300e0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SCR                       AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_RANGE                        3:3
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_RANGE                    2:0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0_AON_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0                     _MK_ADDR_CONST(0xc300e4)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SCR                         AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_RANGE                 31:31
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_RANGE                        30:30
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_RANGE                        7:4
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_RANGE                      3:0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_STATUS_0_AON_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0                      _MK_ADDR_CONST(0xc300e8)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_WRITE_MASK                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_RANGE                 31:31
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_EN_SEQ_DBG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_FIELD                     _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_RANGE                     11:0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0_AON_LAST_SEQ_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 12845056 [0xc40000]

// Reserved address 12910592 [0xc50000]

// Reserved address 12976128 [0xc60000]

// Reserved address 13041664 [0xc70000]

// Reserved address 13107200 [0xc80000]

// Reserved address 13172736 [0xc90000]

// Reserved address 13238272 [0xca0000]

// Reserved address 13303808 [0xcb0000]

// Reserved address 13369344 [0xcc0000]

// Reserved address 13434880 [0xcd0000]

// Reserved address 13500416 [0xce0000]

// Reserved address 13565952 [0xcf0000]

// Register CLK_RST_CONTROLLER_AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0                     _MK_ADDR_CONST(0xcf8000)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SCR                         0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0                    _MK_ADDR_CONST(0xcf8004)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SCR                        0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SHIFT                  _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SHIFT                  _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SHIFT                  _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SHIFT                  _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SHIFT                  _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SHIFT                  _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0                       _MK_ADDR_CONST(0xcf8008)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_CAN_0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0                        _MK_ADDR_CONST(0xcf800c)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_CAN_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_DMIC5_0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0                      _MK_ADDR_CONST(0xcf8010)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_DMIC5_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_GPIO_0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0                       _MK_ADDR_CONST(0xcf8014)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_GPIO_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_HSP_0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0                        _MK_ADDR_CONST(0xcf8018)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_HSP_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C10_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0                      _MK_ADDR_CONST(0xcf801c)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C10_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C2_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0                       _MK_ADDR_CONST(0xcf8020)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C2_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_I2C8_0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0                       _MK_ADDR_CONST(0xcf8024)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_I2C8_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0                        _MK_ADDR_CONST(0xcf8028)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_OSC_0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0                        _MK_ADDR_CONST(0xcf802c)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_OSC_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_PLLAON_0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0                     _MK_ADDR_CONST(0xcf8030)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SCR                         0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PLLAON_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_PWM4_0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0                       _MK_ADDR_CONST(0xcf8034)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_PWM4_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_SPI2_0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0                       _MK_ADDR_CONST(0xcf8038)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SCR                   0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_SPI2_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_TSC_0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0                        _MK_ADDR_CONST(0xcf803c)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TSC_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_UARTC_0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0                      _MK_ADDR_CONST(0xcf8040)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTC_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_UARTG_0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0                      _MK_ADDR_CONST(0xcf8044)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UARTG_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0                      _MK_ADDR_CONST(0xcf8048)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_UFS_0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0                        _MK_ADDR_CONST(0xcf804c)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SCR                    0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_RANGE                  29:29
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_RANGE                  28:28
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_RANGE                  27:27
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_RANGE                        26:24
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_RANGE                      23:23
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_RANGE                      22:22
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_RANGE                      21:21
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_RANGE                      20:20
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_RANGE                      19:19
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_RANGE                      18:18
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_RANGE                      17:17
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_RANGE                      16:16
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_RANGE                      15:15
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_RANGE                      14:14
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_RANGE                      13:13
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_RANGE                      12:12
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_RANGE                      11:11
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_RANGE                      10:10
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_RANGE                      9:9
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_RANGE                      8:8
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_RANGE                      7:7
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_RANGE                      6:6
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_RANGE                      5:5
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_RANGE                      4:4
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_RANGE                      3:3
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_RANGE                      2:2
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_RANGE                      1:1
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_RANGE                      0:0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_UFS_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0                      _MK_ADDR_CONST(0xcf8050)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SCR                  0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_RANGE                        29:29
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_RANGE                        28:28
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_RANGE                        27:27
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_RANGE                      26:24
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_RANGE                    23:23
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_RANGE                    22:22
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_RANGE                    21:21
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_RANGE                    20:20
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_RANGE                    19:19
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_RANGE                    18:18
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_RANGE                    17:17
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_RANGE                    16:16
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_RANGE                    15:15
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_RANGE                    14:14
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_RANGE                    13:13
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_RANGE                    12:12
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_RANGE                    11:11
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_RANGE                    10:10
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_RANGE                    9:9
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_RANGE                    8:8
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_RANGE                    7:7
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_RANGE                    6:6
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_RANGE                    5:5
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_RANGE                    4:4
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_RANGE                    3:3
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_RANGE                    2:2
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_RANGE                    1:1
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_RANGE                    0:0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AON_SCR_TOUCH_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0                        _MK_ADDR_CONST(0xd00000)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_NRESET_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0_SWR_SCE_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0                    _MK_ADDR_CONST(0xd00004)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_RANGE                       2:2
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_INIT_ENUM                   DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_DISABLE                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_NRESET_RST_ENABLE                      _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0_SET_SWR_SCE_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0                    _MK_ADDR_CONST(0xd00008)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1b)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_RANGE                  4:4
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NIC_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_RANGE                  3:3
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_INIT_ENUM                      DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_NSYSPORESET_RST_ENABLE                 _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_RANGE                    1:1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_DBGRESETN_RST_ENABLE                   _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_RANGE                   0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_INIT_ENUM                       DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_DISABLE                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0_CLR_SWR_SCE_PRESETDBGN_RST_ENABLE                  _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0                 _MK_ADDR_CONST(0xd0000c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0_SWR_SCE_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0                     _MK_ADDR_CONST(0xd00010)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0_SET_SWR_SCE_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0                     _MK_ADDR_CONST(0xd00014)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0_CLR_SWR_SCE_ACTMON_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0                     _MK_ADDR_CONST(0xd00018)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0_SWR_SCE_PM_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0                 _MK_ADDR_CONST(0xd0001c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0_SET_SWR_SCE_PM_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0                 _MK_ADDR_CONST(0xd00020)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_RANGE                        0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0_CLR_SWR_SCE_PM_RST_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0                    _MK_ADDR_CONST(0xd00024)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0_SWR_SCE_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0                        _MK_ADDR_CONST(0xd00028)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0_SET_SWR_SCE_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0                        _MK_ADDR_CONST(0xd0002c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0_CLR_SWR_SCE_DMA_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0                    _MK_ADDR_CONST(0xd00030)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0_SWR_SCE_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0                        _MK_ADDR_CONST(0xd00034)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0_SET_SWR_SCE_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0                        _MK_ADDR_CONST(0xd00038)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0_CLR_SWR_SCE_HSP_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0                   _MK_ADDR_CONST(0xd0003c)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0_SWR_TSCTNSCE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0                       _MK_ADDR_CONST(0xd00040)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0_SET_SWR_TSCTNSCE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0                       _MK_ADDR_CONST(0xd00044)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_INIT_ENUM                        DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0_CLR_SWR_TSCTNSCE_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0                    _MK_ADDR_CONST(0xd00048)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0_SWR_SCE_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0                        _MK_ADDR_CONST(0xd0004c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0_SET_SWR_SCE_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0                        _MK_ADDR_CONST(0xd00050)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0_CLR_SWR_SCE_TKE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0                    _MK_ADDR_CONST(0xd00054)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0_SWR_SCE_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0                        _MK_ADDR_CONST(0xd00058)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0_SET_SWR_SCE_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0                        _MK_ADDR_CONST(0xd0005c)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0_CLR_SWR_SCE_GTE_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0                    _MK_ADDR_CONST(0xd00060)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0_SWR_SCE_CFG_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0                        _MK_ADDR_CONST(0xd00064)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0_SET_SWR_SCE_CFG_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0                        _MK_ADDR_CONST(0xd00068)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0_CLR_SWR_SCE_CFG_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0                    _MK_ADDR_CONST(0xd01000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_RESET_VAL                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_INIT_ENUM                  ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0_CLK_ENB_SCE_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0                        _MK_ADDR_CONST(0xd01004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0_SET_CLK_ENB_SCE_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0                        _MK_ADDR_CONST(0xd01008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SHIFT                      _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_RANGE                      1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_ENABLE                     _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0_CLR_CLK_ENB_SCE_CPU_NIC_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0                    _MK_ADDR_CONST(0xd02000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SCR                        0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_RANGE                     1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0_BOND_OUT_SCE_CPU_NIC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0                     _MK_ADDR_CONST(0xd03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_RESET_MASK                  _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_READ_MASK                   _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT                        _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0_SCE_CPU_NIC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NIC_RATE_0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0                       _MK_ADDR_CONST(0xd03004)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_RESET_VAL                     _MK_MASK_CONST(0x10)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_RESET_MASK                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_READ_MASK                     _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_WRITE_MASK                    _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_RANGE                  4:4
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_RANGE                    1:0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NIC_RATE_0_SCE_NIC_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0                  _MK_ADDR_CONST(0xd03008)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_RESET_VAL                        _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_RANGE                     4:0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_DEFAULT                   _MK_MASK_CONST(0xa)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0_SCE_NRESET_CYCLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0                    _MK_ADDR_CONST(0xd10000)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0_SWR_SCE_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0                        _MK_ADDR_CONST(0xd10004)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0_SET_SWR_SCE_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0                        _MK_ADDR_CONST(0xd10008)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0_CLR_SWR_SCE_APB_RST_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0                        _MK_ADDR_CONST(0xd11000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_RESET_VAL                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0_CLK_ENB_SCE_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0                    _MK_ADDR_CONST(0xd11004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0_SET_CLK_ENB_SCE_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0                    _MK_ADDR_CONST(0xd11008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_RANGE                  0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0_CLR_CLK_ENB_SCE_APB_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0                        _MK_ADDR_CONST(0xd12000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_SCR                    0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_RANGE                 0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0_BOND_OUT_SCE_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0                 _MK_ADDR_CONST(0xd13000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_RESET_MASK                      _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_READ_MASK                       _MK_MASK_CONST(0xe00200ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_SHIFT                        _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_RANGE                        17:17
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_SWITCH_DIVIDE_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0_SCE_APB_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0                      _MK_ADDR_CONST(0xd20000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCR                  SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_RESET_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_READ_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_WRITE_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_DFLL_SCE                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0_SCE_CPU_NIC_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0                       _MK_ADDR_CONST(0xd20004)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                   SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                    _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xd20008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0_SCE_CPU_NIC_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xd2000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0_SCE_CPU_NIC_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0                     _MK_ADDR_CONST(0xd20010)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCR                         SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                   _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                        _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0_SCE_CPU_NIC_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0                 _MK_ADDR_CONST(0xd20014)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0_SCE_PLL_ACTIVE_OVR_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0                  _MK_ADDR_CONST(0xd20018)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_PLL_ACTIVE_IRQFIQ_OVR_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xd2001c)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0_SCE_PLL_IDLE_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0                   _MK_ADDR_CONST(0xd20020)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0_SCE_PLL_STBY_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0                        _MK_ADDR_CONST(0xd20024)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCR                    SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0_SCE_PLL_DORMANT_SHALLOW_OVR_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0                  _MK_ADDR_CONST(0xd20028)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCR                      SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_RESET_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_READ_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_WRITE_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_DFLL_SCE                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_RANGE                  16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0_SCE_APB_ACTIVE_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0                   _MK_ADDR_CONST(0xd2002c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCR                       SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_RESET_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_READ_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_WRITE_MASK                        _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_RANGE                    16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0_SCE_APB_ACTIVE_IRQFIQ_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0                    _MK_ADDR_CONST(0xd20030)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0_SCE_APB_IDLE_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0                    _MK_ADDR_CONST(0xd20034)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCR                        SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_RESET_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_READ_MASK                  _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_WRITE_MASK                         _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_RANGE                      16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0_SCE_APB_STBY_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0                 _MK_ADDR_CONST(0xd20038)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCR                     SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_RESET_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_READ_MASK                       _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_WRITE_MASK                      _MK_MASK_CONST(0xe00100ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_DFLL_SCE                        _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_RANGE                        16:16
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0_SCE_APB_DORMANT_SHALLOW_OVR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0                  _MK_ADDR_CONST(0xd2003c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_RESET_VAL                        _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_RESET_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_READ_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_WRITE_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_DFLL_SCE                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0_SCE_CPU_NIC_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   _MK_ADDR_CONST(0xd20040)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                         _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_READ_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                        _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0_SCE_CPU_NIC_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0                    _MK_ADDR_CONST(0xd20044)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0_SCE_CPU_NIC_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0                    _MK_ADDR_CONST(0xd20048)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0_SCE_CPU_NIC_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0                 _MK_ADDR_CONST(0xd2004c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCR                     SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_SCE                        _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0_SCE_CPU_NIC_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0                     _MK_ADDR_CONST(0xd20050)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0_SCE_PLL_ACTIVE_PLL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0                      _MK_ADDR_CONST(0xd20054)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCR                  SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0_SCE_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0                       _MK_ADDR_CONST(0xd20058)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0_SCE_PLL_IDLE_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0                       _MK_ADDR_CONST(0xd2005c)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0_SCE_PLL_STBY_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0                    _MK_ADDR_CONST(0xd20060)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0_SCE_PLL_DORMANT_SHALLOW_PLL_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0                      _MK_ADDR_CONST(0xd20064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCR                  SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_RANGE                 31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_INIT_ENUM                     CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_PLLBPMPCAM_OUT                        _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_DFLL_SCE                  _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_S                 _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_SRC_CLK_M                 _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_RANGE                     7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0_SCE_APB_ACTIVE_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0                       _MK_ADDR_CONST(0xd20068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_VAL                     _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_PLLBPMPCAM_OUT                  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_DFLL_SCE                    _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0_SCE_APB_ACTIVE_IRQFIQ_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0                        _MK_ADDR_CONST(0xd2006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0_SCE_APB_IDLE_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0                        _MK_ADDR_CONST(0xd20070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_RESET_VAL                      _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_RESET_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_READ_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_WRITE_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_RANGE                     31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_INIT_ENUM                 CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_DFLL_SCE                      _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_S                     _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_SRC_CLK_M                     _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_RANGE                 7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0_SCE_APB_STBY_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0                     _MK_ADDR_CONST(0xd20074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_RESET_VAL                   _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_RESET_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_READ_MASK                   _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_WRITE_MASK                  _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_PLLBPMPCAM_OUT                      _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_DFLL_SCE                        _MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_SRC_CLK_M                       _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0_SCE_APB_DORMANT_SHALLOW_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0                   _MK_ADDR_CONST(0xd20078)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_RESET_MASK                        _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_READ_MASK                         _MK_MASK_CONST(0xc0000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_WRITE_MASK                        _MK_MASK_CONST(0x40000007)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_RANGE                      31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SHIFT                      _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_RANGE                      30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_RANGE                    2:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0_SCE_SW_TGT_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0                      _MK_ADDR_CONST(0xd2007c)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCR                  SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_RESET_VAL                    _MK_MASK_CONST(0x1c30)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_SHIFT                       _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_RANGE                       12:12
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_RANGE                   11:11
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_ASYNC_OVR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_RANGE                     10:10
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_DISABLE_PLL_HW_CONTROL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT                 _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_RANGE                 9:9
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_CONFIG_PROPAGATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_RANGE                       8:8
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_BYP_PLL_CONFIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_RANGE                 7:7
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_SEQUENCER_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_RANGE                   6:6
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_PLL_SEQUENCER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_RANGE                   5:5
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_CPU_NIC_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_RANGE                       4:4
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_APB_SWDIV_DIS_HWCTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SHIFT                       _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_RANGE                       3:3
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SEQUENCER_INTF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_SWDIV_RST_ACK_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_RANGE                    1:1
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_SWDIV_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_RANGE                      0:0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0_SCE_RESET_PLL_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0                        _MK_ADDR_CONST(0xd20080)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCR                    SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_RESET_VAL                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_READ_MASK                      _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xe0000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_RANGE                  31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SHIFT                  _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_RANGE                  30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_CAR_SEQ_INTR_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_RANGE                       29:29
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_ACK_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_FIELD                    _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_RANGE                    11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_DEFAULT                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0_SCE_SEQ_TIMEOUT_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0                   _MK_ADDR_CONST(0xd20084)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_VAL                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_READ_MASK                         _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_RANGE                     31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_WAIT_PROG_DELAY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_FIELD                    _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_RANGE                    11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_DEFAULT                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0_SCE_PLL_DLY_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0                  _MK_ADDR_CONST(0xd20088)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_RANGE                  11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0_SCE_PLL_DLY_PWRUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0                       _MK_ADDR_CONST(0xd2008c)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCR                   SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_VAL                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_READ_MASK                     _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_RANGE                      31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_SWDIVCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_FIELD                  _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_RANGE                  11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_DEFAULT                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0_SCE_SWDIV_DLY_SWDIVCFG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0                  _MK_ADDR_CONST(0xd20090)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCR                      SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_READ_MASK                        _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_RANGE                   31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_PLLCFG_WAIT_PROG_DELAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_FIELD                       _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_RANGE                       11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0_SCE_SWDIV_DLY_PLLCFG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0                    _MK_ADDR_CONST(0xd20094)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCR                        SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_FIELD                        _MK_FIELD_CONST(0x3f, CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_RANGE                        5:0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT                      _MK_MASK_CONST(0x13)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0_SCE_SEQUENCER_1USEC_OSC_CYCLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0                   _MK_ADDR_CONST(0xd20098)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCR                       SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_RANGE                        3:3
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_RANGE                    2:0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0_SCE_SEQ_MODE_SEL_OVR_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0                     _MK_ADDR_CONST(0xd2009c)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCR                         SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_RANGE                 31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SM_SWDIV_BUSY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SHIFT                        _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_RANGE                        30:30
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CONFIGURED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SHIFT                        _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_RANGE                        7:4
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_PLL_CURR_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_RANGE                      3:0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0_SCE_SEQ_SWDIV_CURR_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0                      _MK_ADDR_CONST(0xd200a0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCR                  0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_RESET_MASK                   _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_READ_MASK                    _MK_MASK_CONST(0x80000fff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_WRITE_MASK                   _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_RANGE                 31:31
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_EN_SEQ_DBG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_FIELD                     _MK_FIELD_CONST(0xfff, CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_RANGE                     11:0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0_SCE_LAST_SEQ_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0                     _MK_ADDR_CONST(0xd30000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x82)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_READ_MASK                   _MK_MASK_CONST(0x100ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_RANGE                       7:7
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0_SCE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0                    _MK_ADDR_CONST(0xd30004)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_RESET_VAL                  _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_RESET_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_READ_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_WRITE_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0_SCE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0                     _MK_ADDR_CONST(0xd30008)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0_SCE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0                     _MK_ADDR_CONST(0xd3000c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0_SCE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0                    _MK_ADDR_CONST(0xd30010)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_FIELD                        _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0_SCE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0                    _MK_ADDR_CONST(0xd30014)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_READ_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0_SCE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0                     _MK_ADDR_CONST(0xd30018)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCR                         SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0_SCE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0                        _MK_ADDR_CONST(0xd3001c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCR                    SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_RESET_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_READ_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_WRITE_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0_SCE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0                 _MK_ADDR_CONST(0xd30020)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCR                     SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0_SCE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 13828132 [0xd30024]

// Reserved address 13828136 [0xd30028]

// Reserved address 13828140 [0xd3002c]

// Reserved address 13828144 [0xd30030]

// Reserved address 13828148 [0xd30034]

// Reserved address 13828152 [0xd30038]

// Reserved address 13828156 [0xd3003c]

// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0                   _MK_ADDR_CONST(0xd30040)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCR                       SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0_SCE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0                   _MK_ADDR_CONST(0xd30044)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCR                       SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0_SCE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0                    _MK_ADDR_CONST(0xd30048)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCR                        SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0_SCE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0                    _MK_ADDR_CONST(0xd3004c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0_SCE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0                       _MK_ADDR_CONST(0xd30050)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_RESET_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_READ_MASK                     _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0_SCE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0                  _MK_ADDR_CONST(0xd30054)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_READ_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0_SCE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0                  _MK_ADDR_CONST(0xd30058)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                      31:31
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                  3:2
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0_SCE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0                  _MK_ADDR_CONST(0xd3005c)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCR                      SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_RESET_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_READ_MASK                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0_SCE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 13828192 [0xd30060]

// Reserved address 13828196 [0xd30064]

// Reserved address 13828200 [0xd30068]

// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0                        _MK_ADDR_CONST(0xd3006c)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCR                    SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_READ_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0_SCE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0                       _MK_ADDR_CONST(0xd30070)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCR                   SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_FIELD                      _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0_SCE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0                       _MK_ADDR_CONST(0xd30074)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCR                   SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0_SCE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 13828216 [0xd30078]

// Reserved address 13893632 [0xd40000]

// Reserved address 13959168 [0xd50000]

// Reserved address 14024704 [0xd60000]

// Reserved address 14090240 [0xd70000]

// Reserved address 14155776 [0xd80000]

// Reserved address 14221312 [0xd90000]

// Reserved address 14286848 [0xda0000]

// Reserved address 14352384 [0xdb0000]

// Reserved address 14417920 [0xdc0000]

// Reserved address 14483456 [0xdd0000]

// Reserved address 14548992 [0xde0000]

// Reserved address 14614528 [0xdf0000]

// Register CLK_RST_CONTROLLER_SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0                     _MK_ADDR_CONST(0xdf8000)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SCR                         0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_RANGE                       29:29
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_RANGE                       28:28
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_RANGE                       27:27
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_RANGE                     26:24
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_RANGE                   23:23
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_RANGE                   22:22
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_RANGE                   21:21
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_RANGE                   20:20
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_RANGE                   19:19
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_RANGE                   18:18
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_RANGE                   17:17
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_RANGE                   16:16
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_RANGE                   15:15
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_RANGE                   14:14
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_RANGE                   13:13
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_RANGE                   12:12
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_RANGE                   11:11
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_RANGE                   10:10
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_RANGE                   9:9
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_RANGE                   8:8
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_RANGE                   7:7
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_RANGE                   6:6
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_RANGE                   5:5
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_RANGE                   4:4
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_RANGE                   3:3
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_RANGE                   2:2
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_RANGE                   1:1
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_RANGE                   0:0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_SHARED_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0                    _MK_ADDR_CONST(0xdf8004)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SCR                        0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SHIFT                      _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_RANGE                      29:29
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_LCK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_RANGE                      28:28
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_WEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SHIFT                      _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_RANGE                      27:27
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_REN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_RANGE                    26:24
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_SEC_OWNER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SHIFT                  _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_RANGE                  23:23
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SHIFT                  _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_RANGE                  22:22
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SHIFT                  _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_RANGE                  21:21
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_RANGE                  20:20
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SHIFT                  _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_RANGE                  19:19
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SHIFT                  _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_RANGE                  18:18
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SHIFT                  _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_RANGE                  17:17
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_RANGE                  16:16
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_PR0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SHIFT                  _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_RANGE                  15:15
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SHIFT                  _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_RANGE                  14:14
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SHIFT                  _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_RANGE                  13:13
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_RANGE                  12:12
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SHIFT                  _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_RANGE                  11:11
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SHIFT                  _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_RANGE                  10:10
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SHIFT                  _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_RANGE                  9:9
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_RANGE                  8:8
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0W_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SHIFT                  _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_RANGE                  7:7
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G7R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_RANGE                  6:6
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G6R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_RANGE                  5:5
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G5R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SHIFT                  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_RANGE                  4:4
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G4R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_RANGE                  3:3
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G3R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_RANGE                  2:2
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G2R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_RANGE                  1:1
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G1R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_RANGE                  0:0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0_G0R_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0                       _MK_ADDR_CONST(0xdf8008)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SCR                   0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SHIFT                 _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_RANGE                 29:29
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_LCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_RANGE                 28:28
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_WEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_RANGE                 27:27
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_REN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SHIFT                       _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_RANGE                       26:24
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_SEC_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SHIFT                     _MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_RANGE                     23:23
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SHIFT                     _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_RANGE                     22:22
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SHIFT                     _MK_SHIFT_CONST(21)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_RANGE                     21:21
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_RANGE                     20:20
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SHIFT                     _MK_SHIFT_CONST(19)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_RANGE                     19:19
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SHIFT                     _MK_SHIFT_CONST(18)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_RANGE                     18:18
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SHIFT                     _MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_RANGE                     17:17
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_RANGE                     16:16
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_PR0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SHIFT                     _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_RANGE                     15:15
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SHIFT                     _MK_SHIFT_CONST(14)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_RANGE                     14:14
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SHIFT                     _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_RANGE                     13:13
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SHIFT                     _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_RANGE                     12:12
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SHIFT                     _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_RANGE                     11:11
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SHIFT                     _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_RANGE                     10:10
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SHIFT                     _MK_SHIFT_CONST(9)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_RANGE                     9:9
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_RANGE                     8:8
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SHIFT                     _MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_RANGE                     7:7
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G7R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SHIFT                     _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_RANGE                     6:6
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G6R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SHIFT                     _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_RANGE                     5:5
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G5R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_RANGE                     4:4
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G4R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SHIFT                     _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_RANGE                     3:3
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G3R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_RANGE                     2:2
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_RANGE                     1:1
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G1R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SHIFT)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_RANGE                     0:0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SCE_SCR_DVFS_0_G0R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 14680064 [0xe00000]

// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0                   _MK_ADDR_CONST(0xe10000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0_NVDEC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0                  _MK_ADDR_CONST(0xe10004)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_RESET_VAL                        _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_RESET_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_READ_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_WRITE_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0_NVDEC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0                   _MK_ADDR_CONST(0xe10008)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0_NVDEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0                   _MK_ADDR_CONST(0xe1000c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0_NVDEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0                  _MK_ADDR_CONST(0xe10010)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0_NVDEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0                  _MK_ADDR_CONST(0xe10014)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_RESET_VAL                        _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_RESET_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_READ_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0_NVDEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0                   _MK_ADDR_CONST(0xe10018)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0_NVDEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0                      _MK_ADDR_CONST(0xe1001c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_RESET_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_READ_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_WRITE_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0_NVDEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0                       _MK_ADDR_CONST(0xe10020)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0_NVDEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 14745636 [0xe10024]

// Reserved address 14745640 [0xe10028]

// Reserved address 14745644 [0xe1002c]

// Reserved address 14745648 [0xe10030]

// Reserved address 14745652 [0xe10034]

// Reserved address 14745656 [0xe10038]

// Reserved address 14745660 [0xe1003c]

// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0                 _MK_ADDR_CONST(0xe10040)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0_NVDEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0                 _MK_ADDR_CONST(0xe10044)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0_NVDEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0                  _MK_ADDR_CONST(0xe10048)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0_NVDEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0                  _MK_ADDR_CONST(0xe1004c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0_NVDEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0                     _MK_ADDR_CONST(0xe10050)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_RESET_MASK                  _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0_NVDEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0                        _MK_ADDR_CONST(0xe10054)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_READ_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0_NVDEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0                        _MK_ADDR_CONST(0xe10058)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                      3:2
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0_NVDEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0                        _MK_ADDR_CONST(0xe1005c)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_RESET_MASK                     _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_READ_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0_NVDEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 14745696 [0xe10060]

// Reserved address 14745700 [0xe10064]

// Reserved address 14745704 [0xe10068]

// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0                      _MK_ADDR_CONST(0xe1006c)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_READ_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0_NVDEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0                     _MK_ADDR_CONST(0xe10070)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0_NVDEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0                     _MK_ADDR_CONST(0xe10074)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0_NVDEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 14745720 [0xe10078]

// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0                   _MK_ADDR_CONST(0xe20000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0_NVJPG_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0                  _MK_ADDR_CONST(0xe20004)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_RESET_VAL                        _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_RESET_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_READ_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_WRITE_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0_NVJPG_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0                   _MK_ADDR_CONST(0xe20008)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0_NVJPG_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0                   _MK_ADDR_CONST(0xe2000c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0_NVJPG_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0                  _MK_ADDR_CONST(0xe20010)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0_NVJPG_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0                  _MK_ADDR_CONST(0xe20014)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_RESET_VAL                        _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_RESET_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_READ_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0_NVJPG_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0                   _MK_ADDR_CONST(0xe20018)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0_NVJPG_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0                      _MK_ADDR_CONST(0xe2001c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_RESET_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_READ_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_WRITE_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0_NVJPG_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0                       _MK_ADDR_CONST(0xe20020)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0_NVJPG_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 14811172 [0xe20024]

// Reserved address 14811176 [0xe20028]

// Reserved address 14811180 [0xe2002c]

// Reserved address 14811184 [0xe20030]

// Reserved address 14811188 [0xe20034]

// Reserved address 14811192 [0xe20038]

// Reserved address 14811196 [0xe2003c]

// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0                 _MK_ADDR_CONST(0xe20040)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0_NVJPG_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0                 _MK_ADDR_CONST(0xe20044)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0_NVJPG_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0                  _MK_ADDR_CONST(0xe20048)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0_NVJPG_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0                  _MK_ADDR_CONST(0xe2004c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0_NVJPG_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0                     _MK_ADDR_CONST(0xe20050)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_RESET_MASK                  _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0_NVJPG_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0                        _MK_ADDR_CONST(0xe20054)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_READ_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0_NVJPG_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0                        _MK_ADDR_CONST(0xe20058)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                      3:2
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0_NVJPG_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0                        _MK_ADDR_CONST(0xe2005c)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_RESET_MASK                     _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_READ_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0_NVJPG_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 14811232 [0xe20060]

// Reserved address 14811236 [0xe20064]

// Reserved address 14811240 [0xe20068]

// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0                      _MK_ADDR_CONST(0xe2006c)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_READ_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0_NVJPG_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0                     _MK_ADDR_CONST(0xe20070)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0_NVJPG_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0                     _MK_ADDR_CONST(0xe20074)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0_NVJPG_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 14811256 [0xe20078]

// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0                    _MK_ADDR_CONST(0xe30000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0_TSEC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0                   _MK_ADDR_CONST(0xe30004)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_RESET_VAL                         _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_RESET_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_READ_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_WRITE_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0_TSEC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0                    _MK_ADDR_CONST(0xe30008)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0_TSEC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0                    _MK_ADDR_CONST(0xe3000c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0_TSEC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0                   _MK_ADDR_CONST(0xe30010)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0_TSEC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0                   _MK_ADDR_CONST(0xe30014)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_READ_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0_TSEC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0                    _MK_ADDR_CONST(0xe30018)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SCR                        0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0_TSEC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0                       _MK_ADDR_CONST(0xe3001c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_RESET_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_READ_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_WRITE_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0_TSEC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0                        _MK_ADDR_CONST(0xe30020)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SCR                    0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0_TSEC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 14876708 [0xe30024]

// Reserved address 14876712 [0xe30028]

// Reserved address 14876716 [0xe3002c]

// Reserved address 14876720 [0xe30030]

// Reserved address 14876724 [0xe30034]

// Reserved address 14876728 [0xe30038]

// Reserved address 14876732 [0xe3003c]

// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0                  _MK_ADDR_CONST(0xe30040)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0_TSEC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0                  _MK_ADDR_CONST(0xe30044)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0_TSEC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0                   _MK_ADDR_CONST(0xe30048)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0_TSEC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0                   _MK_ADDR_CONST(0xe3004c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0_TSEC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0                      _MK_ADDR_CONST(0xe30050)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_RESET_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_READ_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0_TSEC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0                 _MK_ADDR_CONST(0xe30054)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_READ_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0_TSEC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0                 _MK_ADDR_CONST(0xe30058)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                    31:31
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                        3:2
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0_TSEC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0                 _MK_ADDR_CONST(0xe3005c)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SCR                     0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_RESET_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_READ_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0_TSEC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 14876768 [0xe30060]

// Reserved address 14876772 [0xe30064]

// Reserved address 14876776 [0xe30068]

// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0                       _MK_ADDR_CONST(0xe3006c)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0_TSEC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0                      _MK_ADDR_CONST(0xe30070)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0_TSEC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0                      _MK_ADDR_CONST(0xe30074)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SCR                  0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0_TSEC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 14876792 [0xe30078]

// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0                   _MK_ADDR_CONST(0xe40000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0_TSECB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0                  _MK_ADDR_CONST(0xe40004)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_RESET_VAL                        _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_RESET_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_READ_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_WRITE_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0_TSECB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0                   _MK_ADDR_CONST(0xe40008)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0_TSECB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0                   _MK_ADDR_CONST(0xe4000c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0_TSECB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0                  _MK_ADDR_CONST(0xe40010)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0_TSECB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0                  _MK_ADDR_CONST(0xe40014)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_RESET_VAL                        _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_RESET_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_READ_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0_TSECB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0                   _MK_ADDR_CONST(0xe40018)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0_TSECB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0                      _MK_ADDR_CONST(0xe4001c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_RESET_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_READ_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_WRITE_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0_TSECB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0                       _MK_ADDR_CONST(0xe40020)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0_TSECB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 14942244 [0xe40024]

// Reserved address 14942248 [0xe40028]

// Reserved address 14942252 [0xe4002c]

// Reserved address 14942256 [0xe40030]

// Reserved address 14942260 [0xe40034]

// Reserved address 14942264 [0xe40038]

// Reserved address 14942268 [0xe4003c]

// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0                 _MK_ADDR_CONST(0xe40040)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0_TSECB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0                 _MK_ADDR_CONST(0xe40044)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0_TSECB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0                  _MK_ADDR_CONST(0xe40048)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0_TSECB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0                  _MK_ADDR_CONST(0xe4004c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0_TSECB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0                     _MK_ADDR_CONST(0xe40050)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_RESET_MASK                  _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0_TSECB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0                        _MK_ADDR_CONST(0xe40054)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_READ_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0_TSECB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0                        _MK_ADDR_CONST(0xe40058)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                  31:31
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                      3:2
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0_TSECB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0                        _MK_ADDR_CONST(0xe4005c)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_RESET_MASK                     _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_READ_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0_TSECB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 14942304 [0xe40060]

// Reserved address 14942308 [0xe40064]

// Reserved address 14942312 [0xe40068]

// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0                      _MK_ADDR_CONST(0xe4006c)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_READ_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0_TSECB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0                     _MK_ADDR_CONST(0xe40070)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0_TSECB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0                     _MK_ADDR_CONST(0xe40074)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0_TSECB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 14942328 [0xe40078]

// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0                      _MK_ADDR_CONST(0xe50000)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0_VI_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0                     _MK_ADDR_CONST(0xe50004)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_RESET_VAL                   _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_RESET_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_READ_MASK                   _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_WRITE_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0_VI_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0                      _MK_ADDR_CONST(0xe50008)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0_VI_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0                      _MK_ADDR_CONST(0xe5000c)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0_VI_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0                     _MK_ADDR_CONST(0xe50010)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_FIELD                  _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0_VI_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0                     _MK_ADDR_CONST(0xe50014)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0_VI_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0                      _MK_ADDR_CONST(0xe50018)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_MISC_0_VI_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0                 _MK_ADDR_CONST(0xe5001c)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_RESET_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_READ_MASK                       _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_WRITE_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0_VI_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0                  _MK_ADDR_CONST(0xe50020)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0_VI_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 15007780 [0xe50024]

// Reserved address 15007784 [0xe50028]

// Reserved address 15007788 [0xe5002c]

// Reserved address 15007792 [0xe50030]

// Reserved address 15007796 [0xe50034]

// Reserved address 15007800 [0xe50038]

// Reserved address 15007804 [0xe5003c]

// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0                    _MK_ADDR_CONST(0xe50040)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0_VI_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0                    _MK_ADDR_CONST(0xe50044)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0_VI_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0                     _MK_ADDR_CONST(0xe50048)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_RESET_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_READ_MASK                   _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0_VI_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0                     _MK_ADDR_CONST(0xe5004c)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SCR                         0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_RESET_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_READ_MASK                   _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0_VI_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0                        _MK_ADDR_CONST(0xe50050)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_RESET_MASK                     _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_READ_MASK                      _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0_VI_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0                   _MK_ADDR_CONST(0xe50054)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_RESET_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_READ_MASK                         _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0_VI_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0                   _MK_ADDR_CONST(0xe50058)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                         _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                        31:31
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                    3:2
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0_VI_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0                   _MK_ADDR_CONST(0xe5005c)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SCR                       0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_RESET_MASK                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_READ_MASK                         _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0_VI_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 15007840 [0xe50060]

// Reserved address 15007844 [0xe50064]

// Reserved address 15007848 [0xe50068]

// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0                 _MK_ADDR_CONST(0xe5006c)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_READ_MASK                       _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0_VI_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0                        _MK_ADDR_CONST(0xe50070)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0_VI_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0                        _MK_ADDR_CONST(0xe50074)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SCR                    0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_RESET_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_READ_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0_VI_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 15007864 [0xe50078]

// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0                      _MK_ADDR_CONST(0xe60000)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0_SE_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0                     _MK_ADDR_CONST(0xe60004)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_RESET_VAL                   _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_RESET_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_READ_MASK                   _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_WRITE_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0_SE_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0                      _MK_ADDR_CONST(0xe60008)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0_SE_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0                      _MK_ADDR_CONST(0xe6000c)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0_SE_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0                     _MK_ADDR_CONST(0xe60010)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_FIELD                  _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0_SE_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0                     _MK_ADDR_CONST(0xe60014)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_RESET_VAL                   _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_RESET_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_READ_MASK                   _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0_SE_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0                      _MK_ADDR_CONST(0xe60018)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SCR                  0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_MISC_0_SE_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0                 _MK_ADDR_CONST(0xe6001c)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_RESET_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_READ_MASK                       _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_WRITE_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0_SE_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0                  _MK_ADDR_CONST(0xe60020)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SCR                      0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0_SE_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 15073316 [0xe60024]

// Reserved address 15073320 [0xe60028]

// Reserved address 15073324 [0xe6002c]

// Reserved address 15073328 [0xe60030]

// Reserved address 15073332 [0xe60034]

// Reserved address 15073336 [0xe60038]

// Reserved address 15073340 [0xe6003c]

// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0                    _MK_ADDR_CONST(0xe60040)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0_SE_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0                    _MK_ADDR_CONST(0xe60044)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0_SE_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0                     _MK_ADDR_CONST(0xe60048)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_RESET_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_READ_MASK                   _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0_SE_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0                     _MK_ADDR_CONST(0xe6004c)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SCR                         0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_RESET_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_READ_MASK                   _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0_SE_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0                        _MK_ADDR_CONST(0xe60050)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_RESET_MASK                     _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_READ_MASK                      _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0_SE_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0                   _MK_ADDR_CONST(0xe60054)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_RESET_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_READ_MASK                         _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0_SE_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0                   _MK_ADDR_CONST(0xe60058)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                         _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                         _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                        31:31
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                    3:2
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0_SE_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0                   _MK_ADDR_CONST(0xe6005c)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SCR                       0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_RESET_MASK                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_READ_MASK                         _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0_SE_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 15073376 [0xe60060]

// Reserved address 15073380 [0xe60064]

// Reserved address 15073384 [0xe60068]

// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0                 _MK_ADDR_CONST(0xe6006c)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_READ_MASK                       _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0_SE_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0                        _MK_ADDR_CONST(0xe60070)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0_SE_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0                        _MK_ADDR_CONST(0xe60074)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SCR                    0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_RESET_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_READ_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0_SE_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 15073400 [0xe60078]

// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0                   _MK_ADDR_CONST(0xe70000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_RANGE                   16:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SHIFT                      _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_RANGE                      6:6
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                      _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                      5:5
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                     4:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_RANGE                  3:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_RANGE                       2:2
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_RANGE                       1:1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0_NVENC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0                  _MK_ADDR_CONST(0xe70004)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_RESET_VAL                        _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_RESET_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_READ_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_WRITE_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                    31:28
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_RANGE                     20:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_FIELD                     _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_RANGE                     4:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0_NVENC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0                   _MK_ADDR_CONST(0xe70008)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                     15:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0_NVENC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0                   _MK_ADDR_CONST(0xe7000c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                     31:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0_NVENC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0                  _MK_ADDR_CONST(0xe70010)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_RANGE                    31:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0_NVENC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0                  _MK_ADDR_CONST(0xe70014)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_RESET_VAL                        _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_RESET_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_READ_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                  27:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                      _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                      23:20
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                       19:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_RANGE                        11:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0_NVENC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0                   _MK_ADDR_CONST(0xe70018)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SCR                       0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_FIELD                 _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_RANGE                 15:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0_NVENC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0                      _MK_ADDR_CONST(0xe7001c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_RESET_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_READ_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_WRITE_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_FIELD                  _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_RANGE                  31:24
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                 23:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0_NVENC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0                       _MK_ADDR_CONST(0xe70020)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                  _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                  7:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                   _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                   2:1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_RANGE                     0:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0_NVENC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 15138852 [0xe70024]

// Reserved address 15138856 [0xe70028]

// Reserved address 15138860 [0xe7002c]

// Reserved address 15138864 [0xe70030]

// Reserved address 15138868 [0xe70034]

// Reserved address 15138872 [0xe70038]

// Reserved address 15138876 [0xe7003c]

// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0                 _MK_ADDR_CONST(0xe70040)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0_NVENC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0                 _MK_ADDR_CONST(0xe70044)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0_NVENC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0                  _MK_ADDR_CONST(0xe70048)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0_NVENC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0                  _MK_ADDR_CONST(0xe7004c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0_NVENC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0                     _MK_ADDR_CONST(0xe70050)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_RESET_MASK                  _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_RANGE                   16:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                 7:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                 3:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0_NVENC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0                        _MK_ADDR_CONST(0xe70054)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_READ_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                  _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                  12:12
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_RANGE                    8:8
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                     _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                     2:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0_NVENC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0                        _MK_ADDR_CONST(0xe70058)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                      _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                  _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                  31:31
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                   _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                   23:20
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                     12:4
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                      3:2
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                  1:0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0_NVENC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0                        _MK_ADDR_CONST(0xe7005c)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SCR                    0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_RESET_MASK                     _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_READ_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                      3:3
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0_NVENC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 15138912 [0xe70060]

// Reserved address 15138916 [0xe70064]

// Reserved address 15138920 [0xe70068]

// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0                      _MK_ADDR_CONST(0xe7006c)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SCR                  0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_READ_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                   _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_RANGE                   31:28
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                 _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                 27:27
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                      _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                      25:25
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_RANGE                    24:24
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                      _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                      2:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0_NVENC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0                     _MK_ADDR_CONST(0xe70070)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_RANGE                  31:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0_NVENC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0                     _MK_ADDR_CONST(0xe70074)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SCR                         0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_RANGE                  3:0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0_NVENC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 15138936 [0xe70078]

// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0                     _MK_ADDR_CONST(0xe80000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_READ_MASK                   _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0_ISP_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0                    _MK_ADDR_CONST(0xe80004)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_RESET_VAL                  _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_RESET_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_READ_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_WRITE_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0_ISP_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0                     _MK_ADDR_CONST(0xe80008)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0_ISP_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0                     _MK_ADDR_CONST(0xe8000c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0_ISP_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0                    _MK_ADDR_CONST(0xe80010)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_FIELD                        _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0_ISP_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0                    _MK_ADDR_CONST(0xe80014)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_READ_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0_ISP_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0                     _MK_ADDR_CONST(0xe80018)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SCR                         0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0_ISP_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0                        _MK_ADDR_CONST(0xe8001c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_RESET_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_READ_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_WRITE_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0_ISP_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0                 _MK_ADDR_CONST(0xe80020)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0_ISP_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 15204388 [0xe80024]

// Reserved address 15204392 [0xe80028]

// Reserved address 15204396 [0xe8002c]

// Reserved address 15204400 [0xe80030]

// Reserved address 15204404 [0xe80034]

// Reserved address 15204408 [0xe80038]

// Reserved address 15204412 [0xe8003c]

// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0                   _MK_ADDR_CONST(0xe80040)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0_ISP_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0                   _MK_ADDR_CONST(0xe80044)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0_ISP_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0                    _MK_ADDR_CONST(0xe80048)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0_ISP_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0                    _MK_ADDR_CONST(0xe8004c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0_ISP_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0                       _MK_ADDR_CONST(0xe80050)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_RESET_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_READ_MASK                     _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0_ISP_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0                  _MK_ADDR_CONST(0xe80054)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_READ_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0_ISP_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0                  _MK_ADDR_CONST(0xe80058)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                      31:31
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                  3:2
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0_ISP_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0                  _MK_ADDR_CONST(0xe8005c)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SCR                      0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_RESET_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_READ_MASK                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0_ISP_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 15204448 [0xe80060]

// Reserved address 15204452 [0xe80064]

// Reserved address 15204456 [0xe80068]

// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0                        _MK_ADDR_CONST(0xe8006c)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_READ_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0_ISP_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0                       _MK_ADDR_CONST(0xe80070)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_FIELD                      _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0_ISP_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0                       _MK_ADDR_CONST(0xe80074)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SCR                   0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0_ISP_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 15204472 [0xe80078]

// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0                     _MK_ADDR_CONST(0xe90000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_READ_MASK                   _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_RANGE                       16:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SHIFT                  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_RANGE                  6:6
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                  _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                  5:5
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                 4:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_RANGE                      3:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_SHIFT                   _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_RANGE                   2:2
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_RANGE                   1:1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0_VIC_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0                    _MK_ADDR_CONST(0xe90004)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_RESET_VAL                  _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_RESET_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_READ_MASK                  _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_WRITE_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                        31:28
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                        27:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_RANGE                 20:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_FIELD                 _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_RANGE                 4:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0_VIC_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0                     _MK_ADDR_CONST(0xe90008)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                 15:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_RANGE                       7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0_VIC_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0                     _MK_ADDR_CONST(0xe9000c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                 31:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0_VIC_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0                    _MK_ADDR_CONST(0xe90010)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SHIFT                        _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_FIELD                        _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_RANGE                        31:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_RANGE                     15:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0_VIC_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0                    _MK_ADDR_CONST(0xe90014)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_READ_MASK                  _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                  31:28
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                      27:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                  23:20
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                   19:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SHIFT                    _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_RANGE                    11:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                 7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0_VIC_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0                     _MK_ADDR_CONST(0xe90018)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SCR                         0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_FIELD                     _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_RANGE                     15:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0_VIC_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0                        _MK_ADDR_CONST(0xe9001c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_RESET_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_READ_MASK                      _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_WRITE_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_RANGE                      31:24
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_RANGE                     23:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0_VIC_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0                 _MK_ADDR_CONST(0xe90020)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SCR                     0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                      _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                      _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                      7:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                       _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                       _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                       2:1
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_RANGE                 0:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0_VIC_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Reserved address 15269924 [0xe90024]

// Reserved address 15269928 [0xe90028]

// Reserved address 15269932 [0xe9002c]

// Reserved address 15269936 [0xe90030]

// Reserved address 15269940 [0xe90034]

// Reserved address 15269944 [0xe90038]

// Reserved address 15269948 [0xe9003c]

// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0                   _MK_ADDR_CONST(0xe90040)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0_VIC_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0                   _MK_ADDR_CONST(0xe90044)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0_VIC_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0                    _MK_ADDR_CONST(0xe90048)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0_VIC_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0                    _MK_ADDR_CONST(0xe9004c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SCR                        0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0_VIC_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0                       _MK_ADDR_CONST(0xe90050)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_RESET_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_READ_MASK                     _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_RANGE                       16:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                     _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                     7:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                     3:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0_VIC_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0                  _MK_ADDR_CONST(0xe90054)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_READ_MASK                        _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                     19:16
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                      _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                      12:12
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SHIFT                        _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_RANGE                        8:8
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_FIELD                 _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_RANGE                 2:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0_VIC_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0                  _MK_ADDR_CONST(0xe90058)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                        _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                        _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                      _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                      31:31
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                       _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                       23:20
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                 _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                 12:4
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                  _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                  _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                  3:2
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                      _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                      1:0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0_VIC_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0                  _MK_ADDR_CONST(0xe9005c)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SCR                      0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_RESET_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_READ_MASK                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                  _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                  3:3
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0_VIC_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Reserved address 15269984 [0xe90060]

// Reserved address 15269988 [0xe90064]

// Reserved address 15269992 [0xe90068]

// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0                        _MK_ADDR_CONST(0xe9006c)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_READ_MASK                      _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SHIFT                       _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_RANGE                       31:28
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                     _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                     27:27
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_RANGE                  25:25
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_RANGE                        24:24
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                  _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                  2:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0_VIC_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0                       _MK_ADDR_CONST(0xe90070)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_FIELD                      _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_RANGE                      31:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0_VIC_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0                       _MK_ADDR_CONST(0xe90074)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SCR                   0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_RANGE                      3:0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0_VIC_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Reserved address 15270008 [0xe90078]

// Reserved address 15335424 [0xea0000]

// Reserved address 15400960 [0xeb0000]

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0                    _MK_ADDR_CONST(0xec0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_RANGE                     16:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SHIFT                        _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_RANGE                        6:6
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                        _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                        5:5
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                       4:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_RANGE                    3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_SHIFT                 _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_RANGE                 2:2
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_RANGE                 1:1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_DEFAULT                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0_NVDISPLAYHUB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0                   _MK_ADDR_CONST(0xec0004)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_RESET_VAL                         _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_RESET_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_READ_MASK                         _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_WRITE_MASK                        _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                      _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                      31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                      27:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                    _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_RANGE                       20:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_FIELD                       _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_RANGE                       4:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0_NVDISPLAYHUB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0                    _MK_ADDR_CONST(0xec0008)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                       _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                       15:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0_NVDISPLAYHUB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0                    _MK_ADDR_CONST(0xec000c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                       31:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0_NVDISPLAYHUB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0                   _MK_ADDR_CONST(0xec0010)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SHIFT                      _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_FIELD                      _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_RANGE                      31:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_RANGE                   15:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0_NVDISPLAYHUB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0                   _MK_ADDR_CONST(0xec0014)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_READ_MASK                         _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                        _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                        31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                    27:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                  _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                        23:20
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                 19:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_RANGE                  11:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                       7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0_NVDISPLAYHUB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0                    _MK_ADDR_CONST(0xec0018)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SCR                        0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_FIELD                   _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_RANGE                   15:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0_NVDISPLAYHUB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0                       _MK_ADDR_CONST(0xec001c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_RESET_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_READ_MASK                     _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_WRITE_MASK                    _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                    _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_FIELD                    _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_RANGE                    31:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                   23:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0_NVDISPLAYHUB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0                        _MK_ADDR_CONST(0xec0020)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SCR                    0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                    _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                    7:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                     _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                     2:1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_RANGE                       0:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0_NVDISPLAYHUB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Reserved address 15466532 [0xec0024]

// Reserved address 15466536 [0xec0028]

// Reserved address 15466540 [0xec002c]

// Reserved address 15466544 [0xec0030]

// Reserved address 15466548 [0xec0034]

// Reserved address 15466552 [0xec0038]

// Reserved address 15466556 [0xec003c]

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0                  _MK_ADDR_CONST(0xec0040)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                 _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                 31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                   7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0                  _MK_ADDR_CONST(0xec0044)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SCR                      0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                     28:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                     _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                     12:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                      _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0                   _MK_ADDR_CONST(0xec0048)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                   _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                   31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                     7:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0                   _MK_ADDR_CONST(0xec004c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SCR                       0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_RESET_MASK                        _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_RANGE                       28:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_FIELD                       _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_RANGE                       12:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                        _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0                      _MK_ADDR_CONST(0xec0050)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_RESET_MASK                   _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_READ_MASK                    _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                     _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_FIELD                     _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_RANGE                     16:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                   7:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                   3:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0                 _MK_ADDR_CONST(0xec0054)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_READ_MASK                       _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                   _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                   19:16
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                    12:12
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_RANGE                      8:8
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                       2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0_NVDISPLAYHUB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0                 _MK_ADDR_CONST(0xec0058)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                       _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                       _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                      _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                    _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                    31:31
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                     _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                     23:20
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                       _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                       12:4
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                        _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                        3:2
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                    1:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0                 _MK_ADDR_CONST(0xec005c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SCR                     0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_RESET_MASK                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_READ_MASK                       _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                        3:3
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0_NVDISPLAYHUB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 15466592 [0xec0060]

// Reserved address 15466596 [0xec0064]

// Reserved address 15466600 [0xec0068]

// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0                       _MK_ADDR_CONST(0xec006c)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_READ_MASK                     _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                     _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_RANGE                     31:28
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                   _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                   27:27
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                        _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                        25:25
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SHIFT                      _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_RANGE                      24:24
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                        _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                        2:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0_NVDISPLAYHUB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0                      _MK_ADDR_CONST(0xec0070)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_RANGE                    31:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0                      _MK_ADDR_CONST(0xec0074)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SCR                  0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_RANGE                    3:0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 15466616 [0xec0078]

// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0                  _MK_ADDR_CONST(0xed0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x1007f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_RANGE                 16:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_FLL_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SHIFT                    _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_RANGE                    6:6
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT                    _MK_SHIFT_CONST(5)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_RANGE                    5:5
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_PRB_CLKOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_RANGE                   4:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_EN_CLK_PRE_SKP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_RANGE                        3:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_BYPASSFLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_RANGE                     2:2
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_DVCO_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_RANGE                     1:1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_DEFAULT                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_IDDQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_RANGE                   0:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0_AXICBB_NAFLL_CFG1_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0                 _MK_ADDR_CONST(0xed0004)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_RESET_VAL                       _MK_MASK_CONST(0x86000000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_RESET_MASK                      _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_READ_MASK                       _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_WRITE_MASK                      _MK_MASK_CONST(0xff1f001f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT                  _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_RANGE                  31:28
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT                        _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_FAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_FIELD                  _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_RANGE                  27:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT                        _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_FLL_FRUG_MAIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_RANGE                   20:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_PDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_FIELD                   _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_RANGE                   4:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0_AXICBB_NAFLL_COEFF_MDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0                  _MK_ADDR_CONST(0xed0008)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT                   _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_RANGE                   15:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_CTRL_LDMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_RANGE                 7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0_AXICBB_NAFLL_CFG2_FLL_INIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0                  _MK_ADDR_CONST(0xed000c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_RANGE                   31:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0_AXICBB_NAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0                 _MK_ADDR_CONST(0xed0010)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SHIFT                  _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_FIELD                  _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_RANGE                  31:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_SETUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_RANGE                       15:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0_AXICBB_NAFLL_CTRL1_FLL_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0                 _MK_ADDR_CONST(0xed0014)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_RESET_VAL                       _MK_MASK_CONST(0x86f0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_RESET_MASK                      _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_READ_MASK                       _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_WRITE_MASK                      _MK_MASK_CONST(0xffff0fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT                    _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_RANGE                    31:28
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_VFGAIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_RANGE                        27:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT                      _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_INIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT                    _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_FIELD                    _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_RANGE                    23:20
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT                  _MK_MASK_CONST(0x6)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT                     _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_FIELD                     _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_RANGE                     19:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT                   _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_FIELD                      _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_RANGE                      11:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_DEBUG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_RANGE                   7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0_AXICBB_NAFLL_CTRL2_FLL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0                  _MK_ADDR_CONST(0xed0018)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SCR                      0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_FIELD                       _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_RANGE                       15:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0_AXICBB_NAFLL_MISC_DEBUG_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0                     _MK_ADDR_CONST(0xed001c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_RESET_MASK                  _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_READ_MASK                   _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_WRITE_MASK                  _MK_MASK_CONST(0xffff0000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SHIFT                        _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_FIELD                        _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_RANGE                        31:24
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_RANGE                       23:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0_AXICBB_NAFLL_SKP_COEFF_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0                      _MK_ADDR_CONST(0xed0020)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SCR                  0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT                        _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_FIELD                        _MK_FIELD_CONST(0x1f, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_RANGE                        7:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_RAMP_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT                 _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_FIELD                 _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_RANGE                 2:1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_CTRL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_RANGE                   0:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0_AXICBB_NAFLL_SKP_CTRL_SKP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 15532068 [0xed0024]

// Reserved address 15532072 [0xed0028]

// Reserved address 15532076 [0xed002c]

// Reserved address 15532080 [0xed0030]

// Reserved address 15532084 [0xed0034]

// Reserved address 15532088 [0xed0038]

// Reserved address 15532092 [0xed003c]

// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0                        _MK_ADDR_CONST(0xed0040)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SCR                    0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_READ_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT                     _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_RANGE                     31:31
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_AUTO_INC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_RANGE                       7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0_AXICBB_NAFLL_LUT_WRITE_ADDR_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0                        _MK_ADDR_CONST(0xed0044)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SCR                    0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_RESET_MASK                     _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_READ_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT                 _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_RANGE                 28:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_FIELD                 _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_RANGE                 12:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_DEFAULT_MASK                  _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0_AXICBB_NAFLL_LUT_WRITE_DATA_VAL0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0                 _MK_ADDR_CONST(0xed0048)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT                       _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_RANGE                       31:31
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_AUTO_INC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_FIELD                 _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_RANGE                 7:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0_AXICBB_NAFLL_LUT_READ_ADDR_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0                 _MK_ADDR_CONST(0xed004c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SCR                     0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_RESET_MASK                      _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_READ_MASK                       _MK_MASK_CONST(0x1fff1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SHIFT                   _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_RANGE                   28:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_FIELD                   _MK_FIELD_CONST(0x1fff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_RANGE                   12:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0_AXICBB_NAFLL_LUT_READ_DATA_VAL0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0                    _MK_ADDR_CONST(0xed0050)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SHIFT                 _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_FIELD                 _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_RANGE                 16:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_NDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT                       _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_RANGE                       7:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_VFGAIN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_RANGE                       3:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0_AXICBB_NAFLL_LUT_DEBUG2_PRI_CTRL_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0                       _MK_ADDR_CONST(0xed0054)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_READ_MASK                     _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xf1107)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT                       _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_FIELD                       _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_RANGE                       19:16
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_HYSTERESIS_THRESHOLD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT                        _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_RANGE                        12:12
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RAM_READ_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SHIFT                  _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_RANGE                  8:8
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_RESET_FSM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_RANGE                   2:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0_AXICBB_NAFLL_LUT_CFG_TEMP_IDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0                       _MK_ADDR_CONST(0xed0058)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_VAL                     _MK_MASK_CONST(0x80000000)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_RESET_MASK                    _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_READ_MASK                     _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_WRITE_MASK                    _MK_MASK_CONST(0x80f01fff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT                        _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_RANGE                        31:31
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_SRAM_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT                 _MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_RANGE                 23:20
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_VFGAIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT                   _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_FIELD                   _MK_FIELD_CONST(0x1ff, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_RANGE                   12:4
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_DEFAULT_MASK                    _MK_MASK_CONST(0x1ff)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_REQ_NDIV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT                    _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_FIELD                    _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_RANGE                    3:2
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_SW_OVERRIDE_LUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_FIELD                        _MK_FIELD_CONST(0x3, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_RANGE                        1:0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0_AXICBB_NAFLL_LUT_SW_FREQ_REQ_LUT_VSELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0                       _MK_ADDR_CONST(0xed005c)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SCR                   0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_RESET_MASK                    _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_READ_MASK                     _MK_MASK_CONST(0x8)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT                    _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_RANGE                    3:3
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0_AXICBB_NAFLL_LUT_ACK_RDACK_LUT_DEBUG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 15532128 [0xed0060]

// Reserved address 15532132 [0xed0064]

// Reserved address 15532136 [0xed0068]

// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0                     _MK_ADDR_CONST(0xed006c)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SECURE                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SCR                         0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_WORD_COUNT                  0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_RESET_MASK                  _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_READ_MASK                   _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_WRITE_MASK                  _MK_MASK_CONST(0xfb000007)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SHIFT                 _MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_FIELD                 _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_RANGE                 31:28
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT                       _MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_RANGE                       27:27
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_CONTINOUS_UPDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT                    _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_RANGE                    25:25
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SHIFT                  _MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_RANGE                  24:24
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_FIELD                    _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_RANGE                    2:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0_AXICBB_CLK_FR_CNTR_CFG_COUNT_UPDATE_CYCLES_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0                    _MK_ADDR_CONST(0xed0070)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0_AXICBB_CLK_FR_CNTR_CNT0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0                    _MK_ADDR_CONST(0xed0074)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SCR                        0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_FIELD                        _MK_FIELD_CONST(0xf, CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_RANGE                        3:0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0_AXICBB_CLK_FR_CNTR_CNT1_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 15532152 [0xed0078]

// Reserved address 15597568 [0xee0000]

// Reserved address 15663104 [0xef0000]

// Reserved address 15728640 [0xf00000]

// Reserved address 15794176 [0xf10000]

// Reserved address 15859712 [0xf20000]

// Reserved address 15925248 [0xf30000]

// Reserved address 15990784 [0xf40000]

// Reserved address 16056320 [0xf50000]

// Reserved address 16121856 [0xf60000]

// Reserved address 16187392 [0xf70000]

// Reserved address 16252928 [0xf80000]

// Reserved address 16318464 [0xf90000]

// Register CLK_RST_CONTROLLER_RST_DEV_DSIC_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0                       _MK_ADDR_CONST(0xfa0000)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_0_SWR_DSIC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0                   _MK_ADDR_CONST(0xfa0004)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0_SET_SWR_DSIC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0                   _MK_ADDR_CONST(0xfa0008)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0_CLR_SWR_DSIC_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0                   _MK_ADDR_CONST(0xfa1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0_CLK_ENB_DSIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0                       _MK_ADDR_CONST(0xfa1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0_SET_CLK_ENB_DSIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0                       _MK_ADDR_CONST(0xfa1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0_CLR_CLK_ENB_DSIC_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0                 _MK_ADDR_CONST(0xfa100c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0_DSIC_LP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0                   _MK_ADDR_CONST(0xfa2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_LP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0_BOND_OUT_DSIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_DSID_0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0                       _MK_ADDR_CONST(0xfb0000)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SCR                   0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_INIT_ENUM                        ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_0_SWR_DSID_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0                   _MK_ADDR_CONST(0xfb0004)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0_SET_SWR_DSID_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0                   _MK_ADDR_CONST(0xfb0008)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_SCR                       0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_SHIFT                    _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_DEFAULT                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0_CLR_SWR_DSID_RST_ENABLE                   _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0                   _MK_ADDR_CONST(0xfb1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_SCR                       0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_INIT_ENUM                    DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0_CLK_ENB_DSID_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0                       _MK_ADDR_CONST(0xfb1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0_SET_CLK_ENB_DSID_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0                       _MK_ADDR_CONST(0xfb1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_RANGE                     1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_INIT_ENUM                 DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_DISABLE                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_LP_ENABLE                    _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_FIELD                        _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_RANGE                        0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0_CLR_CLK_ENB_DSID_ENABLE                       _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0                 _MK_ADDR_CONST(0xfb2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_SECURE                  0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_SCR                     0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_WORD_COUNT                      0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_RESET_VAL                       _MK_MASK_CONST(0xe0000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_RESET_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_READ_MASK                       _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_WRITE_MASK                      _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_FIELD                   _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_RANGE                   31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_INIT_ENUM                       CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_CLK_S                   _MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_SRC_CLK_M                   _MK_ENUM_CONST(7)

#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_FIELD                       _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_RANGE                       7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0_DSID_LP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0                   _MK_ADDR_CONST(0xfb2004)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_SCR                       0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_SHIFT                    _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_RANGE                    1:1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_LP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_RANGE                       0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0_BOND_OUT_DSID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0                  _MK_ADDR_CONST(0xfc0000)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SCR                      0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_INIT_ENUM                      ENABLE
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0_SWR_GPIO_CTL5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0                      _MK_ADDR_CONST(0xfc0004)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0_SET_SWR_GPIO_CTL5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0                      _MK_ADDR_CONST(0xfc0008)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SCR                  0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SHIFT                  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SHIFT)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_RANGE                  0:0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0_CLR_SWR_GPIO_CTL5_RST_ENABLE                 _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0                      _MK_ADDR_CONST(0xfc1000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SCR                  0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_INIT_ENUM                  DISABLE
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0_CLK_ENB_GPIO_CTL5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0                  _MK_ADDR_CONST(0xfc1004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0_SET_CLK_ENB_GPIO_CTL5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0                  _MK_ADDR_CONST(0xfc1008)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SECURE                   0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SCR                      0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_WORD_COUNT                       0x1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SHIFT                      _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_RANGE                      0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_DISABLE                    _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0_CLR_CLK_ENB_GPIO_CTL5_ENABLE                     _MK_ENUM_CONST(1)


// Register CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0                      _MK_ADDR_CONST(0xfc2000)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SECURE                       0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SCR                  0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_WORD_COUNT                   0x1
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SHIFT)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_RANGE                     0:0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0_BOND_OUT_GPIO_CTL5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0                       _MK_ADDR_CONST(0xfc3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SCR                   0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_RESET_VAL                     _MK_MASK_CONST(0x20000000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_RESET_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_READ_MASK                     _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_WRITE_MASK                    _MK_MASK_CONST(0xe00000ff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_FIELD                       _MK_FIELD_CONST(0x7, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_RANGE                       31:29
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_INIT_ENUM                   CLK_M
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_CLK_M                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_SRC_CLK_S                       _MK_ENUM_CONST(6)

#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0_GPIO_CTL5_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Reserved address 16580608 [0xfd0000]

// Reserved address 16646144 [0xfe0000]

// Reserved address 16711680 [0xff0000]

// Reserved address 16711684 [0xff0004]

// Reserved address 16711688 [0xff0008]

// Reserved address 16711692 [0xff000c]

// Reserved address 16711696 [0xff0010]

// Reserved address 16711700 [0xff0014]

// Reserved address 16711704 [0xff0018]

// Reserved address 16711708 [0xff001c]

// Reserved address 16711712 [0xff0020]

// Reserved address 16711716 [0xff0024]

// Reserved address 16711720 [0xff0028]

// Reserved address 16711724 [0xff002c]

// Reserved address 16711728 [0xff0030]

// Reserved address 16711732 [0xff0034]

// Reserved address 16711736 [0xff0038]

// Reserved address 16711740 [0xff003c]

// Reserved address 16711744 [0xff0040]

// Reserved address 16711748 [0xff0044]

// Reserved address 16711752 [0xff0048]

// Reserved address 16711756 [0xff004c]

// Reserved address 16711760 [0xff0050]

// Reserved address 16711764 [0xff0054]

// Reserved address 16711768 [0xff0058]

// Reserved address 16711772 [0xff005c]

// Reserved address 16711776 [0xff0060]

// Reserved address 16711780 [0xff0064]

// Reserved address 16711784 [0xff0068]

// Reserved address 16711788 [0xff006c]

// Reserved address 16711792 [0xff0070]

// Reserved address 16711796 [0xff0074]

// Reserved address 16711800 [0xff0078]

// Reserved address 16711804 [0xff007c]

// Reserved address 16711808 [0xff0080]

// Reserved address 16711812 [0xff0084]

// Reserved address 16711816 [0xff0088]

// Reserved address 16711820 [0xff008c]

// Register CLK_RST_CONTROLLER_SOC_ADC_CTRL_0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0                       _MK_ADDR_CONST(0xff0090)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SECURE                        0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SCR                   0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_WORD_COUNT                    0x1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xffff7)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xffff7)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xffff7)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SHIFT                    _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_FIELD                    _MK_FIELD_CONST(0xffff, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RANGE                    19:4
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_SHIFT                      _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_FIELD                      _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_RANGE                      2:2
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_RESET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_SHIFT                     _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_RANGE                     1:1
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SHIFT                   _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_RANGE                   0:0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_DEFAULT                 _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_CTRL_0_SOC_ADC_CTRL_ADC_IDDQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0                    _MK_ADDR_CONST(0xff0094)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SECURE                     0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SCR                        0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_WORD_COUNT                         0x1
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_RESET_MASK                         _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_READ_MASK                  _MK_MASK_CONST(0x3ff)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SHIFT                     _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_FIELD                     _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_RANGE                     9:2
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_DOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_FIELD                   _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_RANGE                   1:1
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_ADC_SAMPLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_SHIFT                     _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_FIELD                     _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_RANGE                     0:0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_WOFFSET                   0x0
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0_SOC_ADC_MONITOR_PWR_GOOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0                   _MK_ADDR_CONST(0xff0098)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SECURE                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SCR                       0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_WORD_COUNT                        0x1
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_RESET_MASK                        _MK_MASK_CONST(0x101ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_READ_MASK                         _MK_MASK_CONST(0x101ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_WRITE_MASK                        _MK_MASK_CONST(0x101ff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT                    _MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_FIELD                    _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_RANGE                    16:16
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_WOFFSET                  0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_SW_OVERRIDE_ADC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SHIFT                   _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_FIELD                   _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_RANGE                   8:1
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_WOFFSET                 0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_DOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SHIFT                 _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_FIELD                 _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_RANGE                 0:0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_WOFFSET                       0x0
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0_SOC_ADC_OVERRIDE_ADC_SAMPLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SOC_ADC_ACC_0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0                        _MK_ADDR_CONST(0xff009c)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_ACC_0_SOC_ADC_ACC_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0                        _MK_ADDR_CONST(0xff00a0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_RANGE                        31:0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_WOFFSET                      0x0
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0_SOC_ADC_NUM_SAMPLES_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0                        _MK_ADDR_CONST(0xff00a4)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SECURE                         0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SCR                    0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_WORD_COUNT                     0x1
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_RESET_VAL                      _MK_MASK_CONST(0xe03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_READ_MASK                      _MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0xff03)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_FIELD                      _MK_FIELD_CONST(0xff, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_RANGE                      15:8
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_WOFFSET                    0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_DEFAULT                    _MK_MASK_CONST(0xe)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SHIFT                  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_FIELD                  _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_RANGE                  1:1
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_WOFFSET                        0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_INIT_ENUM                      OSC_DIV
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_PLLP_OUT0                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_SEL_OSC_DIV                        _MK_ENUM_CONST(1)

#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_RANGE                       0:0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_WOFFSET                     0x0
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0_SOC_ADC_REF_CLK_CFG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


//
// REGISTER LIST
//
#define LIST_ARCLK_RST_REGS(_op_) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SHSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SHSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SHSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TOP_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_KFUSE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE2_0) \
_op_(CLK_RST_CONTROLLER_GPU_ISOB_CTRL_0) \
_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0) \
_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0) \
_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0) \
_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0) \
_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0) \
_op_(CLK_RST_CONTROLLER_LOCK_BOND_OUT_0) \
_op_(CLK_RST_CONTROLLER_INTSTATUS_0) \
_op_(CLK_RST_CONTROLLER_SPARE_REG0_0) \
_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0) \
_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0) \
_op_(CLK_RST_CONTROLLER_INTMASK_0) \
_op_(CLK_RST_CONTROLLER_EMC_MISC_0) \
_op_(CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PCIE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PCIE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0) \
_op_(CLK_RST_CONTROLLER_PLLE_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLE_BASE1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL2_0) \
_op_(CLK_RST_CONTROLLER_PLLE_AUX_0) \
_op_(CLK_RST_CONTROLLER_SATA_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_SATA_PLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_PCIE_PLL_CFG_0) \
_op_(CLK_RST_CONTROLLER_XUSBIO_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_XUSBIO_PLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_PLLE_AUX1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0) \
_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLM_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLM_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLP_RESHIFT_0) \
_op_(CLK_RST_CONTROLLER_PLLP_OUTC_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLP_MISC2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0) \
_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLA_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0) \
_op_(CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_ISP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
_op_(CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMC_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMC_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DTV_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DTV_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0) \
_op_(CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_LA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DP2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DP2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_LA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOR0_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DPAUX1_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DPAUX1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DPAUX1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_SATA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SE_0) \
_op_(CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_UTMIP_PLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0_0) \
_op_(CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_APB2APE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_APB2APE_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_IQC1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0) \
_op_(CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_APE_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_OUT_0) \
_op_(CLK_RST_CONTROLLER_PLLREFE_MISC1_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC2_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLC3_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DVFS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DVFS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0) \
_op_(CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_VIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_OUT1_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLA1_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_I2C_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0) \
_op_(CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0) \
_op_(CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0) \
_op_(CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0) \
_op_(CLK_RST_CONTROLLER_CLK_MPHY_MISC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_MISC_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_MISC2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_MISC1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CFG_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_SW_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0) \
_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_LATENCY_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_DLL_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_DIV_CLK_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_EMCSB_PLLC_SHAPER_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_CVC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_HSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNBPMP_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_BPMP_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_THERM_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_DVFS_0) \
_op_(CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UFS_AON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_XUSB_AON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOPM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AOVC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GPIO_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_AON_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_AON_CPU_PGRST_CTRL_0) \
_op_(CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0) \
_op_(CLK_RST_CONTROLLER_CAN1_CORE_RATE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0) \
_op_(CLK_RST_CONTROLLER_CAN2_CORE_RATE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_BASE_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_0_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_1_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_2_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_3_0) \
_op_(CLK_RST_CONTROLLER_PLLAON_MISC_4_0) \
_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
_op_(CLK_RST_CONTROLLER_CLK_M_DIVIDE_0) \
_op_(CLK_RST_CONTROLLER_OSC_PRE_CLAMP_CTL_0) \
_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
_op_(CLK_RST_CONTROLLER_MISC_REG0_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0) \
_op_(CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_TSC_OSC_SUPER_CLK_DIVIDER_0) \
_op_(CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_AON_I2C_SLOW_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_CAN_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_DMIC5_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_GPIO_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_HSP_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C10_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C2_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_I2C8_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_MSS_ENCRYPT_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_OSC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PLLAON_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_PWM4_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_SPI2_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_TSC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UARTC_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UARTG_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UART_MIPI_CAL_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_UFS_0) \
_op_(CLK_RST_CONTROLLER_AON_SCR_TOUCH_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_ACTMON_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_PM_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_HSP_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_TSCTNSCE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_TKE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_GTE_CLR_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0) \
_op_(CLK_RST_CONTROLLER_SCE_NIC_RATE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_OVR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_PLL_CFG_SCE_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_ACTIVE_IRQFIQ_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_IDLE_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_STBY_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_TGT_DORMANT_SHALLOW_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SW_INTERFACE_CTL_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_CTL_0_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_TIMEOUT_CTL_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_PLL_LOCK_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_PLL_PWRUP_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_SWITCH_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_SWDIV_PLL_DLY_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_1US_CYCLE_COUNT_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_STATUS_0) \
_op_(CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_SHARED_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_PRIVATE_0) \
_op_(CLK_RST_CONTROLLER_SCE_SCR_DVFS_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_COEFF_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG3_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL1_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_CTRL2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_MISC_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_COEFF_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_DATA_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_ADDR_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_READ_DATA_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_DEBUG2_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_SW_FREQ_REQ_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT0_0) \
_op_(CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIC_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSID_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSID_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_SET_0) \
_op_(CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_SET_0) \
_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0) \
_op_(CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_CTRL_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_MONITOR_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_OVERRIDE_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_ACC_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_NUM_SAMPLES_0) \
_op_(CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000

//
// ARCLK_RST REGISTER BANKS
//

#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_DEV_TOP_GTE_0
#define CLK_RST_CONTROLLER0_LAST_REG 0x0038 // CLK_RST_CONTROLLER_RST_DEV_GPU_CLR_0
#define CLK_RST_CONTROLLER1_FIRST_REG 0x1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_FUSE_0
#define CLK_RST_CONTROLLER1_LAST_REG 0x1014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPU_CLR_0
#define CLK_RST_CONTROLLER2_FIRST_REG 0x2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_FUSE_0
#define CLK_RST_CONTROLLER2_LAST_REG 0x2004 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPU_0
#define CLK_RST_CONTROLLER3_FIRST_REG 0x3000 // CLK_RST_CONTROLLER_CLK_SPARE0_0
#define CLK_RST_CONTROLLER3_LAST_REG 0x3024 // CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
#define CLK_RST_CONTROLLER4_FIRST_REG 0x30a4 // CLK_RST_CONTROLLER_INTSTATUS_0
#define CLK_RST_CONTROLLER4_LAST_REG 0x30a8 // CLK_RST_CONTROLLER_SPARE_REG0_0
#define CLK_RST_CONTROLLER5_FIRST_REG 0x30b8 // CLK_RST_CONTROLLER_CLK_MASK_ARM_0
#define CLK_RST_CONTROLLER5_LAST_REG 0x30bc // CLK_RST_CONTROLLER_MISC_CLK_ENB_0
#define CLK_RST_CONTROLLER6_FIRST_REG 0x30c4 // CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0
#define CLK_RST_CONTROLLER6_LAST_REG 0x30cc // CLK_RST_CONTROLLER_INTMASK_0
#define CLK_RST_CONTROLLER7_FIRST_REG 0x30d4 // CLK_RST_CONTROLLER_EMC_MISC_0
#define CLK_RST_CONTROLLER7_LAST_REG 0x30d8 // CLK_RST_CONTROLLER_NAFLL_ADC_RDACK_OVERRIDE_0
#define CLK_RST_CONTROLLER8_FIRST_REG 0x40000 // CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0
#define CLK_RST_CONTROLLER8_LAST_REG 0x40020 // CLK_RST_CONTROLLER_RST_DEV_PCIE_CLR_0
#define CLK_RST_CONTROLLER9_FIRST_REG 0x41000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_0
#define CLK_RST_CONTROLLER9_LAST_REG 0x41008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PCIE_CLR_0
#define CLK_RST_CONTROLLER10_FIRST_REG 0x42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0
#define CLK_RST_CONTROLLER10_LAST_REG 0x42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PCIE_0
#define CLK_RST_CONTROLLER11_FIRST_REG 0x43000 // CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
#define CLK_RST_CONTROLLER11_LAST_REG 0x43034 // CLK_RST_CONTROLLER_PLLE_AUX1_0
#define CLK_RST_CONTROLLER12_FIRST_REG 0x44000 // CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0
#define CLK_RST_CONTROLLER12_LAST_REG 0x44000 // CLK_RST_CONTROLLER_CLK_SOURCE_IPFS_0
#define CLK_RST_CONTROLLER13_FIRST_REG 0x50000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC_0
#define CLK_RST_CONTROLLER13_LAST_REG 0x50020 // CLK_RST_CONTROLLER_PLLC_MISC_4_0
#define CLK_RST_CONTROLLER14_FIRST_REG 0x51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER14_LAST_REG 0x51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC_0
#define CLK_RST_CONTROLLER15_FIRST_REG 0x60000 // CLK_RST_CONTROLLER_PLLM_BASE_0
#define CLK_RST_CONTROLLER15_LAST_REG 0x60000 // CLK_RST_CONTROLLER_PLLM_BASE_0
#define CLK_RST_CONTROLLER16_FIRST_REG 0x60008 // CLK_RST_CONTROLLER_PLLM_MISC1_0
#define CLK_RST_CONTROLLER16_LAST_REG 0x6002c // CLK_RST_CONTROLLER_PLLMB_SS_CTRL2_0
#define CLK_RST_CONTROLLER17_FIRST_REG 0x70000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLP_0
#define CLK_RST_CONTROLLER17_LAST_REG 0x70024 // CLK_RST_CONTROLLER_PLLP_MISC2_0
#define CLK_RST_CONTROLLER18_FIRST_REG 0x71000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER18_LAST_REG 0x71000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLP_0
#define CLK_RST_CONTROLLER19_FIRST_REG 0x80000 // CLK_RST_CONTROLLER_PLLA_BASE_0
#define CLK_RST_CONTROLLER19_LAST_REG 0x80018 // CLK_RST_CONTROLLER_PLLA_MISC_4_0
#define CLK_RST_CONTROLLER20_FIRST_REG 0xa0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLD_0
#define CLK_RST_CONTROLLER20_LAST_REG 0xa000c // CLK_RST_CONTROLLER_PLLD_BASE_0
#define CLK_RST_CONTROLLER21_FIRST_REG 0xa0014 // CLK_RST_CONTROLLER_PLLD_MISC_0
#define CLK_RST_CONTROLLER21_LAST_REG 0xa0028 // CLK_RST_CONTROLLER_PLLD_SS_CTRL2_0
#define CLK_RST_CONTROLLER22_FIRST_REG 0xa1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0
#define CLK_RST_CONTROLLER22_LAST_REG 0xa1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLD_0
#define CLK_RST_CONTROLLER23_FIRST_REG 0xc0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_0
#define CLK_RST_CONTROLLER23_LAST_REG 0xc0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S2_CLR_0
#define CLK_RST_CONTROLLER24_FIRST_REG 0xc1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER24_LAST_REG 0xc1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S2_0
#define CLK_RST_CONTROLLER25_FIRST_REG 0xc2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0
#define CLK_RST_CONTROLLER25_LAST_REG 0xc2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2_0
#define CLK_RST_CONTROLLER26_FIRST_REG 0xd0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_0
#define CLK_RST_CONTROLLER26_LAST_REG 0xd0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S3_CLR_0
#define CLK_RST_CONTROLLER27_FIRST_REG 0xd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER27_LAST_REG 0xd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S3_0
#define CLK_RST_CONTROLLER28_FIRST_REG 0xd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S3_0
#define CLK_RST_CONTROLLER28_LAST_REG 0xd2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3_0
#define CLK_RST_CONTROLLER29_FIRST_REG 0xe0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_0
#define CLK_RST_CONTROLLER29_LAST_REG 0xe0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPDIF_CLR_0
#define CLK_RST_CONTROLLER30_FIRST_REG 0xe1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER30_LAST_REG 0xe1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPDIF_0
#define CLK_RST_CONTROLLER31_FIRST_REG 0xe2000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0
#define CLK_RST_CONTROLLER31_LAST_REG 0xe2004 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0
#define CLK_RST_CONTROLLER32_FIRST_REG 0xe3000 // CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER32_LAST_REG 0xe3000 // CLK_RST_CONTROLLER_CLK_SPARE_SPDIF_0
#define CLK_RST_CONTROLLER33_FIRST_REG 0x110000 // CLK_RST_CONTROLLER_RST_DEV_SPI3_0
#define CLK_RST_CONTROLLER33_LAST_REG 0x110008 // CLK_RST_CONTROLLER_RST_DEV_SPI3_CLR_0
#define CLK_RST_CONTROLLER34_FIRST_REG 0x111000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0
#define CLK_RST_CONTROLLER34_LAST_REG 0x111008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_CLR_0
#define CLK_RST_CONTROLLER35_FIRST_REG 0x112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER35_LAST_REG 0x112000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI3_0
#define CLK_RST_CONTROLLER36_FIRST_REG 0x113000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER36_LAST_REG 0x113000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0
#define CLK_RST_CONTROLLER37_FIRST_REG 0x120000 // CLK_RST_CONTROLLER_RST_DEV_I2C1_0
#define CLK_RST_CONTROLLER37_LAST_REG 0x120008 // CLK_RST_CONTROLLER_RST_DEV_I2C1_CLR_0
#define CLK_RST_CONTROLLER38_FIRST_REG 0x121000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0
#define CLK_RST_CONTROLLER38_LAST_REG 0x121008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_CLR_0
#define CLK_RST_CONTROLLER39_FIRST_REG 0x122000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER39_LAST_REG 0x122000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C1_0
#define CLK_RST_CONTROLLER40_FIRST_REG 0x123000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER40_LAST_REG 0x123000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0
#define CLK_RST_CONTROLLER41_FIRST_REG 0x130000 // CLK_RST_CONTROLLER_RST_DEV_I2C5_0
#define CLK_RST_CONTROLLER41_LAST_REG 0x130008 // CLK_RST_CONTROLLER_RST_DEV_I2C5_CLR_0
#define CLK_RST_CONTROLLER42_FIRST_REG 0x131000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_0
#define CLK_RST_CONTROLLER42_LAST_REG 0x131008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C5_CLR_0
#define CLK_RST_CONTROLLER43_FIRST_REG 0x132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER43_LAST_REG 0x132000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C5_0
#define CLK_RST_CONTROLLER44_FIRST_REG 0x133000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER44_LAST_REG 0x133000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0
#define CLK_RST_CONTROLLER45_FIRST_REG 0x140000 // CLK_RST_CONTROLLER_RST_DEV_SPI1_0
#define CLK_RST_CONTROLLER45_LAST_REG 0x140008 // CLK_RST_CONTROLLER_RST_DEV_SPI1_CLR_0
#define CLK_RST_CONTROLLER46_FIRST_REG 0x141000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0
#define CLK_RST_CONTROLLER46_LAST_REG 0x141008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_CLR_0
#define CLK_RST_CONTROLLER47_FIRST_REG 0x142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER47_LAST_REG 0x142000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI1_0
#define CLK_RST_CONTROLLER48_FIRST_REG 0x143000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER48_LAST_REG 0x143000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0
#define CLK_RST_CONTROLLER49_FIRST_REG 0x170000 // CLK_RST_CONTROLLER_RST_DEV_ISP_0
#define CLK_RST_CONTROLLER49_LAST_REG 0x170008 // CLK_RST_CONTROLLER_RST_DEV_ISP_CLR_0
#define CLK_RST_CONTROLLER50_FIRST_REG 0x171000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_0
#define CLK_RST_CONTROLLER50_LAST_REG 0x171008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ISP_CLR_0
#define CLK_RST_CONTROLLER51_FIRST_REG 0x172000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER51_LAST_REG 0x172000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ISP_0
#define CLK_RST_CONTROLLER52_FIRST_REG 0x173000 // CLK_RST_CONTROLLER_CLK_SOURCE_ISP_0
#define CLK_RST_CONTROLLER52_LAST_REG 0x173004 // CLK_RST_CONTROLLER_ISP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER53_FIRST_REG 0x174000 // CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER53_LAST_REG 0x174000 // CLK_RST_CONTROLLER_CLK_SPARE_ISP_0
#define CLK_RST_CONTROLLER54_FIRST_REG 0x180000 // CLK_RST_CONTROLLER_RST_DEV_VI_0
#define CLK_RST_CONTROLLER54_LAST_REG 0x180014 // CLK_RST_CONTROLLER_RST_DEV_TSCTNVI_CLR_0
#define CLK_RST_CONTROLLER55_FIRST_REG 0x181000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_0
#define CLK_RST_CONTROLLER55_LAST_REG 0x181008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_CLR_0
#define CLK_RST_CONTROLLER56_FIRST_REG 0x182000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER56_LAST_REG 0x182000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_0
#define CLK_RST_CONTROLLER57_FIRST_REG 0x183000 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
#define CLK_RST_CONTROLLER57_LAST_REG 0x183000 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
#define CLK_RST_CONTROLLER58_FIRST_REG 0x183008 // CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER58_LAST_REG 0x183008 // CLK_RST_CONTROLLER_VI_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER59_FIRST_REG 0x190000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC1_0
#define CLK_RST_CONTROLLER59_LAST_REG 0x190008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER60_FIRST_REG 0x191000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_0
#define CLK_RST_CONTROLLER60_LAST_REG 0x191008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC1_CLR_0
#define CLK_RST_CONTROLLER61_FIRST_REG 0x192000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER61_LAST_REG 0x192000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC1_0
#define CLK_RST_CONTROLLER62_FIRST_REG 0x193000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER62_LAST_REG 0x193000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
#define CLK_RST_CONTROLLER63_FIRST_REG 0x1a0000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC2_0
#define CLK_RST_CONTROLLER63_LAST_REG 0x1a0008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC2_CLR_0
#define CLK_RST_CONTROLLER64_FIRST_REG 0x1a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_0
#define CLK_RST_CONTROLLER64_LAST_REG 0x1a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC2_CLR_0
#define CLK_RST_CONTROLLER65_FIRST_REG 0x1a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0
#define CLK_RST_CONTROLLER65_LAST_REG 0x1a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC2_0
#define CLK_RST_CONTROLLER66_FIRST_REG 0x1a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0
#define CLK_RST_CONTROLLER66_LAST_REG 0x1a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0
#define CLK_RST_CONTROLLER67_FIRST_REG 0x1b0000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC4_0
#define CLK_RST_CONTROLLER67_LAST_REG 0x1b0008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER68_FIRST_REG 0x1b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_0
#define CLK_RST_CONTROLLER68_LAST_REG 0x1b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC4_CLR_0
#define CLK_RST_CONTROLLER69_FIRST_REG 0x1b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER69_LAST_REG 0x1b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC4_0
#define CLK_RST_CONTROLLER70_FIRST_REG 0x1b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0
#define CLK_RST_CONTROLLER70_LAST_REG 0x1b3010 // CLK_RST_CONTROLLER_SDMMC4_DIV_CLK_SHAPER_CTRL_0
#define CLK_RST_CONTROLLER71_FIRST_REG 0x1c0000 // CLK_RST_CONTROLLER_RST_DEV_UARTA_0
#define CLK_RST_CONTROLLER71_LAST_REG 0x1c0008 // CLK_RST_CONTROLLER_RST_DEV_UARTA_CLR_0
#define CLK_RST_CONTROLLER72_FIRST_REG 0x1c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0
#define CLK_RST_CONTROLLER72_LAST_REG 0x1c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_CLR_0
#define CLK_RST_CONTROLLER73_FIRST_REG 0x1c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER73_LAST_REG 0x1c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTA_0
#define CLK_RST_CONTROLLER74_FIRST_REG 0x1c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER74_LAST_REG 0x1c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0
#define CLK_RST_CONTROLLER75_FIRST_REG 0x1d0000 // CLK_RST_CONTROLLER_RST_DEV_UARTB_0
#define CLK_RST_CONTROLLER75_LAST_REG 0x1d0008 // CLK_RST_CONTROLLER_RST_DEV_UARTB_CLR_0
#define CLK_RST_CONTROLLER76_FIRST_REG 0x1d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0
#define CLK_RST_CONTROLLER76_LAST_REG 0x1d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_CLR_0
#define CLK_RST_CONTROLLER77_FIRST_REG 0x1d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER77_LAST_REG 0x1d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTB_0
#define CLK_RST_CONTROLLER78_FIRST_REG 0x1d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER78_LAST_REG 0x1d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0
#define CLK_RST_CONTROLLER79_FIRST_REG 0x1e0000 // CLK_RST_CONTROLLER_RST_DEV_HOST1X_0
#define CLK_RST_CONTROLLER79_LAST_REG 0x1e0008 // CLK_RST_CONTROLLER_RST_DEV_HOST1X_CLR_0
#define CLK_RST_CONTROLLER80_FIRST_REG 0x1e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_0
#define CLK_RST_CONTROLLER80_LAST_REG 0x1e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HOST1X_CLR_0
#define CLK_RST_CONTROLLER81_FIRST_REG 0x1e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER81_LAST_REG 0x1e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HOST1X_0
#define CLK_RST_CONTROLLER82_FIRST_REG 0x1e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER82_LAST_REG 0x1e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
#define CLK_RST_CONTROLLER83_FIRST_REG 0x200000 // CLK_RST_CONTROLLER_RST_DEV_EMC_0
#define CLK_RST_CONTROLLER83_LAST_REG 0x200008 // CLK_RST_CONTROLLER_RST_DEV_EMC_CLR_0
#define CLK_RST_CONTROLLER84_FIRST_REG 0x201000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_0
#define CLK_RST_CONTROLLER84_LAST_REG 0x201008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMC_CLR_0
#define CLK_RST_CONTROLLER85_FIRST_REG 0x202000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER85_LAST_REG 0x202000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMC_0
#define CLK_RST_CONTROLLER86_FIRST_REG 0x203000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0
#define CLK_RST_CONTROLLER86_LAST_REG 0x203014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE_0
#define CLK_RST_CONTROLLER87_FIRST_REG 0x204000 // CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER87_LAST_REG 0x204000 // CLK_RST_CONTROLLER_CLK_SPARE_EMC_0
#define CLK_RST_CONTROLLER88_FIRST_REG 0x220000 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_0
#define CLK_RST_CONTROLLER88_LAST_REG 0x220008 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER89_FIRST_REG 0x221000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_0
#define CLK_RST_CONTROLLER89_LAST_REG 0x221008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH4_CLR_0
#define CLK_RST_CONTROLLER90_FIRST_REG 0x222000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER90_LAST_REG 0x222000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH4_0
#define CLK_RST_CONTROLLER91_FIRST_REG 0x223000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER91_LAST_REG 0x223000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4_0
#define CLK_RST_CONTROLLER92_FIRST_REG 0x230000 // CLK_RST_CONTROLLER_RST_DEV_SPI4_0
#define CLK_RST_CONTROLLER92_LAST_REG 0x230008 // CLK_RST_CONTROLLER_RST_DEV_SPI4_CLR_0
#define CLK_RST_CONTROLLER93_FIRST_REG 0x231000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_0
#define CLK_RST_CONTROLLER93_LAST_REG 0x231008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI4_CLR_0
#define CLK_RST_CONTROLLER94_FIRST_REG 0x232000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0
#define CLK_RST_CONTROLLER94_LAST_REG 0x232000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI4_0
#define CLK_RST_CONTROLLER95_FIRST_REG 0x233000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0
#define CLK_RST_CONTROLLER95_LAST_REG 0x233000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI4_0
#define CLK_RST_CONTROLLER96_FIRST_REG 0x240000 // CLK_RST_CONTROLLER_RST_DEV_I2C3_0
#define CLK_RST_CONTROLLER96_LAST_REG 0x240008 // CLK_RST_CONTROLLER_RST_DEV_I2C3_CLR_0
#define CLK_RST_CONTROLLER97_FIRST_REG 0x241000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0
#define CLK_RST_CONTROLLER97_LAST_REG 0x241008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_CLR_0
#define CLK_RST_CONTROLLER98_FIRST_REG 0x242000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER98_LAST_REG 0x242000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C3_0
#define CLK_RST_CONTROLLER99_FIRST_REG 0x243000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER99_LAST_REG 0x243000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0
#define CLK_RST_CONTROLLER100_FIRST_REG 0x250000 // CLK_RST_CONTROLLER_RST_DEV_SDMMC3_0
#define CLK_RST_CONTROLLER100_LAST_REG 0x250008 // CLK_RST_CONTROLLER_RST_DEV_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER101_FIRST_REG 0x251000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_0
#define CLK_RST_CONTROLLER101_LAST_REG 0x251008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC3_CLR_0
#define CLK_RST_CONTROLLER102_FIRST_REG 0x252000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER102_LAST_REG 0x252000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC3_0
#define CLK_RST_CONTROLLER103_FIRST_REG 0x253000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER103_LAST_REG 0x253000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0
#define CLK_RST_CONTROLLER104_FIRST_REG 0x260000 // CLK_RST_CONTROLLER_RST_DEV_UARTD_0
#define CLK_RST_CONTROLLER104_LAST_REG 0x260008 // CLK_RST_CONTROLLER_RST_DEV_UARTD_CLR_0
#define CLK_RST_CONTROLLER105_FIRST_REG 0x261000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_0
#define CLK_RST_CONTROLLER105_LAST_REG 0x261008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTD_CLR_0
#define CLK_RST_CONTROLLER106_FIRST_REG 0x262000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER106_LAST_REG 0x262000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTD_0
#define CLK_RST_CONTROLLER107_FIRST_REG 0x263000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER107_LAST_REG 0x263000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0
#define CLK_RST_CONTROLLER108_FIRST_REG 0x280000 // CLK_RST_CONTROLLER_RST_DEV_CSITE_0
#define CLK_RST_CONTROLLER108_LAST_REG 0x280008 // CLK_RST_CONTROLLER_RST_DEV_CSITE_CLR_0
#define CLK_RST_CONTROLLER109_FIRST_REG 0x281000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_0
#define CLK_RST_CONTROLLER109_LAST_REG 0x281008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CSITE_CLR_0
#define CLK_RST_CONTROLLER110_FIRST_REG 0x282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER110_LAST_REG 0x282000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CSITE_0
#define CLK_RST_CONTROLLER111_FIRST_REG 0x283000 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER111_LAST_REG 0x283000 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
#define CLK_RST_CONTROLLER112_FIRST_REG 0x290000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_0
#define CLK_RST_CONTROLLER112_LAST_REG 0x290008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S1_CLR_0
#define CLK_RST_CONTROLLER113_FIRST_REG 0x291000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER113_LAST_REG 0x291000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S1_0
#define CLK_RST_CONTROLLER114_FIRST_REG 0x292000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
#define CLK_RST_CONTROLLER114_LAST_REG 0x292004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1_0
#define CLK_RST_CONTROLLER115_FIRST_REG 0x2a0000 // CLK_RST_CONTROLLER_RST_DEV_DTV_0
#define CLK_RST_CONTROLLER115_LAST_REG 0x2a0008 // CLK_RST_CONTROLLER_RST_DEV_DTV_CLR_0
#define CLK_RST_CONTROLLER116_FIRST_REG 0x2a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_0
#define CLK_RST_CONTROLLER116_LAST_REG 0x2a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DTV_CLR_0
#define CLK_RST_CONTROLLER117_FIRST_REG 0x2a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0
#define CLK_RST_CONTROLLER117_LAST_REG 0x2a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DTV_0
#define CLK_RST_CONTROLLER118_FIRST_REG 0x2a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0
#define CLK_RST_CONTROLLER118_LAST_REG 0x2a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DTV_0
#define CLK_RST_CONTROLLER119_FIRST_REG 0x2b0000 // CLK_RST_CONTROLLER_RST_DEV_TSEC_0
#define CLK_RST_CONTROLLER119_LAST_REG 0x2b0008 // CLK_RST_CONTROLLER_RST_DEV_TSEC_CLR_0
#define CLK_RST_CONTROLLER120_FIRST_REG 0x2b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_0
#define CLK_RST_CONTROLLER120_LAST_REG 0x2b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSEC_CLR_0
#define CLK_RST_CONTROLLER121_FIRST_REG 0x2b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER121_LAST_REG 0x2b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSEC_0
#define CLK_RST_CONTROLLER122_FIRST_REG 0x2b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSEC_0
#define CLK_RST_CONTROLLER122_LAST_REG 0x2b3004 // CLK_RST_CONTROLLER_TSEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER123_FIRST_REG 0x2c0000 // CLK_RST_CONTROLLER_RST_DEV_LA_0
#define CLK_RST_CONTROLLER123_LAST_REG 0x2c0014 // CLK_RST_CONTROLLER_RST_DEV_DP2_CLR_0
#define CLK_RST_CONTROLLER124_FIRST_REG 0x2c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_LA_0
#define CLK_RST_CONTROLLER124_LAST_REG 0x2c1014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DP2_CLR_0
#define CLK_RST_CONTROLLER125_FIRST_REG 0x2c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_LA_0
#define CLK_RST_CONTROLLER125_LAST_REG 0x2c2004 // CLK_RST_CONTROLLER_BOND_OUT_IP_DP2_0
#define CLK_RST_CONTROLLER126_FIRST_REG 0x2c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER126_LAST_REG 0x2c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
#define CLK_RST_CONTROLLER127_FIRST_REG 0x300000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_0
#define CLK_RST_CONTROLLER127_LAST_REG 0x300008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S4_CLR_0
#define CLK_RST_CONTROLLER128_FIRST_REG 0x301000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER128_LAST_REG 0x301000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S4_0
#define CLK_RST_CONTROLLER129_FIRST_REG 0x302000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S4_0
#define CLK_RST_CONTROLLER129_LAST_REG 0x302004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4_0
#define CLK_RST_CONTROLLER130_FIRST_REG 0x310000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_0
#define CLK_RST_CONTROLLER130_LAST_REG 0x310008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S5_CLR_0
#define CLK_RST_CONTROLLER131_FIRST_REG 0x311000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER131_LAST_REG 0x311000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S5_0
#define CLK_RST_CONTROLLER132_FIRST_REG 0x312000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S5_0
#define CLK_RST_CONTROLLER132_LAST_REG 0x312004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5_0
#define CLK_RST_CONTROLLER133_FIRST_REG 0x320000 // CLK_RST_CONTROLLER_RST_DEV_I2C4_0
#define CLK_RST_CONTROLLER133_LAST_REG 0x320008 // CLK_RST_CONTROLLER_RST_DEV_I2C4_CLR_0
#define CLK_RST_CONTROLLER134_FIRST_REG 0x321000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0
#define CLK_RST_CONTROLLER134_LAST_REG 0x321008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_CLR_0
#define CLK_RST_CONTROLLER135_FIRST_REG 0x322000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER135_LAST_REG 0x322000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C4_0
#define CLK_RST_CONTROLLER136_FIRST_REG 0x323000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER136_LAST_REG 0x323000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0
#define CLK_RST_CONTROLLER137_FIRST_REG 0x330000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_0
#define CLK_RST_CONTROLLER137_LAST_REG 0x330008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AHUB_CLR_0
#define CLK_RST_CONTROLLER138_FIRST_REG 0x331000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER138_LAST_REG 0x331000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AHUB_0
#define CLK_RST_CONTROLLER139_FIRST_REG 0x332000 // CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER139_LAST_REG 0x332000 // CLK_RST_CONTROLLER_CLK_SOURCE_AHUB_0
#define CLK_RST_CONTROLLER140_FIRST_REG 0x340000 // CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER140_LAST_REG 0x340008 // CLK_RST_CONTROLLER_RST_DEV_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER141_FIRST_REG 0x341000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER141_LAST_REG 0x341008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA2CODEC_2X_CLR_0
#define CLK_RST_CONTROLLER142_FIRST_REG 0x342000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER142_LAST_REG 0x342000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER143_FIRST_REG 0x343000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER143_LAST_REG 0x343000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X_0
#define CLK_RST_CONTROLLER144_FIRST_REG 0x360000 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_0
#define CLK_RST_CONTROLLER144_LAST_REG 0x360008 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER145_FIRST_REG 0x361000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_0
#define CLK_RST_CONTROLLER145_LAST_REG 0x361008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH1_CLR_0
#define CLK_RST_CONTROLLER146_FIRST_REG 0x362000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER146_LAST_REG 0x362000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH1_0
#define CLK_RST_CONTROLLER147_FIRST_REG 0x363000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER147_LAST_REG 0x363000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1_0
#define CLK_RST_CONTROLLER148_FIRST_REG 0x370000 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_0
#define CLK_RST_CONTROLLER148_LAST_REG 0x370008 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER149_FIRST_REG 0x371000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_0
#define CLK_RST_CONTROLLER149_LAST_REG 0x371008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH2_CLR_0
#define CLK_RST_CONTROLLER150_FIRST_REG 0x372000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER150_LAST_REG 0x372000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH2_0
#define CLK_RST_CONTROLLER151_FIRST_REG 0x373000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER151_LAST_REG 0x373000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2_0
#define CLK_RST_CONTROLLER152_FIRST_REG 0x380000 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_0
#define CLK_RST_CONTROLLER152_LAST_REG 0x380008 // CLK_RST_CONTROLLER_RST_DEV_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER153_FIRST_REG 0x381000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_0
#define CLK_RST_CONTROLLER153_LAST_REG 0x381008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EXTPERIPH3_CLR_0
#define CLK_RST_CONTROLLER154_FIRST_REG 0x382000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER154_LAST_REG 0x382000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EXTPERIPH3_0
#define CLK_RST_CONTROLLER155_FIRST_REG 0x383000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER155_LAST_REG 0x383000 // CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3_0
#define CLK_RST_CONTROLLER156_FIRST_REG 0x390000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0
#define CLK_RST_CONTROLLER156_LAST_REG 0x390008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER157_FIRST_REG 0x391000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER157_LAST_REG 0x391000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C_SLOW_0
#define CLK_RST_CONTROLLER158_FIRST_REG 0x392000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER158_LAST_REG 0x392000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0
#define CLK_RST_CONTROLLER159_FIRST_REG 0x3a0000 // CLK_RST_CONTROLLER_RST_DEV_SOR1_0
#define CLK_RST_CONTROLLER159_LAST_REG 0x3a0008 // CLK_RST_CONTROLLER_RST_DEV_SOR1_CLR_0
#define CLK_RST_CONTROLLER160_FIRST_REG 0x3a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_0
#define CLK_RST_CONTROLLER160_LAST_REG 0x3a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR1_CLR_0
#define CLK_RST_CONTROLLER161_FIRST_REG 0x3a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER161_LAST_REG 0x3a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR1_0
#define CLK_RST_CONTROLLER162_FIRST_REG 0x3a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER162_LAST_REG 0x3a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR1_0
#define CLK_RST_CONTROLLER163_FIRST_REG 0x3b0000 // CLK_RST_CONTROLLER_RST_DEV_SOR0_0
#define CLK_RST_CONTROLLER163_LAST_REG 0x3b002c // CLK_RST_CONTROLLER_RST_DEV_CEC_CLR_0
#define CLK_RST_CONTROLLER164_FIRST_REG 0x3b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOR0_0
#define CLK_RST_CONTROLLER164_LAST_REG 0x3b102c // CLK_RST_CONTROLLER_CLK_OUT_ENB_CEC_CLR_0
#define CLK_RST_CONTROLLER165_FIRST_REG 0x3b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOR0_0
#define CLK_RST_CONTROLLER165_LAST_REG 0x3b200c // CLK_RST_CONTROLLER_BOND_OUT_IP_CEC_0
#define CLK_RST_CONTROLLER166_FIRST_REG 0x3b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER166_LAST_REG 0x3b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0
#define CLK_RST_CONTROLLER167_FIRST_REG 0x3b4000 // CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER167_LAST_REG 0x3b4000 // CLK_RST_CONTROLLER_CLK_SPARE_SOR0_0
#define CLK_RST_CONTROLLER168_FIRST_REG 0x3c0000 // CLK_RST_CONTROLLER_RST_DEV_SATA_0
#define CLK_RST_CONTROLLER168_LAST_REG 0x3c0008 // CLK_RST_CONTROLLER_RST_DEV_SATA_CLR_0
#define CLK_RST_CONTROLLER169_FIRST_REG 0x3c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_0
#define CLK_RST_CONTROLLER169_LAST_REG 0x3c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SATA_CLR_0
#define CLK_RST_CONTROLLER170_FIRST_REG 0x3c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER170_LAST_REG 0x3c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SATA_0
#define CLK_RST_CONTROLLER171_FIRST_REG 0x3c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SATA_OOB_0
#define CLK_RST_CONTROLLER171_LAST_REG 0x3c3004 // CLK_RST_CONTROLLER_CLK_SOURCE_SATA_0
#define CLK_RST_CONTROLLER172_FIRST_REG 0x3c4000 // CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER172_LAST_REG 0x3c4000 // CLK_RST_CONTROLLER_CLK_SPARE_SATA_0
#define CLK_RST_CONTROLLER173_FIRST_REG 0x3d0000 // CLK_RST_CONTROLLER_RST_DEV_HDA_0
#define CLK_RST_CONTROLLER173_LAST_REG 0x3d0008 // CLK_RST_CONTROLLER_RST_DEV_HDA_CLR_0
#define CLK_RST_CONTROLLER174_FIRST_REG 0x3d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_0
#define CLK_RST_CONTROLLER174_LAST_REG 0x3d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_HDA_CLR_0
#define CLK_RST_CONTROLLER175_FIRST_REG 0x3d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER175_LAST_REG 0x3d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_HDA_0
#define CLK_RST_CONTROLLER176_FIRST_REG 0x3d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER176_LAST_REG 0x3d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_HDA_0
#define CLK_RST_CONTROLLER177_FIRST_REG 0x3e0000 // CLK_RST_CONTROLLER_RST_DEV_SE_0
#define CLK_RST_CONTROLLER177_LAST_REG 0x3e0008 // CLK_RST_CONTROLLER_RST_DEV_SE_CLR_0
#define CLK_RST_CONTROLLER178_FIRST_REG 0x3e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_0
#define CLK_RST_CONTROLLER178_LAST_REG 0x3e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SE_CLR_0
#define CLK_RST_CONTROLLER179_FIRST_REG 0x3e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER179_LAST_REG 0x3e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SE_0
#define CLK_RST_CONTROLLER180_FIRST_REG 0x3e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SE_0
#define CLK_RST_CONTROLLER180_LAST_REG 0x3e3004 // CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER181_FIRST_REG 0x3f0000 // CLK_RST_CONTROLLER_UTMIP_PLL_CFG0_0
#define CLK_RST_CONTROLLER181_LAST_REG 0x3f0014 // CLK_RST_CONTROLLER_XUSB_PLL_CFG0_0
#define CLK_RST_CONTROLLER182_FIRST_REG 0x400000 // CLK_RST_CONTROLLER_RST_DEV_APE_0
#define CLK_RST_CONTROLLER182_LAST_REG 0x400008 // CLK_RST_CONTROLLER_RST_DEV_APE_CLR_0
#define CLK_RST_CONTROLLER183_FIRST_REG 0x401000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_APE_0
#define CLK_RST_CONTROLLER183_LAST_REG 0x40102c // CLK_RST_CONTROLLER_CLK_OUT_ENB_IQC2_CLR_0
#define CLK_RST_CONTROLLER184_FIRST_REG 0x402000 // CLK_RST_CONTROLLER_BOND_OUT_IP_APE_0
#define CLK_RST_CONTROLLER184_LAST_REG 0x40200c // CLK_RST_CONTROLLER_BOND_OUT_IP_IQC2_0
#define CLK_RST_CONTROLLER185_FIRST_REG 0x403000 // CLK_RST_CONTROLLER_PROG_AUDIO_DLY_CLK_0
#define CLK_RST_CONTROLLER185_LAST_REG 0x403008 // CLK_RST_CONTROLLER_CLK_SOURCE_APE_0
#define CLK_RST_CONTROLLER186_FIRST_REG 0x410000 // CLK_RST_CONTROLLER_PLLD2_BASE_0
#define CLK_RST_CONTROLLER186_LAST_REG 0x410014 // CLK_RST_CONTROLLER_PLLD2_SS_CTRL2_0
#define CLK_RST_CONTROLLER187_FIRST_REG 0x420000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLREFE_0
#define CLK_RST_CONTROLLER187_LAST_REG 0x420018 // CLK_RST_CONTROLLER_PLLREFE_MISC1_0
#define CLK_RST_CONTROLLER188_FIRST_REG 0x421000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER188_LAST_REG 0x421000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLREFE_0
#define CLK_RST_CONTROLLER189_FIRST_REG 0x430000 // CLK_RST_CONTROLLER_PLLC2_BASE_0
#define CLK_RST_CONTROLLER189_LAST_REG 0x430014 // CLK_RST_CONTROLLER_PLLC2_MISC_4_0
#define CLK_RST_CONTROLLER190_FIRST_REG 0x440000 // CLK_RST_CONTROLLER_PLLC3_BASE_0
#define CLK_RST_CONTROLLER190_LAST_REG 0x440014 // CLK_RST_CONTROLLER_PLLC3_MISC_4_0
#define CLK_RST_CONTROLLER191_FIRST_REG 0x450000 // CLK_RST_CONTROLLER_PLLDP_BASE_0
#define CLK_RST_CONTROLLER191_LAST_REG 0x450014 // CLK_RST_CONTROLLER_PLLDP_SS_CTRL2_0
#define CLK_RST_CONTROLLER192_FIRST_REG 0x460000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PLLC4_0
#define CLK_RST_CONTROLLER192_LAST_REG 0x460020 // CLK_RST_CONTROLLER_PLLC4_SS_CTRL2_0
#define CLK_RST_CONTROLLER193_FIRST_REG 0x461000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER193_LAST_REG 0x461000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PLLC4_0
#define CLK_RST_CONTROLLER194_FIRST_REG 0x470000 // CLK_RST_CONTROLLER_RST_DEV_XUSB_0
#define CLK_RST_CONTROLLER194_LAST_REG 0x470008 // CLK_RST_CONTROLLER_RST_DEV_XUSB_CLR_0
#define CLK_RST_CONTROLLER195_FIRST_REG 0x471000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_0
#define CLK_RST_CONTROLLER195_LAST_REG 0x471008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_XUSB_CLR_0
#define CLK_RST_CONTROLLER196_FIRST_REG 0x472000 // CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER196_LAST_REG 0x472000 // CLK_RST_CONTROLLER_BOND_OUT_IP_XUSB_0
#define CLK_RST_CONTROLLER197_FIRST_REG 0x473000 // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST_0
#define CLK_RST_CONTROLLER197_LAST_REG 0x473010 // CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS_0
#define CLK_RST_CONTROLLER198_FIRST_REG 0x474000 // CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER198_LAST_REG 0x474000 // CLK_RST_CONTROLLER_CLK_SPARE_XUSB_0
#define CLK_RST_CONTROLLER199_FIRST_REG 0x4b0000 // CLK_RST_CONTROLLER_RST_DEV_DSIPADCTL_0
#define CLK_RST_CONTROLLER199_LAST_REG 0x4b0020 // CLK_RST_CONTROLLER_RST_DEV_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER200_FIRST_REG 0x4b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSI_0
#define CLK_RST_CONTROLLER200_LAST_REG 0x4b1014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER201_FIRST_REG 0x4b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSI_0
#define CLK_RST_CONTROLLER201_LAST_REG 0x4b2004 // CLK_RST_CONTROLLER_BOND_OUT_IP_MIPI_CAL_0
#define CLK_RST_CONTROLLER202_FIRST_REG 0x4b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0
#define CLK_RST_CONTROLLER202_LAST_REG 0x4b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP_0
#define CLK_RST_CONTROLLER203_FIRST_REG 0x4c0000 // CLK_RST_CONTROLLER_RST_DEV_DSIB_0
#define CLK_RST_CONTROLLER203_LAST_REG 0x4c0008 // CLK_RST_CONTROLLER_RST_DEV_DSIB_CLR_0
#define CLK_RST_CONTROLLER204_FIRST_REG 0x4c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_0
#define CLK_RST_CONTROLLER204_LAST_REG 0x4c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIB_CLR_0
#define CLK_RST_CONTROLLER205_FIRST_REG 0x4c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0
#define CLK_RST_CONTROLLER205_LAST_REG 0x4c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSIB_0
#define CLK_RST_CONTROLLER206_FIRST_REG 0x4c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0
#define CLK_RST_CONTROLLER206_LAST_REG 0x4c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP_0
#define CLK_RST_CONTROLLER207_FIRST_REG 0x4d0000 // CLK_RST_CONTROLLER_RST_DEV_ENTROPY_0
#define CLK_RST_CONTROLLER207_LAST_REG 0x4d0008 // CLK_RST_CONTROLLER_RST_DEV_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER208_FIRST_REG 0x4d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_0
#define CLK_RST_CONTROLLER208_LAST_REG 0x4d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ENTROPY_CLR_0
#define CLK_RST_CONTROLLER209_FIRST_REG 0x4d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER209_LAST_REG 0x4d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ENTROPY_0
#define CLK_RST_CONTROLLER210_FIRST_REG 0x4d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER210_LAST_REG 0x4d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_ENTROPY_0
#define CLK_RST_CONTROLLER211_FIRST_REG 0x4e0000 // CLK_RST_CONTROLLER_RST_DEV_DVFS_0
#define CLK_RST_CONTROLLER211_LAST_REG 0x4e0008 // CLK_RST_CONTROLLER_RST_DEV_DVFS_CLR_0
#define CLK_RST_CONTROLLER212_FIRST_REG 0x4e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_0
#define CLK_RST_CONTROLLER212_LAST_REG 0x4e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DVFS_CLR_0
#define CLK_RST_CONTROLLER213_FIRST_REG 0x4e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER213_LAST_REG 0x4e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DVFS_0
#define CLK_RST_CONTROLLER214_FIRST_REG 0x4e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER214_LAST_REG 0x4e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0
#define CLK_RST_CONTROLLER215_FIRST_REG 0x500000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_0
#define CLK_RST_CONTROLLER215_LAST_REG 0x500008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC1_CLR_0
#define CLK_RST_CONTROLLER216_FIRST_REG 0x501000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER216_LAST_REG 0x501000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC1_0
#define CLK_RST_CONTROLLER217_FIRST_REG 0x502000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER217_LAST_REG 0x502000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1_0
#define CLK_RST_CONTROLLER218_FIRST_REG 0x503000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0
#define CLK_RST_CONTROLLER218_LAST_REG 0x503000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1_0
#define CLK_RST_CONTROLLER219_FIRST_REG 0x510000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_0
#define CLK_RST_CONTROLLER219_LAST_REG 0x510008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC2_CLR_0
#define CLK_RST_CONTROLLER220_FIRST_REG 0x511000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER220_LAST_REG 0x511000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC2_0
#define CLK_RST_CONTROLLER221_FIRST_REG 0x512000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER221_LAST_REG 0x512000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2_0
#define CLK_RST_CONTROLLER222_FIRST_REG 0x513000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0
#define CLK_RST_CONTROLLER222_LAST_REG 0x513000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2_0
#define CLK_RST_CONTROLLER223_FIRST_REG 0x520000 // CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_0
#define CLK_RST_CONTROLLER223_LAST_REG 0x520008 // CLK_RST_CONTROLLER_RST_DEV_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER224_FIRST_REG 0x521000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_0
#define CLK_RST_CONTROLLER224_LAST_REG 0x521008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AUD_MCLK_CLR_0
#define CLK_RST_CONTROLLER225_FIRST_REG 0x522000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER225_LAST_REG 0x522000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AUD_MCLK_0
#define CLK_RST_CONTROLLER226_FIRST_REG 0x523000 // CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER226_LAST_REG 0x523000 // CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK_0
#define CLK_RST_CONTROLLER227_FIRST_REG 0x530000 // CLK_RST_CONTROLLER_RST_DEV_I2C6_0
#define CLK_RST_CONTROLLER227_LAST_REG 0x530008 // CLK_RST_CONTROLLER_RST_DEV_I2C6_CLR_0
#define CLK_RST_CONTROLLER228_FIRST_REG 0x531000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0
#define CLK_RST_CONTROLLER228_LAST_REG 0x531008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_CLR_0
#define CLK_RST_CONTROLLER229_FIRST_REG 0x532000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER229_LAST_REG 0x532000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C6_0
#define CLK_RST_CONTROLLER230_FIRST_REG 0x533000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER230_LAST_REG 0x533000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0
#define CLK_RST_CONTROLLER231_FIRST_REG 0x550000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER231_LAST_REG 0x550008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER232_FIRST_REG 0x551000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER232_LAST_REG 0x551000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER233_FIRST_REG 0x552000 // CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER233_LAST_REG 0x552000 // CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER234_FIRST_REG 0x560000 // CLK_RST_CONTROLLER_RST_DEV_VIC_0
#define CLK_RST_CONTROLLER234_LAST_REG 0x560008 // CLK_RST_CONTROLLER_RST_DEV_VIC_CLR_0
#define CLK_RST_CONTROLLER235_FIRST_REG 0x561000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_0
#define CLK_RST_CONTROLLER235_LAST_REG 0x561008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VIC_CLR_0
#define CLK_RST_CONTROLLER236_FIRST_REG 0x562000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER236_LAST_REG 0x562000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VIC_0
#define CLK_RST_CONTROLLER237_FIRST_REG 0x563000 // CLK_RST_CONTROLLER_CLK_SOURCE_VIC_0
#define CLK_RST_CONTROLLER237_LAST_REG 0x563004 // CLK_RST_CONTROLLER_VIC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER238_FIRST_REG 0x564000 // CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER238_LAST_REG 0x564000 // CLK_RST_CONTROLLER_CLK_SPARE_VIC_0
#define CLK_RST_CONTROLLER239_FIRST_REG 0x570000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER239_LAST_REG 0x570008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SDMMC_LEGACY_TM_CLR_0
#define CLK_RST_CONTROLLER240_FIRST_REG 0x571000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER240_LAST_REG 0x571000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER241_FIRST_REG 0x572000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER241_LAST_REG 0x572000 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM_0
#define CLK_RST_CONTROLLER242_FIRST_REG 0x580000 // CLK_RST_CONTROLLER_RST_DEV_NVDEC_0
#define CLK_RST_CONTROLLER242_LAST_REG 0x580008 // CLK_RST_CONTROLLER_RST_DEV_NVDEC_CLR_0
#define CLK_RST_CONTROLLER243_FIRST_REG 0x581000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_0
#define CLK_RST_CONTROLLER243_LAST_REG 0x581008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDEC_CLR_0
#define CLK_RST_CONTROLLER244_FIRST_REG 0x582000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER244_LAST_REG 0x582000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDEC_0
#define CLK_RST_CONTROLLER245_FIRST_REG 0x583000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC_0
#define CLK_RST_CONTROLLER245_LAST_REG 0x583004 // CLK_RST_CONTROLLER_NVDEC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER246_FIRST_REG 0x584000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER246_LAST_REG 0x584000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDEC_0
#define CLK_RST_CONTROLLER247_FIRST_REG 0x590000 // CLK_RST_CONTROLLER_RST_DEV_NVJPG_0
#define CLK_RST_CONTROLLER247_LAST_REG 0x590008 // CLK_RST_CONTROLLER_RST_DEV_NVJPG_CLR_0
#define CLK_RST_CONTROLLER248_FIRST_REG 0x591000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_0
#define CLK_RST_CONTROLLER248_LAST_REG 0x591008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVJPG_CLR_0
#define CLK_RST_CONTROLLER249_FIRST_REG 0x592000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER249_LAST_REG 0x592000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVJPG_0
#define CLK_RST_CONTROLLER250_FIRST_REG 0x593000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG_0
#define CLK_RST_CONTROLLER250_LAST_REG 0x593004 // CLK_RST_CONTROLLER_NVJPG_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER251_FIRST_REG 0x5a0000 // CLK_RST_CONTROLLER_RST_DEV_NVENC_0
#define CLK_RST_CONTROLLER251_LAST_REG 0x5a0008 // CLK_RST_CONTROLLER_RST_DEV_NVENC_CLR_0
#define CLK_RST_CONTROLLER252_FIRST_REG 0x5a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_0
#define CLK_RST_CONTROLLER252_LAST_REG 0x5a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVENC_CLR_0
#define CLK_RST_CONTROLLER253_FIRST_REG 0x5a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER253_LAST_REG 0x5a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVENC_0
#define CLK_RST_CONTROLLER254_FIRST_REG 0x5a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVENC_0
#define CLK_RST_CONTROLLER254_LAST_REG 0x5a3004 // CLK_RST_CONTROLLER_NVENC_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER255_FIRST_REG 0x5a4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER255_LAST_REG 0x5a4000 // CLK_RST_CONTROLLER_CLK_SPARE_NVENC_0
#define CLK_RST_CONTROLLER256_FIRST_REG 0x5b0000 // CLK_RST_CONTROLLER_PLLA1_BASE_0
#define CLK_RST_CONTROLLER256_LAST_REG 0x5b0018 // CLK_RST_CONTROLLER_PLLA1_MISC_4_0
#define CLK_RST_CONTROLLER257_FIRST_REG 0x5c0000 // CLK_RST_CONTROLLER_RST_DEV_QSPI_0
#define CLK_RST_CONTROLLER257_LAST_REG 0x5c0008 // CLK_RST_CONTROLLER_RST_DEV_QSPI_CLR_0
#define CLK_RST_CONTROLLER258_FIRST_REG 0x5c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_0
#define CLK_RST_CONTROLLER258_LAST_REG 0x5c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_QSPI_CLR_0
#define CLK_RST_CONTROLLER259_FIRST_REG 0x5c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0
#define CLK_RST_CONTROLLER259_LAST_REG 0x5c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_QSPI_0
#define CLK_RST_CONTROLLER260_FIRST_REG 0x5c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0
#define CLK_RST_CONTROLLER260_LAST_REG 0x5c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_QSPI_0
#define CLK_RST_CONTROLLER261_FIRST_REG 0x5d0000 // CLK_RST_CONTROLLER_RST_DEV_VI_I2C_0
#define CLK_RST_CONTROLLER261_LAST_REG 0x5d0008 // CLK_RST_CONTROLLER_RST_DEV_VI_I2C_CLR_0
#define CLK_RST_CONTROLLER262_FIRST_REG 0x5d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_0
#define CLK_RST_CONTROLLER262_LAST_REG 0x5d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_VI_I2C_CLR_0
#define CLK_RST_CONTROLLER263_FIRST_REG 0x5d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0
#define CLK_RST_CONTROLLER263_LAST_REG 0x5d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_VI_I2C_0
#define CLK_RST_CONTROLLER264_FIRST_REG 0x5d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0
#define CLK_RST_CONTROLLER264_LAST_REG 0x5d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C_0
#define CLK_RST_CONTROLLER265_FIRST_REG 0x5e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER265_LAST_REG 0x5e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_USB2_HSIC_TRK_CLR_0
#define CLK_RST_CONTROLLER266_FIRST_REG 0x5e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER266_LAST_REG 0x5e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER267_FIRST_REG 0x5e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER267_LAST_REG 0x5e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK_0
#define CLK_RST_CONTROLLER268_FIRST_REG 0x5f0000 // CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP_0
#define CLK_RST_CONTROLLER268_LAST_REG 0x5f0008 // CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT_0
#define CLK_RST_CONTROLLER269_FIRST_REG 0x600000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_0
#define CLK_RST_CONTROLLER269_LAST_REG 0x600008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MAUD_CLR_0
#define CLK_RST_CONTROLLER270_FIRST_REG 0x601000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER270_LAST_REG 0x601000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MAUD_0
#define CLK_RST_CONTROLLER271_FIRST_REG 0x602000 // CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER271_LAST_REG 0x602000 // CLK_RST_CONTROLLER_CLK_SOURCE_MAUD_0
#define CLK_RST_CONTROLLER272_FIRST_REG 0x610000 // CLK_RST_CONTROLLER_RST_DEV_TSECB_0
#define CLK_RST_CONTROLLER272_LAST_REG 0x610008 // CLK_RST_CONTROLLER_RST_DEV_TSECB_CLR_0
#define CLK_RST_CONTROLLER273_FIRST_REG 0x611000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_0
#define CLK_RST_CONTROLLER273_LAST_REG 0x611008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSECB_CLR_0
#define CLK_RST_CONTROLLER274_FIRST_REG 0x612000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER274_LAST_REG 0x612000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSECB_0
#define CLK_RST_CONTROLLER275_FIRST_REG 0x613000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSECB_0
#define CLK_RST_CONTROLLER275_LAST_REG 0x613004 // CLK_RST_CONTROLLER_TSECB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER276_FIRST_REG 0x620000 // CLK_RST_CONTROLLER_RST_DEV_ADSP_0
#define CLK_RST_CONTROLLER276_LAST_REG 0x620008 // CLK_RST_CONTROLLER_RST_DEV_ADSP_CLR_0
#define CLK_RST_CONTROLLER277_FIRST_REG 0x621000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_0
#define CLK_RST_CONTROLLER277_LAST_REG 0x621008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ADSP_CLR_0
#define CLK_RST_CONTROLLER278_FIRST_REG 0x622000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER278_LAST_REG 0x622000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ADSP_0
#define CLK_RST_CONTROLLER279_FIRST_REG 0x623000 // CLK_RST_CONTROLLER_ACLK_BURST_POLICY_0
#define CLK_RST_CONTROLLER279_LAST_REG 0x623004 // CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER_0
#define CLK_RST_CONTROLLER280_FIRST_REG 0x650000 // CLK_RST_CONTROLLER_RST_DEV_MPHY_0
#define CLK_RST_CONTROLLER280_LAST_REG 0x650008 // CLK_RST_CONTROLLER_RST_DEV_MPHY_CLR_0
#define CLK_RST_CONTROLLER281_FIRST_REG 0x651000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_0
#define CLK_RST_CONTROLLER281_LAST_REG 0x651008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MPHY_CLR_0
#define CLK_RST_CONTROLLER282_FIRST_REG 0x652000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER282_LAST_REG 0x652000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MPHY_0
#define CLK_RST_CONTROLLER283_FIRST_REG 0x653000 // CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED_0
#define CLK_RST_CONTROLLER283_LAST_REG 0x653010 // CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB_0
#define CLK_RST_CONTROLLER284_FIRST_REG 0x654000 // CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER284_LAST_REG 0x654000 // CLK_RST_CONTROLLER_CLK_MPHY_MISC_0
#define CLK_RST_CONTROLLER285_FIRST_REG 0x655000 // CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER285_LAST_REG 0x655000 // CLK_RST_CONTROLLER_CLK_SPARE_MPHY_0
#define CLK_RST_CONTROLLER286_FIRST_REG 0x660000 // CLK_RST_CONTROLLER_PLLNVCSI_BASE_0
#define CLK_RST_CONTROLLER286_LAST_REG 0x660014 // CLK_RST_CONTROLLER_PLLNVCSI_MISC_4_0
#define CLK_RST_CONTROLLER287_FIRST_REG 0x670000 // CLK_RST_CONTROLLER_PLLDISPHUB_BASE_0
#define CLK_RST_CONTROLLER287_LAST_REG 0x670014 // CLK_RST_CONTROLLER_PLLDISPHUB_MISC_4_0
#define CLK_RST_CONTROLLER288_FIRST_REG 0x680000 // CLK_RST_CONTROLLER_PLLD3_BASE_0
#define CLK_RST_CONTROLLER288_LAST_REG 0x680014 // CLK_RST_CONTROLLER_PLLD3_SS_CTRL2_0
#define CLK_RST_CONTROLLER289_FIRST_REG 0x690000 // CLK_RST_CONTROLLER_PLLMSB_BASE_0
#define CLK_RST_CONTROLLER289_LAST_REG 0x690028 // CLK_RST_CONTROLLER_PLLMSBB_SS_CTRL2_0
#define CLK_RST_CONTROLLER290_FIRST_REG 0x6a0000 // CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_0
#define CLK_RST_CONTROLLER290_LAST_REG 0x6a0008 // CLK_RST_CONTROLLER_RST_DEV_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER291_FIRST_REG 0x6a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_0
#define CLK_RST_CONTROLLER291_LAST_REG 0x6a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AXI_CBB_CLR_0
#define CLK_RST_CONTROLLER292_FIRST_REG 0x6a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER292_LAST_REG 0x6a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AXI_CBB_0
#define CLK_RST_CONTROLLER293_FIRST_REG 0x6a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB_0
#define CLK_RST_CONTROLLER293_LAST_REG 0x6a3008 // CLK_RST_CONTROLLER_AXI_CBB_SUPER_CLK_DIVIDER_HW_CFG_0
#define CLK_RST_CONTROLLER294_FIRST_REG 0x6b0000 // CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER294_LAST_REG 0x6b0000 // CLK_RST_CONTROLLER_AXI_CBB_CENTRAL_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER295_FIRST_REG 0x6c0000 // CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER295_LAST_REG 0x6c0000 // CLK_RST_CONTROLLER_AXI_CBB_AON_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER296_FIRST_REG 0x6d0000 // CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER296_LAST_REG 0x6d0000 // CLK_RST_CONTROLLER_AXI_CBB_PCIE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER297_FIRST_REG 0x6e0000 // CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER297_LAST_REG 0x6e0000 // CLK_RST_CONTROLLER_AXI_CBB_CCPLEX_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER298_FIRST_REG 0x6f0000 // CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER298_LAST_REG 0x6f0000 // CLK_RST_CONTROLLER_AXI_CBB_GPU_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER299_FIRST_REG 0x700000 // CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER299_LAST_REG 0x700000 // CLK_RST_CONTROLLER_AXI_CBB_APE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER300_FIRST_REG 0x710000 // CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER300_LAST_REG 0x710000 // CLK_RST_CONTROLLER_AXI_CBB_BPMP_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER301_FIRST_REG 0x720000 // CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER301_LAST_REG 0x720000 // CLK_RST_CONTROLLER_AXI_CBB_SCE_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER302_FIRST_REG 0x730000 // CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER302_LAST_REG 0x730000 // CLK_RST_CONTROLLER_AXI2APB_1_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER303_FIRST_REG 0x740000 // CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER303_LAST_REG 0x740000 // CLK_RST_CONTROLLER_AXI2APB_2_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER304_FIRST_REG 0x750000 // CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER304_LAST_REG 0x750000 // CLK_RST_CONTROLLER_AXI2APB_3_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER305_FIRST_REG 0x760000 // CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER305_LAST_REG 0x760000 // CLK_RST_CONTROLLER_AXI2APB_4_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER306_FIRST_REG 0x770000 // CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER306_LAST_REG 0x770000 // CLK_RST_CONTROLLER_AXI2APB_5_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER307_FIRST_REG 0x780000 // CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER307_LAST_REG 0x780000 // CLK_RST_CONTROLLER_AXI_CBB_HOST1X_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER308_FIRST_REG 0x7b0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_0
#define CLK_RST_CONTROLLER308_LAST_REG 0x7b0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC3_CLR_0
#define CLK_RST_CONTROLLER309_FIRST_REG 0x7b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER309_LAST_REG 0x7b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC3_0
#define CLK_RST_CONTROLLER310_FIRST_REG 0x7b2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER310_LAST_REG 0x7b2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3_0
#define CLK_RST_CONTROLLER311_FIRST_REG 0x7b3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0
#define CLK_RST_CONTROLLER311_LAST_REG 0x7b3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3_0
#define CLK_RST_CONTROLLER312_FIRST_REG 0x7c0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_0
#define CLK_RST_CONTROLLER312_LAST_REG 0x7c0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC4_CLR_0
#define CLK_RST_CONTROLLER313_FIRST_REG 0x7c1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER313_LAST_REG 0x7c1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC4_0
#define CLK_RST_CONTROLLER314_FIRST_REG 0x7c2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER314_LAST_REG 0x7c2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4_0
#define CLK_RST_CONTROLLER315_FIRST_REG 0x7c3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0
#define CLK_RST_CONTROLLER315_LAST_REG 0x7c3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4_0
#define CLK_RST_CONTROLLER316_FIRST_REG 0x7d0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_0
#define CLK_RST_CONTROLLER316_LAST_REG 0x7d0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK1_CLR_0
#define CLK_RST_CONTROLLER317_FIRST_REG 0x7d1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER317_LAST_REG 0x7d1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK1_0
#define CLK_RST_CONTROLLER318_FIRST_REG 0x7d2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER318_LAST_REG 0x7d2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1_0
#define CLK_RST_CONTROLLER319_FIRST_REG 0x7d3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0
#define CLK_RST_CONTROLLER319_LAST_REG 0x7d3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1_0
#define CLK_RST_CONTROLLER320_FIRST_REG 0x7e0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_0
#define CLK_RST_CONTROLLER320_LAST_REG 0x7e0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSPK2_CLR_0
#define CLK_RST_CONTROLLER321_FIRST_REG 0x7e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER321_LAST_REG 0x7e1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSPK2_0
#define CLK_RST_CONTROLLER322_FIRST_REG 0x7e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER322_LAST_REG 0x7e2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2_0
#define CLK_RST_CONTROLLER323_FIRST_REG 0x7e3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0
#define CLK_RST_CONTROLLER323_LAST_REG 0x7e3000 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2_0
#define CLK_RST_CONTROLLER324_FIRST_REG 0x7f0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_0
#define CLK_RST_CONTROLLER324_LAST_REG 0x7f0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2S6_CLR_0
#define CLK_RST_CONTROLLER325_FIRST_REG 0x7f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER325_LAST_REG 0x7f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2S6_0
#define CLK_RST_CONTROLLER326_FIRST_REG 0x7f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S6_0
#define CLK_RST_CONTROLLER326_LAST_REG 0x7f2004 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6_0
#define CLK_RST_CONTROLLER327_FIRST_REG 0x800000 // CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_0
#define CLK_RST_CONTROLLER327_LAST_REG 0x800008 // CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER328_FIRST_REG 0x801000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_0
#define CLK_RST_CONTROLLER328_LAST_REG 0x801008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_CLR_0
#define CLK_RST_CONTROLLER329_FIRST_REG 0x802000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER329_LAST_REG 0x802000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY0_0
#define CLK_RST_CONTROLLER330_FIRST_REG 0x803000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER330_LAST_REG 0x803000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0_0
#define CLK_RST_CONTROLLER331_FIRST_REG 0x804000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER331_LAST_REG 0x804000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP_0
#define CLK_RST_CONTROLLER332_FIRST_REG 0x805000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB_0
#define CLK_RST_CONTROLLER332_LAST_REG 0x805004 // CLK_RST_CONTROLLER_NVDISPLAYHUB_SUPER_CLK_DIVIDER_0
#define CLK_RST_CONTROLLER333_FIRST_REG 0x806000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER333_LAST_REG 0x806000 // CLK_RST_CONTROLLER_CLK_SPARE_NVDISPLAY0_0
#define CLK_RST_CONTROLLER334_FIRST_REG 0x810000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_0
#define CLK_RST_CONTROLLER334_LAST_REG 0x810008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY1_CLR_0
#define CLK_RST_CONTROLLER335_FIRST_REG 0x811000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER335_LAST_REG 0x811000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY1_0
#define CLK_RST_CONTROLLER336_FIRST_REG 0x812000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER336_LAST_REG 0x812000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1_0
#define CLK_RST_CONTROLLER337_FIRST_REG 0x820000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_0
#define CLK_RST_CONTROLLER337_LAST_REG 0x820008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY2_CLR_0
#define CLK_RST_CONTROLLER338_FIRST_REG 0x821000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER338_LAST_REG 0x821000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVDISPLAY2_0
#define CLK_RST_CONTROLLER339_FIRST_REG 0x822000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER339_LAST_REG 0x822000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2_0
#define CLK_RST_CONTROLLER340_FIRST_REG 0x840000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_0
#define CLK_RST_CONTROLLER340_LAST_REG 0x840008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER341_FIRST_REG 0x841000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_0
#define CLK_RST_CONTROLLER341_LAST_REG 0x841008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL0_CLR_0
#define CLK_RST_CONTROLLER342_FIRST_REG 0x842000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER342_LAST_REG 0x842000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL0_0
#define CLK_RST_CONTROLLER343_FIRST_REG 0x843000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER343_LAST_REG 0x843000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL0_0
#define CLK_RST_CONTROLLER344_FIRST_REG 0x850000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_0
#define CLK_RST_CONTROLLER344_LAST_REG 0x850008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER345_FIRST_REG 0x851000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_0
#define CLK_RST_CONTROLLER345_LAST_REG 0x851008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL1_CLR_0
#define CLK_RST_CONTROLLER346_FIRST_REG 0x852000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER346_LAST_REG 0x852000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL1_0
#define CLK_RST_CONTROLLER347_FIRST_REG 0x853000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER347_LAST_REG 0x853000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL1_0
#define CLK_RST_CONTROLLER348_FIRST_REG 0x860000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_0
#define CLK_RST_CONTROLLER348_LAST_REG 0x860008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER349_FIRST_REG 0x861000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_0
#define CLK_RST_CONTROLLER349_LAST_REG 0x861008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL2_CLR_0
#define CLK_RST_CONTROLLER350_FIRST_REG 0x862000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER350_LAST_REG 0x862000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL2_0
#define CLK_RST_CONTROLLER351_FIRST_REG 0x863000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER351_LAST_REG 0x863000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL2_0
#define CLK_RST_CONTROLLER352_FIRST_REG 0x870000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_0
#define CLK_RST_CONTROLLER352_LAST_REG 0x870008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER353_FIRST_REG 0x871000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_0
#define CLK_RST_CONTROLLER353_LAST_REG 0x871008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL3_CLR_0
#define CLK_RST_CONTROLLER354_FIRST_REG 0x872000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER354_LAST_REG 0x872000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL3_0
#define CLK_RST_CONTROLLER355_FIRST_REG 0x873000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER355_LAST_REG 0x873000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL3_0
#define CLK_RST_CONTROLLER356_FIRST_REG 0x880000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_0
#define CLK_RST_CONTROLLER356_LAST_REG 0x880008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER357_FIRST_REG 0x881000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_0
#define CLK_RST_CONTROLLER357_LAST_REG 0x881008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL4_CLR_0
#define CLK_RST_CONTROLLER358_FIRST_REG 0x882000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER358_LAST_REG 0x882000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL4_0
#define CLK_RST_CONTROLLER359_FIRST_REG 0x883000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER359_LAST_REG 0x883000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL4_0
#define CLK_RST_CONTROLLER360_FIRST_REG 0x890000 // CLK_RST_CONTROLLER_RST_DEV_TACH_0
#define CLK_RST_CONTROLLER360_LAST_REG 0x890008 // CLK_RST_CONTROLLER_RST_DEV_TACH_CLR_0
#define CLK_RST_CONTROLLER361_FIRST_REG 0x891000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_0
#define CLK_RST_CONTROLLER361_LAST_REG 0x891008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TACH_CLR_0
#define CLK_RST_CONTROLLER362_FIRST_REG 0x892000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER362_LAST_REG 0x892000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TACH_0
#define CLK_RST_CONTROLLER363_FIRST_REG 0x893000 // CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER363_LAST_REG 0x893000 // CLK_RST_CONTROLLER_CLK_SOURCE_TACH_0
#define CLK_RST_CONTROLLER364_FIRST_REG 0x8a0000 // CLK_RST_CONTROLLER_RST_DEV_EQOS_0
#define CLK_RST_CONTROLLER364_LAST_REG 0x8a0008 // CLK_RST_CONTROLLER_RST_DEV_EQOS_CLR_0
#define CLK_RST_CONTROLLER365_FIRST_REG 0x8a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_0
#define CLK_RST_CONTROLLER365_LAST_REG 0x8a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_CLR_0
#define CLK_RST_CONTROLLER366_FIRST_REG 0x8a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER366_LAST_REG 0x8a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_0
#define CLK_RST_CONTROLLER367_FIRST_REG 0x8a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0
#define CLK_RST_CONTROLLER367_LAST_REG 0x8a3008 // CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK_0
#define CLK_RST_CONTROLLER368_FIRST_REG 0x8b0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_0
#define CLK_RST_CONTROLLER368_LAST_REG 0x8b0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EQOS_RX_CLR_0
#define CLK_RST_CONTROLLER369_FIRST_REG 0x8b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER369_LAST_REG 0x8b1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EQOS_RX_0
#define CLK_RST_CONTROLLER370_FIRST_REG 0x8c0000 // CLK_RST_CONTROLLER_RST_DEV_EMCSB_0
#define CLK_RST_CONTROLLER370_LAST_REG 0x8c0008 // CLK_RST_CONTROLLER_RST_DEV_EMCSB_CLR_0
#define CLK_RST_CONTROLLER371_FIRST_REG 0x8c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_0
#define CLK_RST_CONTROLLER371_LAST_REG 0x8c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_EMCSB_CLR_0
#define CLK_RST_CONTROLLER372_FIRST_REG 0x8c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER372_LAST_REG 0x8c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_EMCSB_0
#define CLK_RST_CONTROLLER373_FIRST_REG 0x8c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_0
#define CLK_RST_CONTROLLER373_LAST_REG 0x8c3014 // CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB_SAFE_0
#define CLK_RST_CONTROLLER374_FIRST_REG 0x8c4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER374_LAST_REG 0x8c4000 // CLK_RST_CONTROLLER_CLK_SPARE_EMCB_0
#define CLK_RST_CONTROLLER375_FIRST_REG 0x8d0000 // CLK_RST_CONTROLLER_RST_DEV_UFS_0
#define CLK_RST_CONTROLLER375_LAST_REG 0x8d0008 // CLK_RST_CONTROLLER_RST_DEV_UFS_CLR_0
#define CLK_RST_CONTROLLER376_FIRST_REG 0x8d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_0
#define CLK_RST_CONTROLLER376_LAST_REG 0x8d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UFS_CLR_0
#define CLK_RST_CONTROLLER377_FIRST_REG 0x8d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER377_LAST_REG 0x8d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UFS_0
#define CLK_RST_CONTROLLER378_FIRST_REG 0x8d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS_0
#define CLK_RST_CONTROLLER378_LAST_REG 0x8d3004 // CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF_0
#define CLK_RST_CONTROLLER379_FIRST_REG 0x8e0000 // CLK_RST_CONTROLLER_RST_DEV_NVCSI_0
#define CLK_RST_CONTROLLER379_LAST_REG 0x8e0008 // CLK_RST_CONTROLLER_RST_DEV_NVCSI_CLR_0
#define CLK_RST_CONTROLLER380_FIRST_REG 0x8e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_0
#define CLK_RST_CONTROLLER380_LAST_REG 0x8e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_NVCSI_CLR_0
#define CLK_RST_CONTROLLER381_FIRST_REG 0x8e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER381_LAST_REG 0x8e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_NVCSI_0
#define CLK_RST_CONTROLLER382_FIRST_REG 0x8e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI_0
#define CLK_RST_CONTROLLER382_LAST_REG 0x8e3004 // CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP_0
#define CLK_RST_CONTROLLER383_FIRST_REG 0x8f0000 // CLK_RST_CONTROLLER_RST_DEV_I2C7_0
#define CLK_RST_CONTROLLER383_LAST_REG 0x8f0008 // CLK_RST_CONTROLLER_RST_DEV_I2C7_CLR_0
#define CLK_RST_CONTROLLER384_FIRST_REG 0x8f1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0
#define CLK_RST_CONTROLLER384_LAST_REG 0x8f1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_CLR_0
#define CLK_RST_CONTROLLER385_FIRST_REG 0x8f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER385_LAST_REG 0x8f2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C7_0
#define CLK_RST_CONTROLLER386_FIRST_REG 0x8f3000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER386_LAST_REG 0x8f3000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0
#define CLK_RST_CONTROLLER387_FIRST_REG 0x900000 // CLK_RST_CONTROLLER_RST_DEV_I2C9_0
#define CLK_RST_CONTROLLER387_LAST_REG 0x900008 // CLK_RST_CONTROLLER_RST_DEV_I2C9_CLR_0
#define CLK_RST_CONTROLLER388_FIRST_REG 0x901000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_0
#define CLK_RST_CONTROLLER388_LAST_REG 0x901008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C9_CLR_0
#define CLK_RST_CONTROLLER389_FIRST_REG 0x902000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER389_LAST_REG 0x902000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C9_0
#define CLK_RST_CONTROLLER390_FIRST_REG 0x903000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER390_LAST_REG 0x903000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C9_0
#define CLK_RST_CONTROLLER391_FIRST_REG 0x920000 // CLK_RST_CONTROLLER_RST_DEV_I2C12_0
#define CLK_RST_CONTROLLER391_LAST_REG 0x920008 // CLK_RST_CONTROLLER_RST_DEV_I2C12_CLR_0
#define CLK_RST_CONTROLLER392_FIRST_REG 0x921000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_0
#define CLK_RST_CONTROLLER392_LAST_REG 0x921008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C12_CLR_0
#define CLK_RST_CONTROLLER393_FIRST_REG 0x922000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER393_LAST_REG 0x922000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C12_0
#define CLK_RST_CONTROLLER394_FIRST_REG 0x923000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER394_LAST_REG 0x923000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C12_0
#define CLK_RST_CONTROLLER395_FIRST_REG 0x930000 // CLK_RST_CONTROLLER_RST_DEV_I2C13_0
#define CLK_RST_CONTROLLER395_LAST_REG 0x930008 // CLK_RST_CONTROLLER_RST_DEV_I2C13_CLR_0
#define CLK_RST_CONTROLLER396_FIRST_REG 0x931000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_0
#define CLK_RST_CONTROLLER396_LAST_REG 0x931008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C13_CLR_0
#define CLK_RST_CONTROLLER397_FIRST_REG 0x932000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER397_LAST_REG 0x932000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C13_0
#define CLK_RST_CONTROLLER398_FIRST_REG 0x933000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER398_LAST_REG 0x933000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C13_0
#define CLK_RST_CONTROLLER399_FIRST_REG 0x940000 // CLK_RST_CONTROLLER_RST_DEV_I2C14_0
#define CLK_RST_CONTROLLER399_LAST_REG 0x940008 // CLK_RST_CONTROLLER_RST_DEV_I2C14_CLR_0
#define CLK_RST_CONTROLLER400_FIRST_REG 0x941000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_0
#define CLK_RST_CONTROLLER400_LAST_REG 0x941008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C14_CLR_0
#define CLK_RST_CONTROLLER401_FIRST_REG 0x942000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER401_LAST_REG 0x942000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C14_0
#define CLK_RST_CONTROLLER402_FIRST_REG 0x943000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER402_LAST_REG 0x943000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C14_0
#define CLK_RST_CONTROLLER403_FIRST_REG 0x950000 // CLK_RST_CONTROLLER_RST_DEV_PWM1_0
#define CLK_RST_CONTROLLER403_LAST_REG 0x950008 // CLK_RST_CONTROLLER_RST_DEV_PWM1_CLR_0
#define CLK_RST_CONTROLLER404_FIRST_REG 0x951000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_0
#define CLK_RST_CONTROLLER404_LAST_REG 0x951008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM1_CLR_0
#define CLK_RST_CONTROLLER405_FIRST_REG 0x952000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER405_LAST_REG 0x952000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM1_0
#define CLK_RST_CONTROLLER406_FIRST_REG 0x953000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER406_LAST_REG 0x953000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM1_0
#define CLK_RST_CONTROLLER407_FIRST_REG 0x960000 // CLK_RST_CONTROLLER_RST_DEV_PWM2_0
#define CLK_RST_CONTROLLER407_LAST_REG 0x960008 // CLK_RST_CONTROLLER_RST_DEV_PWM2_CLR_0
#define CLK_RST_CONTROLLER408_FIRST_REG 0x961000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_0
#define CLK_RST_CONTROLLER408_LAST_REG 0x961008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM2_CLR_0
#define CLK_RST_CONTROLLER409_FIRST_REG 0x962000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER409_LAST_REG 0x962000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM2_0
#define CLK_RST_CONTROLLER410_FIRST_REG 0x963000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER410_LAST_REG 0x963000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM2_0
#define CLK_RST_CONTROLLER411_FIRST_REG 0x970000 // CLK_RST_CONTROLLER_RST_DEV_PWM3_0
#define CLK_RST_CONTROLLER411_LAST_REG 0x970008 // CLK_RST_CONTROLLER_RST_DEV_PWM3_CLR_0
#define CLK_RST_CONTROLLER412_FIRST_REG 0x971000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_0
#define CLK_RST_CONTROLLER412_LAST_REG 0x971008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM3_CLR_0
#define CLK_RST_CONTROLLER413_FIRST_REG 0x972000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER413_LAST_REG 0x972000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM3_0
#define CLK_RST_CONTROLLER414_FIRST_REG 0x973000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER414_LAST_REG 0x973000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM3_0
#define CLK_RST_CONTROLLER415_FIRST_REG 0x990000 // CLK_RST_CONTROLLER_RST_DEV_PWM5_0
#define CLK_RST_CONTROLLER415_LAST_REG 0x990008 // CLK_RST_CONTROLLER_RST_DEV_PWM5_CLR_0
#define CLK_RST_CONTROLLER416_FIRST_REG 0x991000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_0
#define CLK_RST_CONTROLLER416_LAST_REG 0x991008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM5_CLR_0
#define CLK_RST_CONTROLLER417_FIRST_REG 0x992000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER417_LAST_REG 0x992000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM5_0
#define CLK_RST_CONTROLLER418_FIRST_REG 0x993000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER418_LAST_REG 0x993000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM5_0
#define CLK_RST_CONTROLLER419_FIRST_REG 0x9a0000 // CLK_RST_CONTROLLER_RST_DEV_PWM6_0
#define CLK_RST_CONTROLLER419_LAST_REG 0x9a0008 // CLK_RST_CONTROLLER_RST_DEV_PWM6_CLR_0
#define CLK_RST_CONTROLLER420_FIRST_REG 0x9a1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_0
#define CLK_RST_CONTROLLER420_LAST_REG 0x9a1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM6_CLR_0
#define CLK_RST_CONTROLLER421_FIRST_REG 0x9a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER421_LAST_REG 0x9a2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM6_0
#define CLK_RST_CONTROLLER422_FIRST_REG 0x9a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER422_LAST_REG 0x9a3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM6_0
#define CLK_RST_CONTROLLER423_FIRST_REG 0x9b0000 // CLK_RST_CONTROLLER_RST_DEV_PWM7_0
#define CLK_RST_CONTROLLER423_LAST_REG 0x9b0008 // CLK_RST_CONTROLLER_RST_DEV_PWM7_CLR_0
#define CLK_RST_CONTROLLER424_FIRST_REG 0x9b1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_0
#define CLK_RST_CONTROLLER424_LAST_REG 0x9b1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM7_CLR_0
#define CLK_RST_CONTROLLER425_FIRST_REG 0x9b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER425_LAST_REG 0x9b2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM7_0
#define CLK_RST_CONTROLLER426_FIRST_REG 0x9b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER426_LAST_REG 0x9b3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM7_0
#define CLK_RST_CONTROLLER427_FIRST_REG 0x9c0000 // CLK_RST_CONTROLLER_RST_DEV_PWM8_0
#define CLK_RST_CONTROLLER427_LAST_REG 0x9c0008 // CLK_RST_CONTROLLER_RST_DEV_PWM8_CLR_0
#define CLK_RST_CONTROLLER428_FIRST_REG 0x9c1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_0
#define CLK_RST_CONTROLLER428_LAST_REG 0x9c1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM8_CLR_0
#define CLK_RST_CONTROLLER429_FIRST_REG 0x9c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER429_LAST_REG 0x9c2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM8_0
#define CLK_RST_CONTROLLER430_FIRST_REG 0x9c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER430_LAST_REG 0x9c3000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM8_0
#define CLK_RST_CONTROLLER431_FIRST_REG 0x9d0000 // CLK_RST_CONTROLLER_RST_DEV_UARTE_0
#define CLK_RST_CONTROLLER431_LAST_REG 0x9d0008 // CLK_RST_CONTROLLER_RST_DEV_UARTE_CLR_0
#define CLK_RST_CONTROLLER432_FIRST_REG 0x9d1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_0
#define CLK_RST_CONTROLLER432_LAST_REG 0x9d1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTE_CLR_0
#define CLK_RST_CONTROLLER433_FIRST_REG 0x9d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER433_LAST_REG 0x9d2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTE_0
#define CLK_RST_CONTROLLER434_FIRST_REG 0x9d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER434_LAST_REG 0x9d3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0
#define CLK_RST_CONTROLLER435_FIRST_REG 0x9e0000 // CLK_RST_CONTROLLER_RST_DEV_UARTF_0
#define CLK_RST_CONTROLLER435_LAST_REG 0x9e0008 // CLK_RST_CONTROLLER_RST_DEV_UARTF_CLR_0
#define CLK_RST_CONTROLLER436_FIRST_REG 0x9e1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0
#define CLK_RST_CONTROLLER436_LAST_REG 0x9e1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_CLR_0
#define CLK_RST_CONTROLLER437_FIRST_REG 0x9e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER437_LAST_REG 0x9e2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTF_0
#define CLK_RST_CONTROLLER438_FIRST_REG 0x9e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER438_LAST_REG 0x9e3000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0
#define CLK_RST_CONTROLLER439_FIRST_REG 0x9f0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_0
#define CLK_RST_CONTROLLER439_LAST_REG 0x9f0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DBGAPB_CLR_0
#define CLK_RST_CONTROLLER440_FIRST_REG 0x9f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER440_LAST_REG 0x9f1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DBGAPB_0
#define CLK_RST_CONTROLLER441_FIRST_REG 0x9f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER441_LAST_REG 0x9f2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0
#define CLK_RST_CONTROLLER442_FIRST_REG 0xa00000 // CLK_RST_CONTROLLER_PLLBPMPCAM_BASE_0
#define CLK_RST_CONTROLLER442_LAST_REG 0xa00014 // CLK_RST_CONTROLLER_PLLBPMPCAM_MISC_4_0
#define CLK_RST_CONTROLLER443_FIRST_REG 0xa01000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER443_LAST_REG 0xa01000 // CLK_RST_CONTROLLER_CLK_SPARE_BPMP_0
#define CLK_RST_CONTROLLER444_FIRST_REG 0xa10000 // CLK_RST_CONTROLLER_RST_DEV_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER444_LAST_REG 0xa1005c // CLK_RST_CONTROLLER_RST_DEV_BPMP_GTE_CLR_0
#define CLK_RST_CONTROLLER445_FIRST_REG 0xa11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER445_LAST_REG 0xa11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER446_FIRST_REG 0xa12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER446_LAST_REG 0xa12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER447_FIRST_REG 0xa13000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_0
#define CLK_RST_CONTROLLER447_LAST_REG 0xa13008 // CLK_RST_CONTROLLER_BPMP_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER448_FIRST_REG 0xa20000 // CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_0
#define CLK_RST_CONTROLLER448_LAST_REG 0xa20008 // CLK_RST_CONTROLLER_RST_DEV_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER449_FIRST_REG 0xa21000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_0
#define CLK_RST_CONTROLLER449_LAST_REG 0xa21008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_BPMP_APB_CLR_0
#define CLK_RST_CONTROLLER450_FIRST_REG 0xa22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER450_LAST_REG 0xa22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_BPMP_APB_0
#define CLK_RST_CONTROLLER451_FIRST_REG 0xa23000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER451_LAST_REG 0xa23000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB_0
#define CLK_RST_CONTROLLER452_FIRST_REG 0xa30000 // CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_0
#define CLK_RST_CONTROLLER452_LAST_REG 0xa30008 // CLK_RST_CONTROLLER_RST_DEV_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER453_FIRST_REG 0xa31000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_0
#define CLK_RST_CONTROLLER453_LAST_REG 0xa31008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SOC_THERM_CLR_0
#define CLK_RST_CONTROLLER454_FIRST_REG 0xa32000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER454_LAST_REG 0xa32000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SOC_THERM_0
#define CLK_RST_CONTROLLER455_FIRST_REG 0xa33000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER455_LAST_REG 0xa33000 // CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM_0
#define CLK_RST_CONTROLLER456_FIRST_REG 0xa40000 // CLK_RST_CONTROLLER_RST_DEV_ACTMON_0
#define CLK_RST_CONTROLLER456_LAST_REG 0xa40008 // CLK_RST_CONTROLLER_RST_DEV_ACTMON_CLR_0
#define CLK_RST_CONTROLLER457_FIRST_REG 0xa41000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_0
#define CLK_RST_CONTROLLER457_LAST_REG 0xa41008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_ACTMON_CLR_0
#define CLK_RST_CONTROLLER458_FIRST_REG 0xa42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER458_LAST_REG 0xa42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_ACTMON_0
#define CLK_RST_CONTROLLER459_FIRST_REG 0xa43000 // CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER459_LAST_REG 0xa43000 // CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON_0
#define CLK_RST_CONTROLLER460_FIRST_REG 0xa50000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_0
#define CLK_RST_CONTROLLER460_LAST_REG 0xa50008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSENSOR_CLR_0
#define CLK_RST_CONTROLLER461_FIRST_REG 0xa51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER461_LAST_REG 0xa51000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSENSOR_0
#define CLK_RST_CONTROLLER462_FIRST_REG 0xa52000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER462_LAST_REG 0xa52000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSENSOR_0
#define CLK_RST_CONTROLLER463_FIRST_REG 0xa60000 // CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER463_LAST_REG 0xa600a0 // CLK_RST_CONTROLLER_BPMP_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER464_FIRST_REG 0xa70000 // CLK_RST_CONTROLLER_BPMP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER464_LAST_REG 0xa70020 // CLK_RST_CONTROLLER_BPMP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER465_FIRST_REG 0xa70040 // CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER465_LAST_REG 0xa7005c // CLK_RST_CONTROLLER_BPMP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER466_FIRST_REG 0xa7006c // CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER466_LAST_REG 0xa70074 // CLK_RST_CONTROLLER_BPMP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER467_FIRST_REG 0xaf0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_0
#define CLK_RST_CONTROLLER467_LAST_REG 0xaf0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SIMON_CLR_0
#define CLK_RST_CONTROLLER468_FIRST_REG 0xaf1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER468_LAST_REG 0xaf1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SIMON_0
#define CLK_RST_CONTROLLER469_FIRST_REG 0xaf2000 // CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER469_LAST_REG 0xaf2000 // CLK_RST_CONTROLLER_CLK_SOURCE_SIMON_0
#define CLK_RST_CONTROLLER470_FIRST_REG 0xaf8000 // CLK_RST_CONTROLLER_BPMP_SCR_SHARED_0
#define CLK_RST_CONTROLLER470_LAST_REG 0xaf8010 // CLK_RST_CONTROLLER_BPMP_SCR_SIMON_0
#define CLK_RST_CONTROLLER471_FIRST_REG 0xb00000 // CLK_RST_CONTROLLER_RST_DEV_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER471_LAST_REG 0xb00068 // CLK_RST_CONTROLLER_RST_DEV_AON_HSP_CLR_0
#define CLK_RST_CONTROLLER472_FIRST_REG 0xb01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER472_LAST_REG 0xb01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER473_FIRST_REG 0xb02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER473_LAST_REG 0xb02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER474_FIRST_REG 0xb03000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0
#define CLK_RST_CONTROLLER474_LAST_REG 0xb0300c // CLK_RST_CONTROLLER_AON_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER475_FIRST_REG 0xb10000 // CLK_RST_CONTROLLER_RST_DEV_CAN1_0
#define CLK_RST_CONTROLLER475_LAST_REG 0xb10008 // CLK_RST_CONTROLLER_RST_DEV_CAN1_CLR_0
#define CLK_RST_CONTROLLER476_FIRST_REG 0xb11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_0
#define CLK_RST_CONTROLLER476_LAST_REG 0xb11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN1_CLR_0
#define CLK_RST_CONTROLLER477_FIRST_REG 0xb12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER477_LAST_REG 0xb12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN1_0
#define CLK_RST_CONTROLLER478_FIRST_REG 0xb13000 // CLK_RST_CONTROLLER_CLK_SOURCE_CAN1_0
#define CLK_RST_CONTROLLER478_LAST_REG 0xb13004 // CLK_RST_CONTROLLER_CAN1_CORE_RATE_0
#define CLK_RST_CONTROLLER479_FIRST_REG 0xb20000 // CLK_RST_CONTROLLER_RST_DEV_CAN2_0
#define CLK_RST_CONTROLLER479_LAST_REG 0xb20008 // CLK_RST_CONTROLLER_RST_DEV_CAN2_CLR_0
#define CLK_RST_CONTROLLER480_FIRST_REG 0xb21000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_0
#define CLK_RST_CONTROLLER480_LAST_REG 0xb21008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_CAN2_CLR_0
#define CLK_RST_CONTROLLER481_FIRST_REG 0xb22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER481_LAST_REG 0xb22000 // CLK_RST_CONTROLLER_BOND_OUT_IP_CAN2_0
#define CLK_RST_CONTROLLER482_FIRST_REG 0xb23000 // CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0
#define CLK_RST_CONTROLLER482_LAST_REG 0xb23004 // CLK_RST_CONTROLLER_CAN2_CORE_RATE_0
#define CLK_RST_CONTROLLER483_FIRST_REG 0xb30000 // CLK_RST_CONTROLLER_RST_DEV_AON_APB_0
#define CLK_RST_CONTROLLER483_LAST_REG 0xb30008 // CLK_RST_CONTROLLER_RST_DEV_AON_APB_CLR_0
#define CLK_RST_CONTROLLER484_FIRST_REG 0xb31000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_0
#define CLK_RST_CONTROLLER484_LAST_REG 0xb31008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_APB_CLR_0
#define CLK_RST_CONTROLLER485_FIRST_REG 0xb32000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER485_LAST_REG 0xb32000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_APB_0
#define CLK_RST_CONTROLLER486_FIRST_REG 0xb33000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER486_LAST_REG 0xb33000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0
#define CLK_RST_CONTROLLER487_FIRST_REG 0xb40000 // CLK_RST_CONTROLLER_RST_DEV_UARTC_0
#define CLK_RST_CONTROLLER487_LAST_REG 0xb40008 // CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0
#define CLK_RST_CONTROLLER488_FIRST_REG 0xb41000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0
#define CLK_RST_CONTROLLER488_LAST_REG 0xb41008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_CLR_0
#define CLK_RST_CONTROLLER489_FIRST_REG 0xb42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER489_LAST_REG 0xb42000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTC_0
#define CLK_RST_CONTROLLER490_FIRST_REG 0xb43000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER490_LAST_REG 0xb43000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
#define CLK_RST_CONTROLLER491_FIRST_REG 0xb50000 // CLK_RST_CONTROLLER_RST_DEV_UARTG_0
#define CLK_RST_CONTROLLER491_LAST_REG 0xb50008 // CLK_RST_CONTROLLER_RST_DEV_UARTG_CLR_0
#define CLK_RST_CONTROLLER492_FIRST_REG 0xb51000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0
#define CLK_RST_CONTROLLER492_LAST_REG 0xb51008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_CLR_0
#define CLK_RST_CONTROLLER493_FIRST_REG 0xb52000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER493_LAST_REG 0xb52000 // CLK_RST_CONTROLLER_BOND_OUT_IP_UARTG_0
#define CLK_RST_CONTROLLER494_FIRST_REG 0xb53000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER494_LAST_REG 0xb53000 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0
#define CLK_RST_CONTROLLER495_FIRST_REG 0xb60000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER495_LAST_REG 0xb60008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_UART_FST_MIPI_CAL_CLR_0
#define CLK_RST_CONTROLLER496_FIRST_REG 0xb61000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER496_LAST_REG 0xb61000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER497_FIRST_REG 0xb62000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER497_LAST_REG 0xb62000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL_0
#define CLK_RST_CONTROLLER498_FIRST_REG 0xb70000 // CLK_RST_CONTROLLER_RST_DEV_I2C2_0
#define CLK_RST_CONTROLLER498_LAST_REG 0xb70008 // CLK_RST_CONTROLLER_RST_DEV_I2C2_CLR_0
#define CLK_RST_CONTROLLER499_FIRST_REG 0xb71000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0
#define CLK_RST_CONTROLLER499_LAST_REG 0xb71008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_CLR_0
#define CLK_RST_CONTROLLER500_FIRST_REG 0xb72000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER500_LAST_REG 0xb72000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C2_0
#define CLK_RST_CONTROLLER501_FIRST_REG 0xb73000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER501_LAST_REG 0xb73000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0
#define CLK_RST_CONTROLLER502_FIRST_REG 0xb80000 // CLK_RST_CONTROLLER_RST_DEV_I2C8_0
#define CLK_RST_CONTROLLER502_LAST_REG 0xb80008 // CLK_RST_CONTROLLER_RST_DEV_I2C8_CLR_0
#define CLK_RST_CONTROLLER503_FIRST_REG 0xb81000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0
#define CLK_RST_CONTROLLER503_LAST_REG 0xb81008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_CLR_0
#define CLK_RST_CONTROLLER504_FIRST_REG 0xb82000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER504_LAST_REG 0xb82000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C8_0
#define CLK_RST_CONTROLLER505_FIRST_REG 0xb83000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER505_LAST_REG 0xb83000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0
#define CLK_RST_CONTROLLER506_FIRST_REG 0xb90000 // CLK_RST_CONTROLLER_RST_DEV_I2C10_0
#define CLK_RST_CONTROLLER506_LAST_REG 0xb90008 // CLK_RST_CONTROLLER_RST_DEV_I2C10_CLR_0
#define CLK_RST_CONTROLLER507_FIRST_REG 0xb91000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0
#define CLK_RST_CONTROLLER507_LAST_REG 0xb91008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_CLR_0
#define CLK_RST_CONTROLLER508_FIRST_REG 0xb92000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER508_LAST_REG 0xb92000 // CLK_RST_CONTROLLER_BOND_OUT_IP_I2C10_0
#define CLK_RST_CONTROLLER509_FIRST_REG 0xb93000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER509_LAST_REG 0xb93000 // CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0
#define CLK_RST_CONTROLLER510_FIRST_REG 0xba0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER510_LAST_REG 0xba0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_CLR_0
#define CLK_RST_CONTROLLER511_FIRST_REG 0xba1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER511_LAST_REG 0xba1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER512_FIRST_REG 0xba2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER512_LAST_REG 0xba2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0
#define CLK_RST_CONTROLLER513_FIRST_REG 0xbb0000 // CLK_RST_CONTROLLER_RST_DEV_SPI2_0
#define CLK_RST_CONTROLLER513_LAST_REG 0xbb0008 // CLK_RST_CONTROLLER_RST_DEV_SPI2_CLR_0
#define CLK_RST_CONTROLLER514_FIRST_REG 0xbb1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0
#define CLK_RST_CONTROLLER514_LAST_REG 0xbb1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_CLR_0
#define CLK_RST_CONTROLLER515_FIRST_REG 0xbb2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER515_LAST_REG 0xbb2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SPI2_0
#define CLK_RST_CONTROLLER516_FIRST_REG 0xbb3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER516_LAST_REG 0xbb3000 // CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0
#define CLK_RST_CONTROLLER517_FIRST_REG 0xbc0000 // CLK_RST_CONTROLLER_RST_DEV_DMIC5_0
#define CLK_RST_CONTROLLER517_LAST_REG 0xbc0008 // CLK_RST_CONTROLLER_RST_DEV_DMIC5_CLR_0
#define CLK_RST_CONTROLLER518_FIRST_REG 0xbc1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0
#define CLK_RST_CONTROLLER518_LAST_REG 0xbc1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_CLR_0
#define CLK_RST_CONTROLLER519_FIRST_REG 0xbc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER519_LAST_REG 0xbc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DMIC5_0
#define CLK_RST_CONTROLLER520_FIRST_REG 0xbc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0
#define CLK_RST_CONTROLLER520_LAST_REG 0xbc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0
#define CLK_RST_CONTROLLER521_FIRST_REG 0xbd0000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_0
#define CLK_RST_CONTROLLER521_LAST_REG 0xbd0008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_TOUCH_CLR_0
#define CLK_RST_CONTROLLER522_FIRST_REG 0xbd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER522_LAST_REG 0xbd1000 // CLK_RST_CONTROLLER_BOND_OUT_IP_AON_TOUCH_0
#define CLK_RST_CONTROLLER523_FIRST_REG 0xbd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER523_LAST_REG 0xbd2000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH_0
#define CLK_RST_CONTROLLER524_FIRST_REG 0xbe0000 // CLK_RST_CONTROLLER_PLLAON_BASE_0
#define CLK_RST_CONTROLLER524_LAST_REG 0xbe0014 // CLK_RST_CONTROLLER_PLLAON_MISC_4_0
#define CLK_RST_CONTROLLER525_FIRST_REG 0xbf0000 // CLK_RST_CONTROLLER_OSC_CTRL_0
#define CLK_RST_CONTROLLER525_LAST_REG 0xbf0014 // CLK_RST_CONTROLLER_MISC_REG0_0
#define CLK_RST_CONTROLLER526_FIRST_REG 0xc00000 // CLK_RST_CONTROLLER_RST_DEV_PWM4_0
#define CLK_RST_CONTROLLER526_LAST_REG 0xc00008 // CLK_RST_CONTROLLER_RST_DEV_PWM4_CLR_0
#define CLK_RST_CONTROLLER527_FIRST_REG 0xc01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_0
#define CLK_RST_CONTROLLER527_LAST_REG 0xc01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_PWM4_CLR_0
#define CLK_RST_CONTROLLER528_FIRST_REG 0xc02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER528_LAST_REG 0xc02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_PWM4_0
#define CLK_RST_CONTROLLER529_FIRST_REG 0xc03000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER529_LAST_REG 0xc03000 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM4_0
#define CLK_RST_CONTROLLER530_FIRST_REG 0xc10000 // CLK_RST_CONTROLLER_RST_DEV_TSCTNAON_0
#define CLK_RST_CONTROLLER530_LAST_REG 0xc10020 // CLK_RST_CONTROLLER_RST_DEV_AON_GTE_CLR_0
#define CLK_RST_CONTROLLER531_FIRST_REG 0xc11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_0
#define CLK_RST_CONTROLLER531_LAST_REG 0xc11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_TSC_CLR_0
#define CLK_RST_CONTROLLER532_FIRST_REG 0xc12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER532_LAST_REG 0xc12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_TSC_0
#define CLK_RST_CONTROLLER533_FIRST_REG 0xc13000 // CLK_RST_CONTROLLER_CLK_SOURCE_TSC_0
#define CLK_RST_CONTROLLER533_LAST_REG 0xc1300c // CLK_RST_CONTROLLER_TSC_OVERRIDE_CFG0_0
#define CLK_RST_CONTROLLER534_FIRST_REG 0xc20000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER534_LAST_REG 0xc20008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_MSS_ENCRYPT_CLR_0
#define CLK_RST_CONTROLLER535_FIRST_REG 0xc21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER535_LAST_REG 0xc21000 // CLK_RST_CONTROLLER_BOND_OUT_IP_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER536_FIRST_REG 0xc22000 // CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER536_LAST_REG 0xc22000 // CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT_0
#define CLK_RST_CONTROLLER537_FIRST_REG 0xc30000 // CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER537_LAST_REG 0xc300e8 // CLK_RST_CONTROLLER_AON_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER538_FIRST_REG 0xcf8000 // CLK_RST_CONTROLLER_AON_SCR_SHARED_0
#define CLK_RST_CONTROLLER538_LAST_REG 0xcf8050 // CLK_RST_CONTROLLER_AON_SCR_TOUCH_0
#define CLK_RST_CONTROLLER539_FIRST_REG 0xd00000 // CLK_RST_CONTROLLER_RST_DEV_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER539_LAST_REG 0xd00068 // CLK_RST_CONTROLLER_RST_DEV_SCE_CFG_CLR_0
#define CLK_RST_CONTROLLER540_FIRST_REG 0xd01000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER540_LAST_REG 0xd01008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_CPU_NIC_CLR_0
#define CLK_RST_CONTROLLER541_FIRST_REG 0xd02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER541_LAST_REG 0xd02000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER542_FIRST_REG 0xd03000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_0
#define CLK_RST_CONTROLLER542_LAST_REG 0xd03008 // CLK_RST_CONTROLLER_SCE_SWR_RESET_CYCLE_COUNT_0
#define CLK_RST_CONTROLLER543_FIRST_REG 0xd10000 // CLK_RST_CONTROLLER_RST_DEV_SCE_APB_0
#define CLK_RST_CONTROLLER543_LAST_REG 0xd10008 // CLK_RST_CONTROLLER_RST_DEV_SCE_APB_CLR_0
#define CLK_RST_CONTROLLER544_FIRST_REG 0xd11000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_0
#define CLK_RST_CONTROLLER544_LAST_REG 0xd11008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_SCE_APB_CLR_0
#define CLK_RST_CONTROLLER545_FIRST_REG 0xd12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0
#define CLK_RST_CONTROLLER545_LAST_REG 0xd12000 // CLK_RST_CONTROLLER_BOND_OUT_IP_SCE_APB_0
#define CLK_RST_CONTROLLER546_FIRST_REG 0xd13000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0
#define CLK_RST_CONTROLLER546_LAST_REG 0xd13000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB_0
#define CLK_RST_CONTROLLER547_FIRST_REG 0xd20000 // CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC_TGT_ACTIVE_OVR_0
#define CLK_RST_CONTROLLER547_LAST_REG 0xd200a0 // CLK_RST_CONTROLLER_SCE_SEQ_DEBUG_0
#define CLK_RST_CONTROLLER548_FIRST_REG 0xd30000 // CLK_RST_CONTROLLER_SCE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER548_LAST_REG 0xd30020 // CLK_RST_CONTROLLER_SCE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER549_FIRST_REG 0xd30040 // CLK_RST_CONTROLLER_SCE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER549_LAST_REG 0xd3005c // CLK_RST_CONTROLLER_SCE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER550_FIRST_REG 0xd3006c // CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER550_LAST_REG 0xd30074 // CLK_RST_CONTROLLER_SCE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER551_FIRST_REG 0xdf8000 // CLK_RST_CONTROLLER_SCE_SCR_SHARED_0
#define CLK_RST_CONTROLLER551_LAST_REG 0xdf8008 // CLK_RST_CONTROLLER_SCE_SCR_DVFS_0
#define CLK_RST_CONTROLLER552_FIRST_REG 0xe10000 // CLK_RST_CONTROLLER_NVDEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER552_LAST_REG 0xe10020 // CLK_RST_CONTROLLER_NVDEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER553_FIRST_REG 0xe10040 // CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER553_LAST_REG 0xe1005c // CLK_RST_CONTROLLER_NVDEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER554_FIRST_REG 0xe1006c // CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER554_LAST_REG 0xe10074 // CLK_RST_CONTROLLER_NVDEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER555_FIRST_REG 0xe20000 // CLK_RST_CONTROLLER_NVJPG_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER555_LAST_REG 0xe20020 // CLK_RST_CONTROLLER_NVJPG_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER556_FIRST_REG 0xe20040 // CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER556_LAST_REG 0xe2005c // CLK_RST_CONTROLLER_NVJPG_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER557_FIRST_REG 0xe2006c // CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER557_LAST_REG 0xe20074 // CLK_RST_CONTROLLER_NVJPG_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER558_FIRST_REG 0xe30000 // CLK_RST_CONTROLLER_TSEC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER558_LAST_REG 0xe30020 // CLK_RST_CONTROLLER_TSEC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER559_FIRST_REG 0xe30040 // CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER559_LAST_REG 0xe3005c // CLK_RST_CONTROLLER_TSEC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER560_FIRST_REG 0xe3006c // CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER560_LAST_REG 0xe30074 // CLK_RST_CONTROLLER_TSEC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER561_FIRST_REG 0xe40000 // CLK_RST_CONTROLLER_TSECB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER561_LAST_REG 0xe40020 // CLK_RST_CONTROLLER_TSECB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER562_FIRST_REG 0xe40040 // CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER562_LAST_REG 0xe4005c // CLK_RST_CONTROLLER_TSECB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER563_FIRST_REG 0xe4006c // CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER563_LAST_REG 0xe40074 // CLK_RST_CONTROLLER_TSECB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER564_FIRST_REG 0xe50000 // CLK_RST_CONTROLLER_VI_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER564_LAST_REG 0xe50020 // CLK_RST_CONTROLLER_VI_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER565_FIRST_REG 0xe50040 // CLK_RST_CONTROLLER_VI_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER565_LAST_REG 0xe5005c // CLK_RST_CONTROLLER_VI_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER566_FIRST_REG 0xe5006c // CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER566_LAST_REG 0xe50074 // CLK_RST_CONTROLLER_VI_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER567_FIRST_REG 0xe60000 // CLK_RST_CONTROLLER_SE_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER567_LAST_REG 0xe60020 // CLK_RST_CONTROLLER_SE_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER568_FIRST_REG 0xe60040 // CLK_RST_CONTROLLER_SE_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER568_LAST_REG 0xe6005c // CLK_RST_CONTROLLER_SE_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER569_FIRST_REG 0xe6006c // CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER569_LAST_REG 0xe60074 // CLK_RST_CONTROLLER_SE_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER570_FIRST_REG 0xe70000 // CLK_RST_CONTROLLER_NVENC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER570_LAST_REG 0xe70020 // CLK_RST_CONTROLLER_NVENC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER571_FIRST_REG 0xe70040 // CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER571_LAST_REG 0xe7005c // CLK_RST_CONTROLLER_NVENC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER572_FIRST_REG 0xe7006c // CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER572_LAST_REG 0xe70074 // CLK_RST_CONTROLLER_NVENC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER573_FIRST_REG 0xe80000 // CLK_RST_CONTROLLER_ISP_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER573_LAST_REG 0xe80020 // CLK_RST_CONTROLLER_ISP_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER574_FIRST_REG 0xe80040 // CLK_RST_CONTROLLER_ISP_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER574_LAST_REG 0xe8005c // CLK_RST_CONTROLLER_ISP_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER575_FIRST_REG 0xe8006c // CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER575_LAST_REG 0xe80074 // CLK_RST_CONTROLLER_ISP_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER576_FIRST_REG 0xe90000 // CLK_RST_CONTROLLER_VIC_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER576_LAST_REG 0xe90020 // CLK_RST_CONTROLLER_VIC_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER577_FIRST_REG 0xe90040 // CLK_RST_CONTROLLER_VIC_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER577_LAST_REG 0xe9005c // CLK_RST_CONTROLLER_VIC_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER578_FIRST_REG 0xe9006c // CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER578_LAST_REG 0xe90074 // CLK_RST_CONTROLLER_VIC_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER579_FIRST_REG 0xec0000 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER579_LAST_REG 0xec0020 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER580_FIRST_REG 0xec0040 // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER580_LAST_REG 0xec005c // CLK_RST_CONTROLLER_NVDISPLAYHUB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER581_FIRST_REG 0xec006c // CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER581_LAST_REG 0xec0074 // CLK_RST_CONTROLLER_NVDISPLAYHUB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER582_FIRST_REG 0xed0000 // CLK_RST_CONTROLLER_AXICBB_NAFLL_CFG1_0
#define CLK_RST_CONTROLLER582_LAST_REG 0xed0020 // CLK_RST_CONTROLLER_AXICBB_NAFLL_SKP_CTRL_0
#define CLK_RST_CONTROLLER583_FIRST_REG 0xed0040 // CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_WRITE_ADDR_0
#define CLK_RST_CONTROLLER583_LAST_REG 0xed005c // CLK_RST_CONTROLLER_AXICBB_NAFLL_LUT_ACK_0
#define CLK_RST_CONTROLLER584_FIRST_REG 0xed006c // CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CFG_0
#define CLK_RST_CONTROLLER584_LAST_REG 0xed0074 // CLK_RST_CONTROLLER_AXICBB_CLK_FR_CNTR_CNT1_0
#define CLK_RST_CONTROLLER585_FIRST_REG 0xfa0000 // CLK_RST_CONTROLLER_RST_DEV_DSIC_0
#define CLK_RST_CONTROLLER585_LAST_REG 0xfa0008 // CLK_RST_CONTROLLER_RST_DEV_DSIC_CLR_0
#define CLK_RST_CONTROLLER586_FIRST_REG 0xfa1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSIC_0
#define CLK_RST_CONTROLLER586_LAST_REG 0xfa100c // CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP_0
#define CLK_RST_CONTROLLER587_FIRST_REG 0xfa2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0
#define CLK_RST_CONTROLLER587_LAST_REG 0xfa2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSIC_0
#define CLK_RST_CONTROLLER588_FIRST_REG 0xfb0000 // CLK_RST_CONTROLLER_RST_DEV_DSID_0
#define CLK_RST_CONTROLLER588_LAST_REG 0xfb0008 // CLK_RST_CONTROLLER_RST_DEV_DSID_CLR_0
#define CLK_RST_CONTROLLER589_FIRST_REG 0xfb1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_0
#define CLK_RST_CONTROLLER589_LAST_REG 0xfb1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_DSID_CLR_0
#define CLK_RST_CONTROLLER590_FIRST_REG 0xfb2000 // CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP_0
#define CLK_RST_CONTROLLER590_LAST_REG 0xfb2004 // CLK_RST_CONTROLLER_BOND_OUT_IP_DSID_0
#define CLK_RST_CONTROLLER591_FIRST_REG 0xfc0000 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_0
#define CLK_RST_CONTROLLER591_LAST_REG 0xfc0008 // CLK_RST_CONTROLLER_RST_DEV_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER592_FIRST_REG 0xfc1000 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_0
#define CLK_RST_CONTROLLER592_LAST_REG 0xfc1008 // CLK_RST_CONTROLLER_CLK_OUT_ENB_GPIO_CTL5_CLR_0
#define CLK_RST_CONTROLLER593_FIRST_REG 0xfc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER593_LAST_REG 0xfc2000 // CLK_RST_CONTROLLER_BOND_OUT_IP_GPIO_CTL5_0
#define CLK_RST_CONTROLLER594_FIRST_REG 0xfc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER594_LAST_REG 0xfc3000 // CLK_RST_CONTROLLER_CLK_SOURCE_GPIO_CTL5_0
#define CLK_RST_CONTROLLER595_FIRST_REG 0xff0090 // CLK_RST_CONTROLLER_SOC_ADC_CTRL_0
#define CLK_RST_CONTROLLER595_LAST_REG 0xff00a4 // CLK_RST_CONTROLLER_SOC_ADC_REF_CLK_CFG_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARCLK_RST_H_INC_
